// SPDX-License-Identifier: GPL-2.0-only // Copyright (c) 2012-2017 ASPEED Technology Inc. // Copyright (c) 2018-2021 Intel Corporation #include <asm/unaligned.h> #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/clkdev.h> #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/jiffies.h> #include <linux/math.h> #include <linux/module.h> #include <linux/of.h> #include <linux/peci.h> #include <linux/platform_device.h> #include <linux/reset.h> /* ASPEED PECI Registers */ /* Control Register */ #define ASPEED_PECI_CTRL … #define ASPEED_PECI_CTRL_SAMPLING_MASK … #define ASPEED_PECI_CTRL_RD_MODE_MASK … #define ASPEED_PECI_CTRL_RD_MODE_DBG … #define ASPEED_PECI_CTRL_RD_MODE_COUNT … #define ASPEED_PECI_CTRL_CLK_SRC_HCLK … #define ASPEED_PECI_CTRL_CLK_DIV_MASK … #define ASPEED_PECI_CTRL_INVERT_OUT … #define ASPEED_PECI_CTRL_INVERT_IN … #define ASPEED_PECI_CTRL_BUS_CONTENTION_EN … #define ASPEED_PECI_CTRL_PECI_EN … #define ASPEED_PECI_CTRL_PECI_CLK_EN … /* Timing Negotiation Register */ #define ASPEED_PECI_TIMING_NEGOTIATION … #define ASPEED_PECI_T_NEGO_MSG_MASK … #define ASPEED_PECI_T_NEGO_ADDR_MASK … /* Command Register */ #define ASPEED_PECI_CMD … #define ASPEED_PECI_CMD_PIN_MONITORING … #define ASPEED_PECI_CMD_STS_MASK … #define ASPEED_PECI_CMD_STS_ADDR_T_NEGO … #define ASPEED_PECI_CMD_IDLE_MASK … #define ASPEED_PECI_CMD_FIRE … /* Read/Write Length Register */ #define ASPEED_PECI_RW_LENGTH … #define ASPEED_PECI_AW_FCS_EN … #define ASPEED_PECI_RD_LEN_MASK … #define ASPEED_PECI_WR_LEN_MASK … #define ASPEED_PECI_TARGET_ADDR_MASK … /* Expected FCS Data Register */ #define ASPEED_PECI_EXPECTED_FCS … #define ASPEED_PECI_EXPECTED_RD_FCS_MASK … #define ASPEED_PECI_EXPECTED_AW_FCS_AUTO_MASK … #define ASPEED_PECI_EXPECTED_WR_FCS_MASK … /* Captured FCS Data Register */ #define ASPEED_PECI_CAPTURED_FCS … #define ASPEED_PECI_CAPTURED_RD_FCS_MASK … #define ASPEED_PECI_CAPTURED_WR_FCS_MASK … /* Interrupt Register */ #define ASPEED_PECI_INT_CTRL … #define ASPEED_PECI_TIMING_NEGO_SEL_MASK … #define ASPEED_PECI_1ST_BIT_OF_ADDR_NEGO … #define ASPEED_PECI_2ND_BIT_OF_ADDR_NEGO … #define ASPEED_PECI_MESSAGE_NEGO … #define ASPEED_PECI_INT_MASK … #define ASPEED_PECI_INT_BUS_TIMEOUT … #define ASPEED_PECI_INT_BUS_CONTENTION … #define ASPEED_PECI_INT_WR_FCS_BAD … #define ASPEED_PECI_INT_WR_FCS_ABORT … #define ASPEED_PECI_INT_CMD_DONE … /* Interrupt Status Register */ #define ASPEED_PECI_INT_STS … #define ASPEED_PECI_INT_TIMING_RESULT_MASK … /* bits[4..0]: Same bit fields in the 'Interrupt Register' */ /* Rx/Tx Data Buffer Registers */ #define ASPEED_PECI_WR_DATA0 … #define ASPEED_PECI_WR_DATA1 … #define ASPEED_PECI_WR_DATA2 … #define ASPEED_PECI_WR_DATA3 … #define ASPEED_PECI_RD_DATA0 … #define ASPEED_PECI_RD_DATA1 … #define ASPEED_PECI_RD_DATA2 … #define ASPEED_PECI_RD_DATA3 … #define ASPEED_PECI_WR_DATA4 … #define ASPEED_PECI_WR_DATA5 … #define ASPEED_PECI_WR_DATA6 … #define ASPEED_PECI_WR_DATA7 … #define ASPEED_PECI_RD_DATA4 … #define ASPEED_PECI_RD_DATA5 … #define ASPEED_PECI_RD_DATA6 … #define ASPEED_PECI_RD_DATA7 … #define ASPEED_PECI_DATA_BUF_SIZE_MAX … /* Timing Negotiation */ #define ASPEED_PECI_CLK_FREQUENCY_MIN … #define ASPEED_PECI_CLK_FREQUENCY_DEFAULT … #define ASPEED_PECI_CLK_FREQUENCY_MAX … #define ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT … /* Timeout */ #define ASPEED_PECI_IDLE_CHECK_TIMEOUT_US … #define ASPEED_PECI_IDLE_CHECK_INTERVAL_US … #define ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT … #define ASPEED_PECI_CMD_TIMEOUT_MS_MAX … #define ASPEED_PECI_CLK_DIV1(msg_timing) … #define ASPEED_PECI_CLK_DIV2(clk_div_exp) … #define ASPEED_PECI_CLK_DIV(msg_timing, clk_div_exp) … struct aspeed_peci { … }; struct clk_aspeed_peci { … }; static void aspeed_peci_controller_enable(struct aspeed_peci *priv) { … } static void aspeed_peci_init_regs(struct aspeed_peci *priv) { … } static int aspeed_peci_check_idle(struct aspeed_peci *priv) { … } static int aspeed_peci_xfer(struct peci_controller *controller, u8 addr, struct peci_request *req) { … } static irqreturn_t aspeed_peci_irq_handler(int irq, void *arg) { … } static void clk_aspeed_peci_find_div_values(unsigned long rate, int *msg_timing, int *clk_div_exp) { … } static int clk_aspeed_peci_get_div(unsigned long rate, const unsigned long *prate) { … } static int clk_aspeed_peci_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) { … } static long clk_aspeed_peci_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { … } static unsigned long clk_aspeed_peci_recalc_rate(struct clk_hw *hw, unsigned long prate) { … } static const struct clk_ops clk_aspeed_peci_ops = …; /* * PECI HW contains a clock divider which is a combination of: * div0: 4 (fixed divider) * div1: x + 1 * div2: 1 << y * In other words, out_clk = in_clk / (div0 * div1 * div2) * The resulting frequency is used by PECI Controller to drive the PECI bus to * negotiate optimal transfer rate. */ static struct clk *devm_aspeed_peci_register_clk_div(struct device *dev, struct clk *parent, struct aspeed_peci *priv) { … } static void aspeed_peci_property_sanitize(struct device *dev, const char *propname, u32 min, u32 max, u32 default_val, u32 *propval) { … } static void aspeed_peci_property_setup(struct aspeed_peci *priv) { … } static const struct peci_controller_ops aspeed_ops = …; static void aspeed_peci_reset_control_release(void *data) { … } static int devm_aspeed_peci_reset_control_deassert(struct device *dev, struct reset_control *rst) { … } static void aspeed_peci_clk_release(void *data) { … } static int devm_aspeed_peci_clk_enable(struct device *dev, struct clk *clk) { … } static int aspeed_peci_probe(struct platform_device *pdev) { … } static const struct of_device_id aspeed_peci_of_table[] = …; MODULE_DEVICE_TABLE(of, aspeed_peci_of_table); static struct platform_driver aspeed_peci_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; MODULE_IMPORT_NS(…);
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