/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2018-2023 HabanaLabs, Ltd. * All Rights Reserved. * */ #ifndef HL_BOOT_IF_H #define HL_BOOT_IF_H #define LKD_HARD_RESET_MAGIC … #define HL_POWER9_HOST_MAGIC … #define BOOT_FIT_SRAM_OFFSET … #define VERSION_MAX_LEN … enum cpu_boot_err { … }; /* * Mask for fatal failures * This mask contains all possible fatal failures, and a dynamic code * will clear the non-relevant ones. */ #define CPU_BOOT_ERR_FATAL_MASK … /* * CPU error bits in BOOT_ERROR registers * * CPU_BOOT_ERR0_DRAM_INIT_FAIL DRAM initialization failed. * DRAM is not reliable to use. * * CPU_BOOT_ERR0_FIT_CORRUPTED FIT data integrity verification of the * image provided by the host has failed. * * CPU_BOOT_ERR0_TS_INIT_FAIL Thermal Sensor initialization failed. * Boot continues as usual, but keep in * mind this is a warning. * * CPU_BOOT_ERR0_DRAM_SKIPPED DRAM initialization has been skipped. * Skipping DRAM initialization has been * requested (e.g. strap, command, etc.) * and FW skipped the DRAM initialization. * Host can initialize the DRAM. * * CPU_BOOT_ERR0_BMC_WAIT_SKIPPED Waiting for BMC data will be skipped. * Meaning the BMC data might not be * available until reset. * * CPU_BOOT_ERR0_NIC_DATA_NOT_RDY NIC data from BMC is not ready. * BMC has not provided the NIC data yet. * Once provided this bit will be cleared. * * CPU_BOOT_ERR0_NIC_FW_FAIL NIC FW loading failed. * The NIC FW loading and initialization * failed. This means NICs are not usable. * * CPU_BOOT_ERR0_SECURITY_NOT_RDY Chip security initialization has been * started, but is not ready yet - chip * cannot be accessed. * * CPU_BOOT_ERR0_SECURITY_FAIL Security related tasks have failed. * The tasks are security init (root of * trust), boot authentication (chain of * trust), data packets authentication. * * CPU_BOOT_ERR0_EFUSE_FAIL Reading from eFuse failed. * The PCI device ID might be wrong. * * CPU_BOOT_ERR0_PRI_IMG_VER_FAIL Verification of primary image failed. * It mean that ppboot checksum * verification for the preboot primary * image has failed to match expected * checksum. Trying to program image again * might solve this. * * CPU_BOOT_ERR0_SEC_IMG_VER_FAIL Verification of secondary image failed. * It mean that ppboot checksum * verification for the preboot secondary * image has failed to match expected * checksum. Trying to program image again * might solve this. * * CPU_BOOT_ERR0_PLL_FAIL PLL settings failed, meaning that one * of the PLLs remains in REF_CLK * * CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL Device is unusable and customer support * should be contacted. * * CPU_BOOT_ERR0_BOOT_FW_CRIT_ERR Critical error was detected during * the execution of ppboot or preboot. * for example: stack overflow. * * CPU_BOOT_ERR0_BINNING_FAIL Binning settings failed, meaning * malfunctioning components might still be * in use. * * CPU_BOOT_ERR0_TPM_FAIL TPM verification flow failed. * * CPU_BOOT_ERR0_TMP_THRESH_INIT_FAIL Failed to set threshold for tmperature * sensor. * * CPU_BOOT_ERR_EEPROM_FAIL Failed reading EEPROM data. Defaults * are used. * * CPU_BOOT_ERR_ENG_ARC_MEM_SCRUB_FAIL Failed scrubbing the Engines/ARCFarm * memories. Boot disabled until reset. * * CPU_BOOT_ERR0_ENABLED Error registers enabled. * This is a main indication that the * running FW populates the error * registers. Meaning the error bits are * not garbage, but actual error statuses. */ #define CPU_BOOT_ERR0_DRAM_INIT_FAIL … #define CPU_BOOT_ERR0_FIT_CORRUPTED … #define CPU_BOOT_ERR0_TS_INIT_FAIL … #define CPU_BOOT_ERR0_DRAM_SKIPPED … #define CPU_BOOT_ERR0_BMC_WAIT_SKIPPED … #define CPU_BOOT_ERR0_NIC_DATA_NOT_RDY … #define CPU_BOOT_ERR0_NIC_FW_FAIL … #define CPU_BOOT_ERR0_SECURITY_NOT_RDY … #define CPU_BOOT_ERR0_SECURITY_FAIL … #define CPU_BOOT_ERR0_EFUSE_FAIL … #define CPU_BOOT_ERR0_PRI_IMG_VER_FAIL … #define CPU_BOOT_ERR0_SEC_IMG_VER_FAIL … #define CPU_BOOT_ERR0_PLL_FAIL … #define CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL … #define CPU_BOOT_ERR0_BOOT_FW_CRIT_ERR … #define CPU_BOOT_ERR0_BINNING_FAIL … #define CPU_BOOT_ERR0_TPM_FAIL … #define CPU_BOOT_ERR0_TMP_THRESH_INIT_FAIL … #define CPU_BOOT_ERR0_EEPROM_FAIL … #define CPU_BOOT_ERR0_ENG_ARC_MEM_SCRUB_FAIL … #define CPU_BOOT_ERR0_ENABLED … #define CPU_BOOT_ERR1_ENABLED … enum cpu_boot_dev_sts { … }; /* * BOOT DEVICE STATUS bits in BOOT_DEVICE_STS registers * * CPU_BOOT_DEV_STS0_SECURITY_EN Security is Enabled. * This is an indication for security * enabled in FW, which means that * all conditions for security are met: * device is indicated as security enabled, * registers are protected, and device * uses keys for image verification. * Initialized in: preboot * * CPU_BOOT_DEV_STS0_DEBUG_EN Debug is enabled. * Enabled when JTAG or DEBUG is enabled * in FW. * Initialized in: preboot * * CPU_BOOT_DEV_STS0_WATCHDOG_EN Watchdog is enabled. * Watchdog is enabled in FW. * Initialized in: preboot * * CPU_BOOT_DEV_STS0_DRAM_INIT_EN DRAM initialization is enabled. * DRAM initialization has been done in FW. * Initialized in: u-boot * * CPU_BOOT_DEV_STS0_BMC_WAIT_EN Waiting for BMC data enabled. * If set, it means that during boot, * FW waited for BMC data. * Initialized in: u-boot * * CPU_BOOT_DEV_STS0_E2E_CRED_EN E2E credits initialized. * FW initialized E2E credits. * Initialized in: u-boot * * CPU_BOOT_DEV_STS0_HBM_CRED_EN HBM credits initialized. * FW initialized HBM credits. * Initialized in: u-boot * * CPU_BOOT_DEV_STS0_RL_EN Rate limiter initialized. * FW initialized rate limiter. * Initialized in: u-boot * * CPU_BOOT_DEV_STS0_SRAM_SCR_EN SRAM scrambler enabled. * FW initialized SRAM scrambler. * Initialized in: linux * * CPU_BOOT_DEV_STS0_DRAM_SCR_EN DRAM scrambler enabled. * FW initialized DRAM scrambler. * Initialized in: u-boot * * CPU_BOOT_DEV_STS0_FW_HARD_RST_EN FW hard reset procedure is enabled. * FW has the hard reset procedure * implemented. This means that FW will * perform hard reset procedure on * receiving the halt-machine event. * Initialized in: preboot, u-boot, linux * * CPU_BOOT_DEV_STS0_PLL_INFO_EN FW retrieval of PLL info is enabled. * Initialized in: linux * * CPU_BOOT_DEV_STS0_SP_SRAM_EN SP SRAM is initialized and available * for use. * Initialized in: preboot * * CPU_BOOT_DEV_STS0_CLK_GATE_EN Clock Gating enabled. * FW initialized Clock Gating. * Initialized in: preboot * * CPU_BOOT_DEV_STS0_HBM_ECC_EN HBM ECC handling Enabled. * FW handles HBM ECC indications. * Initialized in: linux * * CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN Packets ack value used in the armcpd * is set to the PI counter. * Initialized in: linux * * CPU_BOOT_DEV_STS0_FW_LD_COM_EN Flexible FW loading communication * protocol is enabled. * Initialized in: preboot * * CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN FW iATU configuration is enabled. * This bit if set, means the iATU has been * configured and is ready for use. * Initialized in: ppboot * * CPU_BOOT_DEV_STS0_FW_NIC_MAC_EN NIC MAC channels init is done by FW and * any access to them is done via the FW. * Initialized in: linux * * CPU_BOOT_DEV_STS0_DYN_PLL_EN Dynamic PLL configuration is enabled. * FW sends to host a bitmap of supported * PLLs. * Initialized in: linux * * CPU_BOOT_DEV_STS0_GIC_PRIVILEGED_EN GIC access permission only from * previleged entity. FW sets this status * bit for host. If this bit is set then * GIC can not be accessed from host. * Initialized in: linux * * CPU_BOOT_DEV_STS0_EQ_INDEX_EN Event Queue (EQ) index is a running * index for each new event sent to host. * This is used as a method in host to * identify that the waiting event in * queue is actually a new event which * was not served before. * Initialized in: linux * * CPU_BOOT_DEV_STS0_MULTI_IRQ_POLL_EN Use multiple scratchpad interfaces to * prevent IRQs overriding each other. * Initialized in: linux * * CPU_BOOT_DEV_STS0_FW_NIC_STAT_XPCS91_EN * NIC STAT and XPCS91 access is restricted * and is done via FW only. * Initialized in: linux * * CPU_BOOT_DEV_STS0_FW_NIC_STAT_EXT_EN * NIC STAT get all is supported. * Initialized in: linux * * CPU_BOOT_DEV_STS0_IS_IDLE_CHECK_EN * F/W checks if the device is idle by reading defined set * of registers. It returns a bitmask of all the engines, * where a bit is set if the engine is not idle. * Initialized in: linux * * CPU_BOOT_DEV_STS0_MAP_HWMON_EN * If set, means f/w supports proprietary * HWMON enum mapping to cpucp enums. * Initialized in: linux * * CPU_BOOT_DEV_STS0_NIC_MEM_CLEAR_EN * If set, means f/w supports nic hbm memory clear and * tmr,txs hbm memory init. * Initialized in: zephyr-mgmt * * CPU_BOOT_DEV_STS_MMU_PGTBL_DRAM_EN * MMU page tables are located in DRAM. * F/W initializes security settings for MMU * page tables to reside in DRAM. * Initialized in: zephyr-mgmt * * CPU_BOOT_DEV_STS0_ENABLED Device status register enabled. * This is a main indication that the * running FW populates the device status * register. Meaning the device status * bits are not garbage, but actual * statuses. * Initialized in: preboot * */ #define CPU_BOOT_DEV_STS0_SECURITY_EN … #define CPU_BOOT_DEV_STS0_DEBUG_EN … #define CPU_BOOT_DEV_STS0_WATCHDOG_EN … #define CPU_BOOT_DEV_STS0_DRAM_INIT_EN … #define CPU_BOOT_DEV_STS0_BMC_WAIT_EN … #define CPU_BOOT_DEV_STS0_E2E_CRED_EN … #define CPU_BOOT_DEV_STS0_HBM_CRED_EN … #define CPU_BOOT_DEV_STS0_RL_EN … #define CPU_BOOT_DEV_STS0_SRAM_SCR_EN … #define CPU_BOOT_DEV_STS0_DRAM_SCR_EN … #define CPU_BOOT_DEV_STS0_FW_HARD_RST_EN … #define CPU_BOOT_DEV_STS0_PLL_INFO_EN … #define CPU_BOOT_DEV_STS0_SP_SRAM_EN … #define CPU_BOOT_DEV_STS0_CLK_GATE_EN … #define CPU_BOOT_DEV_STS0_HBM_ECC_EN … #define CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN … #define CPU_BOOT_DEV_STS0_FW_LD_COM_EN … #define CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN … #define CPU_BOOT_DEV_STS0_FW_NIC_MAC_EN … #define CPU_BOOT_DEV_STS0_DYN_PLL_EN … #define CPU_BOOT_DEV_STS0_GIC_PRIVILEGED_EN … #define CPU_BOOT_DEV_STS0_EQ_INDEX_EN … #define CPU_BOOT_DEV_STS0_MULTI_IRQ_POLL_EN … #define CPU_BOOT_DEV_STS0_FW_NIC_STAT_XPCS91_EN … #define CPU_BOOT_DEV_STS0_FW_NIC_STAT_EXT_EN … #define CPU_BOOT_DEV_STS0_IS_IDLE_CHECK_EN … #define CPU_BOOT_DEV_STS0_MAP_HWMON_EN … #define CPU_BOOT_DEV_STS0_NIC_MEM_CLEAR_EN … #define CPU_BOOT_DEV_STS0_MMU_PGTBL_DRAM_EN … #define CPU_BOOT_DEV_STS0_ENABLED … #define CPU_BOOT_DEV_STS1_ENABLED … enum cpu_boot_status { … }; enum kmd_msg { … }; enum cpu_msg_status { … }; /* communication registers mapping - consider ABI when changing */ struct cpu_dyn_regs { … }; /* TODO: remove the desc magic after the code is updated to use message */ /* HCDM - Habana Communications Descriptor Magic */ #define HL_COMMS_DESC_MAGIC … #define HL_COMMS_DESC_VER … /* HCMv - Habana Communications Message + header version */ #define HL_COMMS_MSG_MAGIC_VALUE … #define HL_COMMS_MSG_MAGIC_MASK … #define HL_COMMS_MSG_MAGIC_VER_MASK … #define HL_COMMS_MSG_MAGIC_VER(ver) … #define HL_COMMS_MSG_MAGIC_V0 … #define HL_COMMS_MSG_MAGIC_V1 … #define HL_COMMS_MSG_MAGIC_V2 … #define HL_COMMS_MSG_MAGIC_V3 … #define HL_COMMS_MSG_MAGIC … #define HL_COMMS_MSG_MAGIC_VALIDATE_MAGIC(magic) … #define HL_COMMS_MSG_MAGIC_VALIDATE_VERSION(magic, ver) … #define HL_COMMS_MSG_MAGIC_VALIDATE(magic, ver) … enum comms_msg_type { … }; /* * Binning information shared between LKD and FW * @tpc_mask_l - TPC binning information lower 64 bit * @dec_mask - Decoder binning information * @dram_mask - DRAM binning information * @edma_mask - EDMA binning information * @mme_mask_l - MME binning information lower 32 * @mme_mask_h - MME binning information upper 32 * @rot_mask - Rotator binning information * @xbar_mask - xBAR binning information * @reserved - reserved field for future binning info w/o ABI change * @tpc_mask_h - TPC binning information upper 64 bit * @nic_mask - NIC binning information */ struct lkd_fw_binning_info { … }; /* TODO: remove this struct after the code is updated to use message */ /* this is the comms descriptor header - meta data */ struct comms_desc_header { … }; /* this is the comms message header - meta data */ struct comms_msg_header { … }; enum lkd_fw_ascii_msg_lvls { … }; #define LKD_FW_ASCII_MSG_MAX_LEN … #define LKD_FW_ASCII_MSG_MAX … #define LKD_FW_ASCII_MSG_MIN_DESC_VERSION … struct lkd_fw_ascii_msg { … }; /* this is the main FW descriptor - consider ABI when changing */ struct lkd_fw_comms_desc { … }; enum comms_reset_cause { … }; /* TODO: remove define after struct name is aligned on all projects */ #define lkd_msg_comms … /* this is the comms message descriptor */ struct lkd_fw_comms_msg { … }; /* * LKD commands: * * COMMS_NOOP Used to clear the command register and no actual * command is send. * * COMMS_CLR_STS Clear status command - FW should clear the * status register. Used for synchronization * between the commands as part of the race free * protocol. * * COMMS_RST_STATE Reset the current communication state which is * kept by FW for proper responses. * Should be used in the beginning of the * communication cycle to clean any leftovers from * previous communication attempts. * * COMMS_PREP_DESC Prepare descriptor for setting up the * communication and other dynamic data: * struct lkd_fw_comms_desc. * This command has a parameter stating the next FW * component size, so the FW can actually prepare a * space for it and in the status response provide * the descriptor offset. The Offset of the next FW * data component is a part of the descriptor * structure. * * COMMS_DATA_RDY The FW data has been uploaded and is ready for * validation. * * COMMS_EXEC Execute the next FW component. * * COMMS_RST_DEV Reset the device. * * COMMS_GOTO_WFE Execute WFE command. Allowed only on non-secure * devices. * * COMMS_SKIP_BMC Perform actions required for BMC-less servers. * Do not wait for BMC response. * * COMMS_PREP_DESC_ELBI Same as COMMS_PREP_DESC only that the memory * space is allocated in a ELBI access only * address range. * */ enum comms_cmd { … }; #define COMMS_COMMAND_SIZE_SHIFT … #define COMMS_COMMAND_SIZE_MASK … #define COMMS_COMMAND_CMD_SHIFT … #define COMMS_COMMAND_CMD_MASK … /* * LKD command to FW register structure * @size - FW component size * @cmd - command from enum comms_cmd */ struct comms_command { … }; /* * FW status * * COMMS_STS_NOOP Used to clear the status register and no actual * status is provided. * * COMMS_STS_ACK Command has been received and recognized. * * COMMS_STS_OK Command execution has finished successfully. * * COMMS_STS_ERR Command execution was unsuccessful and resulted * in error. * * COMMS_STS_VALID_ERR FW validation has failed. * * COMMS_STS_TIMEOUT_ERR Command execution has timed out. */ enum comms_sts { … }; /* RAM types for FW components loading - defines the base address */ enum comms_ram_types { … }; #define COMMS_STATUS_OFFSET_SHIFT … #define COMMS_STATUS_OFFSET_MASK … #define COMMS_STATUS_OFFSET_ALIGN_SHIFT … #define COMMS_STATUS_RAM_TYPE_SHIFT … #define COMMS_STATUS_RAM_TYPE_MASK … #define COMMS_STATUS_STATUS_SHIFT … #define COMMS_STATUS_STATUS_MASK … /* * FW status to LKD register structure * @offset - an offset from the base of the ram_type shifted right by * 2 bits (always aligned to 32 bits). * Allows a maximum addressable offset of 256MB from RAM base. * Example: for real offset in RAM of 0x800000 (8MB), the value * in offset field is (0x800000 >> 2) = 0x200000. * @ram_type - the RAM type that should be used for offset from * enum comms_ram_types * @status - status from enum comms_sts */ struct comms_status { … }; #define NAME_MAX_LEN … struct hl_module_data { … }; /** * struct hl_component_versions - versions associated with hl component. * @struct_size: size of all the struct (including dynamic size of modules). * @modules_offset: offset of the modules field in this struct. * @component: version of the component itself. * @fw_os: Firmware OS Version. * @comp_name: Name of the component. * @modules_counter: number of set bits in modules_mask. * @reserved: reserved for future use. * @modules: versions of the component's modules. Elborated explanation in * struct cpucp_versions. */ struct hl_component_versions { … }; /* Max size of fit size */ #define HL_FW_VERSIONS_FIT_SIZE … #endif /* HL_BOOT_IF_H */
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