/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2020-2022 HabanaLabs, Ltd. * All Rights Reserved. * */ #ifndef GAUDI2_H #define GAUDI2_H #define SRAM_CFG_BAR_ID … #define MSIX_BAR_ID … #define DRAM_BAR_ID … /* Refers to CFG_REGION_SIZE, BAR0_RSRVD_SIZE and SRAM_SIZE */ #define CFG_BAR_SIZE … #define MSIX_BAR_SIZE … #define CFG_BASE … #define CFG_SIZE … #define CFG_REGION_SIZE … #define STM_FLASH_BASE_ADDR … #define STM_FLASH_ALIGNED_OFF … #define STM_FLASH_SIZE … #define SPI_FLASH_BASE_ADDR … #define SPI_FLASH_SIZE … #define SCRATCHPAD_SRAM_ADDR … #define SCRATCHPAD_SRAM_SIZE … #define PCIE_FW_SRAM_ADDR … #define PCIE_FW_SRAM_SIZE … #define BAR0_RSRVD_BASE_ADDR … #define BAR0_RSRVD_SIZE … #define SRAM_BASE_ADDR … #define SRAM_SIZE … #define DRAM_PHYS_BASE … /* every hint address is masked accordingly */ #define DRAM_VA_HINT_MASK … #define HOST_PHYS_BASE_0 … #define HOST_PHYS_SIZE_0 … #define HOST_PHYS_BASE_1 … #define HOST_PHYS_SIZE_1 … #define RESERVED_VA_RANGE_FOR_ARC_ON_HBM_START … #define RESERVED_VA_RANGE_FOR_ARC_ON_HBM_END … #define RESERVED_VA_FOR_VIRTUAL_MSIX_DOORBELL_START … #define RESERVED_VA_FOR_VIRTUAL_MSIX_DOORBELL_END … #define RESERVED_VA_RANGE_FOR_ARC_ON_HOST_START … #define RESERVED_VA_RANGE_FOR_ARC_ON_HOST_END … #define RESERVED_VA_RANGE_FOR_ARC_ON_HOST_HPAGE_START … #define RESERVED_VA_RANGE_FOR_ARC_ON_HOST_HPAGE_END … #define RESERVED_MSIX_UNEXPECTED_USER_ERROR_INTERRUPT … #define GAUDI2_MSIX_ENTRIES … #define QMAN_PQ_ENTRY_SIZE … #define MAX_ASID … #define NUM_ARC_CPUS … /* Every ARC cpu in the system contains a single DCCM block * except MME and Scheduler ARCs which contain 2 DCCM blocks */ #define ARC_DCCM_BLOCK_SIZE … #define NUM_OF_DCORES … #define NUM_OF_SFT … #define NUM_OF_PSOC_ARC … #define NUM_OF_SCHEDULER_ARC … #define NUM_OF_PQ_PER_QMAN … #define NUM_OF_CQ_PER_QMAN … #define NUM_OF_CP_PER_QMAN … #define NUM_OF_EDMA_PER_DCORE … #define NUM_OF_HIF_PER_DCORE … #define NUM_OF_PDMA … #define NUM_OF_TPC_PER_DCORE … #define NUM_DCORE0_TPC … #define NUM_DCORE1_TPC … #define NUM_DCORE2_TPC … #define NUM_DCORE3_TPC … #define NUM_OF_DEC_PER_DCORE … #define NUM_OF_ROT … #define NUM_OF_HMMU_PER_DCORE … #define NUM_OF_MME_PER_DCORE … #define NUM_OF_MME_SBTE_PER_DCORE … #define NUM_OF_MME_WB_PER_DCORE … #define NUM_OF_RTR_PER_DCORE … #define NUM_OF_VDEC_PER_DCORE … #define NUM_OF_IF_RTR_PER_SFT … #define NUM_OF_PCIE_VDEC … #define NUM_OF_ARC_FARMS_ARC … #define NUM_OF_XBAR … #define TPC_NUM_OF_KERNEL_TENSORS … #define TPC_NUM_OF_QM_TENSORS … #define MME_NUM_OF_LFSR_SEEDS … #define NIC_NUMBER_OF_MACROS … #define NIC_NUMBER_OF_QM_PER_MACRO … #define NIC_NUMBER_OF_ENGINES … #define NIC_MAX_NUMBER_OF_PORTS … #define DEVICE_CACHE_LINE_SIZE … #endif /* GAUDI2_H */
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