/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2020-2022 HabanaLabs, Ltd. * All Rights Reserved. * */ #ifndef GAUDI2P_H_ #define GAUDI2P_H_ #include <uapi/drm/habanalabs_accel.h> #include "../common/habanalabs.h" #include <linux/habanalabs/hl_boot_if.h> #include "../include/gaudi2/gaudi2.h" #include "../include/gaudi2/gaudi2_packets.h" #include "../include/gaudi2/gaudi2_fw_if.h" #include "../include/gaudi2/gaudi2_async_events.h" #define GAUDI2_LINUX_FW_FILE … #define GAUDI2_BOOT_FIT_FILE … #define GAUDI2_CPU_TIMEOUT_USEC … #define NUMBER_OF_PDMA_QUEUES … #define NUMBER_OF_EDMA_QUEUES … #define NUMBER_OF_MME_QUEUES … #define NUMBER_OF_TPC_QUEUES … #define NUMBER_OF_NIC_QUEUES … #define NUMBER_OF_ROT_QUEUES … #define NUMBER_OF_CPU_QUEUES … #define NUMBER_OF_HW_QUEUES … #define NUMBER_OF_QUEUES … #define DCORE_NUM_OF_SOB … #define DCORE_NUM_OF_MONITORS … #define NUMBER_OF_DEC … /* Map all arcs dccm + arc schedulers acp blocks */ #define NUM_OF_USER_ACP_BLOCKS … #define NUM_OF_USER_NIC_UMR_BLOCKS … #define NUM_OF_EXPOSED_SM_BLOCKS … #define NUM_USER_MAPPED_BLOCKS … /* Within the user mapped array, decoder entries start post all the ARC related * entries */ #define USR_MAPPED_BLK_DEC_START_IDX … #define USR_MAPPED_BLK_SM_START_IDX … #define SM_OBJS_BLOCK_SIZE … #define GAUDI2_MAX_PENDING_CS … #if !IS_MAX_PENDING_CS_VALID(GAUDI2_MAX_PENDING_CS) #error "GAUDI2_MAX_PENDING_CS must be power of 2 and greater than 1" #endif #define CORESIGHT_TIMEOUT_USEC … #define GAUDI2_PREBOOT_REQ_TIMEOUT_USEC … #define GAUDI2_PREBOOT_EXTENDED_REQ_TIMEOUT_USEC … #define GAUDI2_BOOT_FIT_REQ_TIMEOUT_USEC … #define GAUDI2_NIC_CLK_FREQ … #define DC_POWER_DEFAULT … #define GAUDI2_HBM_NUM … #define DMA_MAX_TRANSFER_SIZE … #define GAUDI2_DEFAULT_CARD_NAME … #define QMAN_STREAMS … #define NUM_OF_MME_SBTE_PORTS … #define NUM_OF_MME_WB_PORTS … #define GAUDI2_ENGINE_ID_DCORE_OFFSET … /* DRAM Memory Map */ #define CPU_FW_IMAGE_SIZE … #define CPU_FW_IMAGE_ADDR … #define PMMU_PAGE_TABLES_SIZE … #define EDMA_PQS_SIZE … #define EDMA_SCRATCHPAD_SIZE … #define HMMU_PAGE_TABLES_SIZE … #define NIC_NUMBER_OF_PORTS … #define NUMBER_OF_PCIE_DEC … #define PCIE_DEC_SHIFT … #define SRAM_USER_BASE_OFFSET … /* cluster binning */ #define MAX_FAULTY_HBMS … #define GAUDI2_XBAR_EDGE_FULL_MASK … #define GAUDI2_EDMA_FULL_MASK … #define GAUDI2_DRAM_FULL_MASK … /* Host virtual address space. */ #define VA_HOST_SPACE_PAGE_START … #define VA_HOST_SPACE_PAGE_END … #define VA_HOST_SPACE_HPAGE_START … #define VA_HOST_SPACE_HPAGE_END … /* 140TB */ #define VA_HOST_SPACE_PAGE_SIZE … /* 140TB */ #define VA_HOST_SPACE_HPAGE_SIZE … #define VA_HOST_SPACE_SIZE … #define HOST_SPACE_INTERNAL_CB_SZ … /* * HBM virtual address space * Gaudi2 has 6 HBM devices, each supporting 16GB total of 96GB at most. * No core separation is supported so we can have one chunk of virtual address * space just above the physical ones. * The virtual address space starts immediately after the end of the physical * address space which is determined at run-time. */ #define VA_HBM_SPACE_END … #define HW_CAP_PLL … #define HW_CAP_DRAM … #define HW_CAP_PMMU … #define HW_CAP_CPU … #define HW_CAP_MSIX … #define HW_CAP_CPU_Q … #define HW_CAP_CPU_Q_SHIFT … #define HW_CAP_CLK_GATE … #define HW_CAP_KDMA … #define HW_CAP_SRAM_SCRAMBLER … #define HW_CAP_DCORE0_DMMU0 … #define HW_CAP_DCORE0_DMMU1 … #define HW_CAP_DCORE0_DMMU2 … #define HW_CAP_DCORE0_DMMU3 … #define HW_CAP_DCORE1_DMMU0 … #define HW_CAP_DCORE1_DMMU1 … #define HW_CAP_DCORE1_DMMU2 … #define HW_CAP_DCORE1_DMMU3 … #define HW_CAP_DCORE2_DMMU0 … #define HW_CAP_DCORE2_DMMU1 … #define HW_CAP_DCORE2_DMMU2 … #define HW_CAP_DCORE2_DMMU3 … #define HW_CAP_DCORE3_DMMU0 … #define HW_CAP_DCORE3_DMMU1 … #define HW_CAP_DCORE3_DMMU2 … #define HW_CAP_DCORE3_DMMU3 … #define HW_CAP_DMMU_MASK … #define HW_CAP_DMMU_SHIFT … #define HW_CAP_PDMA_MASK … #define HW_CAP_EDMA_MASK … #define HW_CAP_EDMA_SHIFT … #define HW_CAP_MME_MASK … #define HW_CAP_MME_SHIFT … #define HW_CAP_ROT_MASK … #define HW_CAP_ROT_SHIFT … #define HW_CAP_HBM_SCRAMBLER_HW_RESET … #define HW_CAP_HBM_SCRAMBLER_SW_RESET … #define HW_CAP_HBM_SCRAMBLER_MASK … #define HW_CAP_HBM_SCRAMBLER_SHIFT … #define HW_CAP_RESERVED … #define HW_CAP_MMU_MASK … /* Range Registers */ #define RR_TYPE_SHORT … #define RR_TYPE_LONG … #define RR_TYPE_SHORT_PRIV … #define RR_TYPE_LONG_PRIV … #define NUM_SHORT_LBW_RR … #define NUM_LONG_LBW_RR … #define NUM_SHORT_HBW_RR … #define NUM_LONG_HBW_RR … /* RAZWI initiator coordinates- X- 5 bits, Y- 4 bits */ #define RAZWI_INITIATOR_X_SHIFT … #define RAZWI_INITIATOR_X_MASK … #define RAZWI_INITIATOR_Y_SHIFT … #define RAZWI_INITIATOR_Y_MASK … #define RTR_ID_X_Y(x, y) … /* decoders have separate mask */ #define HW_CAP_DEC_SHIFT … #define HW_CAP_DEC_MASK … /* TPCs have separate mask */ #define HW_CAP_TPC_SHIFT … #define HW_CAP_TPC_MASK … /* nics have separate mask */ #define HW_CAP_NIC_SHIFT … #define HW_CAP_NIC_MASK … #define GAUDI2_ARC_PCI_MSB_ADDR(addr) … #define GAUDI2_SOB_INCREMENT_BY_ONE … #define GAUDI2_NUM_TESTED_QS … enum gaudi2_reserved_sob_id { … }; enum gaudi2_reserved_mon_id { … }; enum gaudi2_reserved_cq_id { … }; /* * Gaudi2 subtitute TPCs Numbering * At most- two faulty TPCs are allowed * First replacement to a faulty TPC will be TPC24, second- TPC23 */ enum substitude_tpc { … }; enum gaudi2_dma_core_id { … }; enum gaudi2_rotator_id { … }; enum gaudi2_mme_id { … }; enum gaudi2_tpc_id { … }; enum gaudi2_dec_id { … }; enum gaudi2_hbm_id { … }; /* specific EDMA enumeration */ enum gaudi2_edma_id { … }; /* User interrupt count is aligned with HW CQ count. * We have 64 CQ's per dcore, CQ0 in dcore 0 is reserved for legacy mode */ #define GAUDI2_NUM_USER_INTERRUPTS … #define GAUDI2_NUM_RESERVED_INTERRUPTS … #define GAUDI2_TOTAL_USER_INTERRUPTS … enum gaudi2_irq_num { … }; static_assert(…); /** * struct dup_block_ctx - context to initialize unit instances across multiple * blocks where block can be either a dcore of duplicated * common module. this code relies on constant offsets * of blocks and unit instances in a block. * @instance_cfg_fn: instance specific configuration function. * @data: private configuration data. * @base: base address of the first instance in the first block. * @block_off: subsequent blocks address spacing. * @instance_off: subsequent block's instances address spacing. * @enabled_mask: mask of enabled instances (1- enabled, 0- disabled). * @blocks: number of blocks. * @instances: unit instances per block. */ struct dup_block_ctx { … }; /** * struct gaudi2_queues_test_info - Holds the address of a the messages used for testing the * device queues. * @dma_addr: the address used by the HW for accessing the message. * @kern_addr: The address used by the driver for accessing the message. */ struct gaudi2_queues_test_info { … }; /** * struct gaudi2_device - ASIC specific manage structure. * @cpucp_info_get: get information on device from CPU-CP * @mapped_blocks: array that holds the base address and size of all blocks * the user can map. * @lfsr_rand_seeds: array of MME ACC random seeds to set. * @hw_queues_lock: protects the H/W queues from concurrent access. * @scratchpad_kernel_address: general purpose PAGE_SIZE contiguous memory, * this memory region should be write-only. * currently used for HBW QMAN writes which is * redundant. * @scratchpad_bus_address: scratchpad bus address * @virt_msix_db_cpu_addr: host memory page for the virtual MSI-X doorbell. * @virt_msix_db_dma_addr: bus address of the page for the virtual MSI-X doorbell. * @dram_bar_cur_addr: current address of DRAM PCI bar. * @hw_cap_initialized: This field contains a bit per H/W engine. When that * engine is initialized, that bit is set by the driver to * signal we can use this engine in later code paths. * Each bit is cleared upon reset of its corresponding H/W * engine. * @active_hw_arc: This field contains a bit per ARC of an H/W engine with * exception of TPC and NIC engines. Once an engine arc is * initialized, its respective bit is set. Driver can uniquely * identify each initialized ARC and use this information in * later code paths. Each respective bit is cleared upon reset * of its corresponding ARC of the H/W engine. * @dec_hw_cap_initialized: This field contains a bit per decoder H/W engine. * When that engine is initialized, that bit is set by * the driver to signal we can use this engine in later * code paths. * Each bit is cleared upon reset of its corresponding H/W * engine. * @tpc_hw_cap_initialized: This field contains a bit per TPC H/W engine. * When that engine is initialized, that bit is set by * the driver to signal we can use this engine in later * code paths. * Each bit is cleared upon reset of its corresponding H/W * engine. * @active_tpc_arc: This field contains a bit per ARC of the TPC engines. * Once an engine arc is initialized, its respective bit is * set. Each respective bit is cleared upon reset of its * corresponding ARC of the TPC engine. * @nic_hw_cap_initialized: This field contains a bit per nic H/W engine. * @active_nic_arc: This field contains a bit per ARC of the NIC engines. * Once an engine arc is initialized, its respective bit is * set. Each respective bit is cleared upon reset of its * corresponding ARC of the NIC engine. * @hw_events: array that holds all H/W events that are defined valid. * @events_stat: array that holds histogram of all received events. * @events_stat_aggregate: same as events_stat but doesn't get cleared on reset. * @num_of_valid_hw_events: used to hold the number of valid H/W events. * @nic_ports: array that holds all NIC ports manage structures. * @nic_macros: array that holds all NIC macro manage structures. * @core_info: core info to be used by the Ethernet driver. * @aux_ops: functions for core <-> aux drivers communication. * @flush_db_fifo: flag to force flush DB FIFO after a write. * @hbm_cfg: HBM subsystem settings * @hw_queues_lock_mutex: used by simulator instead of hw_queues_lock. * @queues_test_info: information used by the driver when testing the HW queues. */ struct gaudi2_device { … }; /* * Types of the Gaudi2 IP blocks, used by special blocks iterator. * Required for scenarios where only particular block types can be * addressed (e.g., special PLDM images). */ enum gaudi2_block_types { … }; extern const u32 gaudi2_dma_core_blocks_bases[DMA_CORE_ID_SIZE]; extern const u32 gaudi2_qm_blocks_bases[GAUDI2_QUEUE_ID_SIZE]; extern const u32 gaudi2_mme_acc_blocks_bases[MME_ID_SIZE]; extern const u32 gaudi2_mme_ctrl_lo_blocks_bases[MME_ID_SIZE]; extern const u32 edma_stream_base[NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES]; extern const u32 gaudi2_rot_blocks_bases[ROTATOR_ID_SIZE]; void gaudi2_iterate_tpcs(struct hl_device *hdev, struct iterate_module_ctx *ctx); int gaudi2_coresight_init(struct hl_device *hdev); int gaudi2_debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, void *data); void gaudi2_halt_coresight(struct hl_device *hdev, struct hl_ctx *ctx); void gaudi2_init_blocks(struct hl_device *hdev, struct dup_block_ctx *cfg_ctx); bool gaudi2_is_hmmu_enabled(struct hl_device *hdev, int dcore_id, int hmmu_id); void gaudi2_write_rr_to_all_lbw_rtrs(struct hl_device *hdev, u8 rr_type, u32 rr_index, u64 min_val, u64 max_val); void gaudi2_pb_print_security_errors(struct hl_device *hdev, u32 block_addr, u32 cause, u32 offended_addr); int gaudi2_init_security(struct hl_device *hdev); void gaudi2_ack_protection_bits_errors(struct hl_device *hdev); int gaudi2_send_device_activity(struct hl_device *hdev, bool open); #endif /* GAUDI2P_H_ */
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