/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2019-2022 HabanaLabs, Ltd. * All Rights Reserved. * */ #ifndef GAUDIP_H_ #define GAUDIP_H_ #include <uapi/drm/habanalabs_accel.h> #include "../common/habanalabs.h" #include <linux/habanalabs/hl_boot_if.h> #include "../include/gaudi/gaudi_packets.h" #include "../include/gaudi/gaudi.h" #include "../include/gaudi/gaudi_async_events.h" #include "../include/gaudi/gaudi_fw_if.h" #define NUMBER_OF_EXT_HW_QUEUES … #define NUMBER_OF_CMPLT_QUEUES … #define NUMBER_OF_CPU_HW_QUEUES … #define NUMBER_OF_INT_HW_QUEUES … #define NUMBER_OF_HW_QUEUES … /* 10 NIC QMANs, DMA5 QMAN, TPC7 QMAN */ #define NUMBER_OF_COLLECTIVE_QUEUES … #define NUMBER_OF_SOBS_IN_GRP … #define GAUDI_STREAM_MASTER_ARR_SIZE … #define CORESIGHT_TIMEOUT_USEC … #define GAUDI_MAX_CLK_FREQ … #define MAX_POWER_DEFAULT_PCI … #define MAX_POWER_DEFAULT_PMC … #define DC_POWER_DEFAULT_PCI … #define DC_POWER_DEFAULT_PMC … #define DC_POWER_DEFAULT_PMC_SEC … #define GAUDI_CPU_TIMEOUT_USEC … #define TPC_ENABLED_MASK … #define GAUDI_HBM_SIZE_32GB … #define GAUDI_HBM_DEVICES … #define GAUDI_HBM_CHANNELS … #define GAUDI_HBM_CFG_BASE … #define GAUDI_HBM_CFG_OFFSET … #define DMA_MAX_TRANSFER_SIZE … #define GAUDI_DEFAULT_CARD_NAME … #define GAUDI_MAX_PENDING_CS … #if !IS_MAX_PENDING_CS_VALID(GAUDI_MAX_PENDING_CS) #error "GAUDI_MAX_PENDING_CS must be power of 2 and greater than 1" #endif #define PCI_DMA_NUMBER_OF_CHNLS … #define HBM_DMA_NUMBER_OF_CHNLS … #define DMA_NUMBER_OF_CHNLS … #define MME_NUMBER_OF_SLAVE_ENGINES … #define MME_NUMBER_OF_ENGINES … #define MME_NUMBER_OF_QMANS … #define QMAN_STREAMS … #define PQ_FETCHER_CACHE_SIZE … #define DMA_QMAN_OFFSET … #define TPC_QMAN_OFFSET … #define MME_QMAN_OFFSET … #define NIC_MACRO_QMAN_OFFSET … #define NIC_ENGINE_QMAN_OFFSET … #define TPC_CFG_OFFSET … #define DMA_CORE_OFFSET … #define QMAN_LDMA_SRC_OFFSET … #define QMAN_LDMA_DST_OFFSET … #define QMAN_LDMA_SIZE_OFFSET … #define QMAN_CPDMA_SRC_OFFSET … #define QMAN_CPDMA_DST_OFFSET … #define QMAN_CPDMA_SIZE_OFFSET … #define SIF_RTR_CTRL_OFFSET … #define NIF_RTR_CTRL_OFFSET … #define MME_ACC_OFFSET … #define SRAM_BANK_OFFSET … #define NUM_OF_SOB_IN_BLOCK … #define NUM_OF_MONITORS_IN_BLOCK … #define MONITOR_MAX_SOBS … /* DRAM Memory Map */ #define CPU_FW_IMAGE_SIZE … #define MMU_PAGE_TABLES_SIZE … #define MMU_CACHE_MNG_SIZE … #define RESERVED … #define CPU_FW_IMAGE_ADDR … #define MMU_PAGE_TABLES_ADDR … #define MMU_CACHE_MNG_ADDR … #define DRAM_DRIVER_END_ADDR … #define DRAM_BASE_ADDR_USER … #if (DRAM_DRIVER_END_ADDR > DRAM_BASE_ADDR_USER) #error "Driver must reserve no more than 512MB" #endif /* Internal QMANs PQ sizes */ #define MME_QMAN_LENGTH … #define MME_QMAN_SIZE_IN_BYTES … #define HBM_DMA_QMAN_LENGTH … #define HBM_DMA_QMAN_SIZE_IN_BYTES … #define TPC_QMAN_LENGTH … #define TPC_QMAN_SIZE_IN_BYTES … #define NIC_QMAN_LENGTH … #define NIC_QMAN_SIZE_IN_BYTES … #define SRAM_USER_BASE_OFFSET … /* Virtual address space */ #define VA_HOST_SPACE_START … #define VA_HOST_SPACE_END … #define VA_HOST_SPACE_SIZE … #define HOST_SPACE_INTERNAL_CB_SZ … #define HW_CAP_PLL … #define HW_CAP_HBM … #define HW_CAP_MMU … #define HW_CAP_MME … #define HW_CAP_CPU … #define HW_CAP_PCI_DMA … #define HW_CAP_MSI … #define HW_CAP_CPU_Q … #define HW_CAP_HBM_DMA … #define HW_CAP_SRAM_SCRAMBLER … #define HW_CAP_HBM_SCRAMBLER … #define HW_CAP_NIC0 … #define HW_CAP_NIC1 … #define HW_CAP_NIC2 … #define HW_CAP_NIC3 … #define HW_CAP_NIC4 … #define HW_CAP_NIC5 … #define HW_CAP_NIC6 … #define HW_CAP_NIC7 … #define HW_CAP_NIC8 … #define HW_CAP_NIC9 … #define HW_CAP_NIC_MASK … #define HW_CAP_NIC_SHIFT … #define HW_CAP_TPC0 … #define HW_CAP_TPC1 … #define HW_CAP_TPC2 … #define HW_CAP_TPC3 … #define HW_CAP_TPC4 … #define HW_CAP_TPC5 … #define HW_CAP_TPC6 … #define HW_CAP_TPC7 … #define HW_CAP_TPC_MASK … #define HW_CAP_TPC_SHIFT … #define NEXT_SYNC_OBJ_ADDR_INTERVAL … #define NUM_OF_MME_ENGINES … #define NUM_OF_MME_SUB_ENGINES … #define NUM_OF_TPC_ENGINES … #define NUM_OF_DMA_ENGINES … #define NUM_OF_QUEUES … #define NUM_OF_STREAMS … #define NUM_OF_FENCES … #define GAUDI_CPU_PCI_MSB_ADDR(addr) … #define GAUDI_PCI_TO_CPU_ADDR(addr) … #define GAUDI_CPU_TO_PCI_ADDR(addr, extension) … enum gaudi_dma_channels { … }; enum gaudi_tpc_mask { … }; enum gaudi_nic_mask { … }; /* * struct gaudi_hw_sob_group - H/W SOB group info. * @hdev: habanalabs device structure. * @kref: refcount of this SOB group. group will reset once refcount is zero. * @base_sob_id: base sob id of this SOB group. * @queue_id: id of the queue that waits on this sob group */ struct gaudi_hw_sob_group { … }; #define NUM_SOB_GROUPS … /** * struct gaudi_collective_properties - * holds all SOB groups and queues info reserved for the collective * @hw_sob_group: H/W SOB groups. * @next_sob_group_val: the next value to use for the currently used SOB group. * @curr_sob_group_idx: the index of the currently used SOB group. * @mstr_sob_mask: pre-defined masks for collective master monitors */ struct gaudi_collective_properties { … }; /** * struct gaudi_internal_qman_info - Internal QMAN information. * @pq_kernel_addr: Kernel address of the PQ memory area in the host. * @pq_dma_addr: DMA address of the PQ memory area in the host. * @pq_size: Size of allocated host memory for PQ. */ struct gaudi_internal_qman_info { … }; /** * struct gaudi_device - ASIC specific manage structure. * @cpucp_info_get: get information on device from CPU-CP * @hw_queues_lock: protects the H/W queues from concurrent access. * @internal_qmans: Internal QMANs information. The array size is larger than * the actual number of internal queues because they are not in * consecutive order. * @hbm_bar_cur_addr: current address of HBM PCI bar. * @events: array that holds all event id's * @events_stat: array that holds histogram of all received events. * @events_stat_aggregate: same as events_stat but doesn't get cleared on reset * @hw_cap_initialized: This field contains a bit per H/W engine. When that * engine is initialized, that bit is set by the driver to * signal we can use this engine in later code paths. * Each bit is cleared upon reset of its corresponding H/W * engine. * @mmu_cache_inv_pi: PI for MMU cache invalidation flow. The H/W expects an * 8-bit value so use u8. */ struct gaudi_device { … }; void gaudi_init_security(struct hl_device *hdev); void gaudi_ack_protection_bits_errors(struct hl_device *hdev); int gaudi_debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, void *data); void gaudi_halt_coresight(struct hl_device *hdev, struct hl_ctx *ctx); void gaudi_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid); #endif /* GAUDIP_H_ */
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