linux/drivers/accel/habanalabs/include/goya/asic_reg/goya_blocks.h

/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2018 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef GOYA_BLOCKS_H_
#define GOYA_BLOCKS_H_

#define mmPCI_NRTR_BASE
#define PCI_NRTR_MAX_OFFSET
#define PCI_NRTR_SECTION
#define mmPCI_RD_REGULATOR_BASE
#define PCI_RD_REGULATOR_MAX_OFFSET
#define PCI_RD_REGULATOR_SECTION
#define mmPCI_WR_REGULATOR_BASE
#define PCI_WR_REGULATOR_MAX_OFFSET
#define PCI_WR_REGULATOR_SECTION
#define mmMME1_RTR_BASE
#define MME1_RTR_MAX_OFFSET
#define MME1_RTR_SECTION
#define mmMME1_RD_REGULATOR_BASE
#define MME1_RD_REGULATOR_MAX_OFFSET
#define MME1_RD_REGULATOR_SECTION
#define mmMME1_WR_REGULATOR_BASE
#define MME1_WR_REGULATOR_MAX_OFFSET
#define MME1_WR_REGULATOR_SECTION
#define mmMME2_RTR_BASE
#define MME2_RTR_MAX_OFFSET
#define MME2_RTR_SECTION
#define mmMME2_RD_REGULATOR_BASE
#define MME2_RD_REGULATOR_MAX_OFFSET
#define MME2_RD_REGULATOR_SECTION
#define mmMME2_WR_REGULATOR_BASE
#define MME2_WR_REGULATOR_MAX_OFFSET
#define MME2_WR_REGULATOR_SECTION
#define mmMME3_RTR_BASE
#define MME3_RTR_MAX_OFFSET
#define MME3_RTR_SECTION
#define mmMME3_RD_REGULATOR_BASE
#define MME3_RD_REGULATOR_MAX_OFFSET
#define MME3_RD_REGULATOR_SECTION
#define mmMME3_WR_REGULATOR_BASE
#define MME3_WR_REGULATOR_MAX_OFFSET
#define MME3_WR_REGULATOR_SECTION
#define mmMME_BASE
#define MME_MAX_OFFSET
#define MME_SECTION
#define mmMME_QM_BASE
#define MME_QM_MAX_OFFSET
#define MME_QM_SECTION
#define mmMME_CMDQ_BASE
#define MME_CMDQ_MAX_OFFSET
#define MME_CMDQ_SECTION
#define mmACC_MS_ECC_MEM_0_BASE
#define ACC_MS_ECC_MEM_0_MAX_OFFSET
#define ACC_MS_ECC_MEM_0_SECTION
#define mmACC_MS_ECC_MEM_1_BASE
#define ACC_MS_ECC_MEM_1_MAX_OFFSET
#define ACC_MS_ECC_MEM_1_SECTION
#define mmACC_MS_ECC_MEM_2_BASE
#define ACC_MS_ECC_MEM_2_MAX_OFFSET
#define ACC_MS_ECC_MEM_2_SECTION
#define mmACC_MS_ECC_MEM_3_BASE
#define ACC_MS_ECC_MEM_3_MAX_OFFSET
#define ACC_MS_ECC_MEM_3_SECTION
#define mmSBA_ECC_MEM_BASE
#define SBA_ECC_MEM_MAX_OFFSET
#define SBA_ECC_MEM_SECTION
#define mmSBB_ECC_MEM_BASE
#define SBB_ECC_MEM_MAX_OFFSET
#define SBB_ECC_MEM_SECTION
#define mmMME4_RTR_BASE
#define MME4_RTR_MAX_OFFSET
#define MME4_RTR_SECTION
#define mmMME4_RD_REGULATOR_BASE
#define MME4_RD_REGULATOR_MAX_OFFSET
#define MME4_RD_REGULATOR_SECTION
#define mmMME4_WR_REGULATOR_BASE
#define MME4_WR_REGULATOR_MAX_OFFSET
#define MME4_WR_REGULATOR_SECTION
#define mmSYNC_MNGR_BASE
#define SYNC_MNGR_MAX_OFFSET
#define SYNC_MNGR_SECTION
#define mmMME5_RTR_BASE
#define MME5_RTR_MAX_OFFSET
#define MME5_RTR_SECTION
#define mmMME5_RD_REGULATOR_BASE
#define MME5_RD_REGULATOR_MAX_OFFSET
#define MME5_RD_REGULATOR_SECTION
#define mmMME5_WR_REGULATOR_BASE
#define MME5_WR_REGULATOR_MAX_OFFSET
#define MME5_WR_REGULATOR_SECTION
#define mmMME6_RTR_BASE
#define MME6_RTR_MAX_OFFSET
#define MME6_RTR_SECTION
#define mmMME6_RD_REGULATOR_BASE
#define MME6_RD_REGULATOR_MAX_OFFSET
#define MME6_RD_REGULATOR_SECTION
#define mmMME6_WR_REGULATOR_BASE
#define MME6_WR_REGULATOR_MAX_OFFSET
#define MME6_WR_REGULATOR_SECTION
#define mmDMA_NRTR_BASE
#define DMA_NRTR_MAX_OFFSET
#define DMA_NRTR_SECTION
#define mmDMA_RD_REGULATOR_BASE
#define DMA_RD_REGULATOR_MAX_OFFSET
#define DMA_RD_REGULATOR_SECTION
#define mmDMA_WR_REGULATOR_BASE
#define DMA_WR_REGULATOR_MAX_OFFSET
#define DMA_WR_REGULATOR_SECTION
#define mmSRAM_Y0_X0_BANK_BASE
#define SRAM_Y0_X0_BANK_MAX_OFFSET
#define SRAM_Y0_X0_BANK_SECTION
#define mmSRAM_Y0_X0_RTR_BASE
#define SRAM_Y0_X0_RTR_MAX_OFFSET
#define SRAM_Y0_X0_RTR_SECTION
#define mmSRAM_Y0_X1_BANK_BASE
#define SRAM_Y0_X1_BANK_MAX_OFFSET
#define SRAM_Y0_X1_BANK_SECTION
#define mmSRAM_Y0_X1_RTR_BASE
#define SRAM_Y0_X1_RTR_MAX_OFFSET
#define SRAM_Y0_X1_RTR_SECTION
#define mmSRAM_Y0_X2_BANK_BASE
#define SRAM_Y0_X2_BANK_MAX_OFFSET
#define SRAM_Y0_X2_BANK_SECTION
#define mmSRAM_Y0_X2_RTR_BASE
#define SRAM_Y0_X2_RTR_MAX_OFFSET
#define SRAM_Y0_X2_RTR_SECTION
#define mmSRAM_Y0_X3_BANK_BASE
#define SRAM_Y0_X3_BANK_MAX_OFFSET
#define SRAM_Y0_X3_BANK_SECTION
#define mmSRAM_Y0_X3_RTR_BASE
#define SRAM_Y0_X3_RTR_MAX_OFFSET
#define SRAM_Y0_X3_RTR_SECTION
#define mmSRAM_Y0_X4_BANK_BASE
#define SRAM_Y0_X4_BANK_MAX_OFFSET
#define SRAM_Y0_X4_BANK_SECTION
#define mmSRAM_Y0_X4_RTR_BASE
#define SRAM_Y0_X4_RTR_MAX_OFFSET
#define SRAM_Y0_X4_RTR_SECTION
#define mmSRAM_Y1_X0_BANK_BASE
#define SRAM_Y1_X0_BANK_MAX_OFFSET
#define SRAM_Y1_X0_BANK_SECTION
#define mmSRAM_Y1_X0_RTR_BASE
#define SRAM_Y1_X0_RTR_MAX_OFFSET
#define SRAM_Y1_X0_RTR_SECTION
#define mmSRAM_Y1_X1_BANK_BASE
#define SRAM_Y1_X1_BANK_MAX_OFFSET
#define SRAM_Y1_X1_BANK_SECTION
#define mmSRAM_Y1_X1_RTR_BASE
#define SRAM_Y1_X1_RTR_MAX_OFFSET
#define SRAM_Y1_X1_RTR_SECTION
#define mmSRAM_Y1_X2_BANK_BASE
#define SRAM_Y1_X2_BANK_MAX_OFFSET
#define SRAM_Y1_X2_BANK_SECTION
#define mmSRAM_Y1_X2_RTR_BASE
#define SRAM_Y1_X2_RTR_MAX_OFFSET
#define SRAM_Y1_X2_RTR_SECTION
#define mmSRAM_Y1_X3_BANK_BASE
#define SRAM_Y1_X3_BANK_MAX_OFFSET
#define SRAM_Y1_X3_BANK_SECTION
#define mmSRAM_Y1_X3_RTR_BASE
#define SRAM_Y1_X3_RTR_MAX_OFFSET
#define SRAM_Y1_X3_RTR_SECTION
#define mmSRAM_Y1_X4_BANK_BASE
#define SRAM_Y1_X4_BANK_MAX_OFFSET
#define SRAM_Y1_X4_BANK_SECTION
#define mmSRAM_Y1_X4_RTR_BASE
#define SRAM_Y1_X4_RTR_MAX_OFFSET
#define SRAM_Y1_X4_RTR_SECTION
#define mmSRAM_Y2_X0_BANK_BASE
#define SRAM_Y2_X0_BANK_MAX_OFFSET
#define SRAM_Y2_X0_BANK_SECTION
#define mmSRAM_Y2_X0_RTR_BASE
#define SRAM_Y2_X0_RTR_MAX_OFFSET
#define SRAM_Y2_X0_RTR_SECTION
#define mmSRAM_Y2_X1_BANK_BASE
#define SRAM_Y2_X1_BANK_MAX_OFFSET
#define SRAM_Y2_X1_BANK_SECTION
#define mmSRAM_Y2_X1_RTR_BASE
#define SRAM_Y2_X1_RTR_MAX_OFFSET
#define SRAM_Y2_X1_RTR_SECTION
#define mmSRAM_Y2_X2_BANK_BASE
#define SRAM_Y2_X2_BANK_MAX_OFFSET
#define SRAM_Y2_X2_BANK_SECTION
#define mmSRAM_Y2_X2_RTR_BASE
#define SRAM_Y2_X2_RTR_MAX_OFFSET
#define SRAM_Y2_X2_RTR_SECTION
#define mmSRAM_Y2_X3_BANK_BASE
#define SRAM_Y2_X3_BANK_MAX_OFFSET
#define SRAM_Y2_X3_BANK_SECTION
#define mmSRAM_Y2_X3_RTR_BASE
#define SRAM_Y2_X3_RTR_MAX_OFFSET
#define SRAM_Y2_X3_RTR_SECTION
#define mmSRAM_Y2_X4_BANK_BASE
#define SRAM_Y2_X4_BANK_MAX_OFFSET
#define SRAM_Y2_X4_BANK_SECTION
#define mmSRAM_Y2_X4_RTR_BASE
#define SRAM_Y2_X4_RTR_MAX_OFFSET
#define SRAM_Y2_X4_RTR_SECTION
#define mmSRAM_Y3_X0_BANK_BASE
#define SRAM_Y3_X0_BANK_MAX_OFFSET
#define SRAM_Y3_X0_BANK_SECTION
#define mmSRAM_Y3_X0_RTR_BASE
#define SRAM_Y3_X0_RTR_MAX_OFFSET
#define SRAM_Y3_X0_RTR_SECTION
#define mmSRAM_Y3_X1_BANK_BASE
#define SRAM_Y3_X1_BANK_MAX_OFFSET
#define SRAM_Y3_X1_BANK_SECTION
#define mmSRAM_Y3_X1_RTR_BASE
#define SRAM_Y3_X1_RTR_MAX_OFFSET
#define SRAM_Y3_X1_RTR_SECTION
#define mmSRAM_Y3_X2_BANK_BASE
#define SRAM_Y3_X2_BANK_MAX_OFFSET
#define SRAM_Y3_X2_BANK_SECTION
#define mmSRAM_Y3_X2_RTR_BASE
#define SRAM_Y3_X2_RTR_MAX_OFFSET
#define SRAM_Y3_X2_RTR_SECTION
#define mmSRAM_Y3_X3_BANK_BASE
#define SRAM_Y3_X3_BANK_MAX_OFFSET
#define SRAM_Y3_X3_BANK_SECTION
#define mmSRAM_Y3_X3_RTR_BASE
#define SRAM_Y3_X3_RTR_MAX_OFFSET
#define SRAM_Y3_X3_RTR_SECTION
#define mmSRAM_Y3_X4_BANK_BASE
#define SRAM_Y3_X4_BANK_MAX_OFFSET
#define SRAM_Y3_X4_BANK_SECTION
#define mmSRAM_Y3_X4_RTR_BASE
#define SRAM_Y3_X4_RTR_MAX_OFFSET
#define SRAM_Y3_X4_RTR_SECTION
#define mmSRAM_Y4_X0_BANK_BASE
#define SRAM_Y4_X0_BANK_MAX_OFFSET
#define SRAM_Y4_X0_BANK_SECTION
#define mmSRAM_Y4_X0_RTR_BASE
#define SRAM_Y4_X0_RTR_MAX_OFFSET
#define SRAM_Y4_X0_RTR_SECTION
#define mmSRAM_Y4_X1_BANK_BASE
#define SRAM_Y4_X1_BANK_MAX_OFFSET
#define SRAM_Y4_X1_BANK_SECTION
#define mmSRAM_Y4_X1_RTR_BASE
#define SRAM_Y4_X1_RTR_MAX_OFFSET
#define SRAM_Y4_X1_RTR_SECTION
#define mmSRAM_Y4_X2_BANK_BASE
#define SRAM_Y4_X2_BANK_MAX_OFFSET
#define SRAM_Y4_X2_BANK_SECTION
#define mmSRAM_Y4_X2_RTR_BASE
#define SRAM_Y4_X2_RTR_MAX_OFFSET
#define SRAM_Y4_X2_RTR_SECTION
#define mmSRAM_Y4_X3_BANK_BASE
#define SRAM_Y4_X3_BANK_MAX_OFFSET
#define SRAM_Y4_X3_BANK_SECTION
#define mmSRAM_Y4_X3_RTR_BASE
#define SRAM_Y4_X3_RTR_MAX_OFFSET
#define SRAM_Y4_X3_RTR_SECTION
#define mmSRAM_Y4_X4_BANK_BASE
#define SRAM_Y4_X4_BANK_MAX_OFFSET
#define SRAM_Y4_X4_BANK_SECTION
#define mmSRAM_Y4_X4_RTR_BASE
#define SRAM_Y4_X4_RTR_MAX_OFFSET
#define SRAM_Y4_X4_RTR_SECTION
#define mmSRAM_Y5_X0_BANK_BASE
#define SRAM_Y5_X0_BANK_MAX_OFFSET
#define SRAM_Y5_X0_BANK_SECTION
#define mmSRAM_Y5_X0_RTR_BASE
#define SRAM_Y5_X0_RTR_MAX_OFFSET
#define SRAM_Y5_X0_RTR_SECTION
#define mmSRAM_Y5_X1_BANK_BASE
#define SRAM_Y5_X1_BANK_MAX_OFFSET
#define SRAM_Y5_X1_BANK_SECTION
#define mmSRAM_Y5_X1_RTR_BASE
#define SRAM_Y5_X1_RTR_MAX_OFFSET
#define SRAM_Y5_X1_RTR_SECTION
#define mmSRAM_Y5_X2_BANK_BASE
#define SRAM_Y5_X2_BANK_MAX_OFFSET
#define SRAM_Y5_X2_BANK_SECTION
#define mmSRAM_Y5_X2_RTR_BASE
#define SRAM_Y5_X2_RTR_MAX_OFFSET
#define SRAM_Y5_X2_RTR_SECTION
#define mmSRAM_Y5_X3_BANK_BASE
#define SRAM_Y5_X3_BANK_MAX_OFFSET
#define SRAM_Y5_X3_BANK_SECTION
#define mmSRAM_Y5_X3_RTR_BASE
#define SRAM_Y5_X3_RTR_MAX_OFFSET
#define SRAM_Y5_X3_RTR_SECTION
#define mmSRAM_Y5_X4_BANK_BASE
#define SRAM_Y5_X4_BANK_MAX_OFFSET
#define SRAM_Y5_X4_BANK_SECTION
#define mmSRAM_Y5_X4_RTR_BASE
#define SRAM_Y5_X4_RTR_MAX_OFFSET
#define SRAM_Y5_X4_RTR_SECTION
#define mmDMA_QM_0_BASE
#define DMA_QM_0_MAX_OFFSET
#define DMA_QM_0_SECTION
#define mmDMA_CH_0_BASE
#define DMA_CH_0_MAX_OFFSET
#define DMA_CH_0_SECTION
#define mmDMA_QM_1_BASE
#define DMA_QM_1_MAX_OFFSET
#define DMA_QM_1_SECTION
#define mmDMA_CH_1_BASE
#define DMA_CH_1_MAX_OFFSET
#define DMA_CH_1_SECTION
#define mmDMA_QM_2_BASE
#define DMA_QM_2_MAX_OFFSET
#define DMA_QM_2_SECTION
#define mmDMA_CH_2_BASE
#define DMA_CH_2_MAX_OFFSET
#define DMA_CH_2_SECTION
#define mmDMA_QM_3_BASE
#define DMA_QM_3_MAX_OFFSET
#define DMA_QM_3_SECTION
#define mmDMA_CH_3_BASE
#define DMA_CH_3_MAX_OFFSET
#define DMA_CH_3_SECTION
#define mmDMA_QM_4_BASE
#define DMA_QM_4_MAX_OFFSET
#define DMA_QM_4_SECTION
#define mmDMA_CH_4_BASE
#define DMA_CH_4_MAX_OFFSET
#define DMA_CH_4_SECTION
#define mmCPU_CA53_CFG_BASE
#define CPU_CA53_CFG_MAX_OFFSET
#define CPU_CA53_CFG_SECTION
#define mmCPU_IF_BASE
#define CPU_IF_MAX_OFFSET
#define CPU_IF_SECTION
#define mmCPU_TIMESTAMP_BASE
#define CPU_TIMESTAMP_MAX_OFFSET
#define CPU_TIMESTAMP_SECTION
#define mmMMU_BASE
#define MMU_MAX_OFFSET
#define MMU_SECTION
#define mmSTLB_BASE
#define STLB_MAX_OFFSET
#define STLB_SECTION
#define mmNORTH_THERMAL_SENSOR_BASE
#define NORTH_THERMAL_SENSOR_MAX_OFFSET
#define NORTH_THERMAL_SENSOR_SECTION
#define mmMC_PLL_BASE
#define MC_PLL_MAX_OFFSET
#define MC_PLL_SECTION
#define mmCPU_PLL_BASE
#define CPU_PLL_MAX_OFFSET
#define CPU_PLL_SECTION
#define mmIC_PLL_BASE
#define IC_PLL_MAX_OFFSET
#define IC_PLL_SECTION
#define mmDMA_PROCESS_MON_BASE
#define DMA_PROCESS_MON_MAX_OFFSET
#define DMA_PROCESS_MON_SECTION
#define mmDMA_MACRO_BASE
#define DMA_MACRO_MAX_OFFSET
#define DMA_MACRO_SECTION
#define mmDDR_PHY_CH0_BASE
#define DDR_PHY_CH0_MAX_OFFSET
#define DDR_PHY_CH0_SECTION
#define mmDDR_MC_CH0_BASE
#define DDR_MC_CH0_MAX_OFFSET
#define DDR_MC_CH0_SECTION
#define mmDDR_MISC_CH0_BASE
#define DDR_MISC_CH0_MAX_OFFSET
#define DDR_MISC_CH0_SECTION
#define mmDDR_PHY_CH1_BASE
#define DDR_PHY_CH1_MAX_OFFSET
#define DDR_PHY_CH1_SECTION
#define mmDDR_MC_CH1_BASE
#define DDR_MC_CH1_MAX_OFFSET
#define DDR_MC_CH1_SECTION
#define mmDDR_MISC_CH1_BASE
#define DDR_MISC_CH1_MAX_OFFSET
#define DDR_MISC_CH1_SECTION
#define mmGIC_BASE
#define GIC_MAX_OFFSET
#define GIC_SECTION
#define mmPCIE_WRAP_BASE
#define PCIE_WRAP_MAX_OFFSET
#define PCIE_WRAP_SECTION
#define mmPCIE_DBI_BASE
#define PCIE_DBI_MAX_OFFSET
#define PCIE_DBI_SECTION
#define mmPCIE_CORE_BASE
#define PCIE_CORE_MAX_OFFSET
#define PCIE_CORE_SECTION
#define mmPCIE_DB_CFG_BASE
#define PCIE_DB_CFG_MAX_OFFSET
#define PCIE_DB_CFG_SECTION
#define mmPCIE_DB_CMD_BASE
#define PCIE_DB_CMD_MAX_OFFSET
#define PCIE_DB_CMD_SECTION
#define mmPCIE_AUX_BASE
#define PCIE_AUX_MAX_OFFSET
#define PCIE_AUX_SECTION
#define mmPCIE_DB_RSV_BASE
#define PCIE_DB_RSV_MAX_OFFSET
#define PCIE_DB_RSV_SECTION
#define mmPCIE_PHY_BASE
#define PCIE_PHY_MAX_OFFSET
#define PCIE_PHY_SECTION
#define mmPSOC_I2C_M0_BASE
#define PSOC_I2C_M0_MAX_OFFSET
#define PSOC_I2C_M0_SECTION
#define mmPSOC_I2C_M1_BASE
#define PSOC_I2C_M1_MAX_OFFSET
#define PSOC_I2C_M1_SECTION
#define mmPSOC_I2C_S_BASE
#define PSOC_I2C_S_MAX_OFFSET
#define PSOC_I2C_S_SECTION
#define mmPSOC_SPI_BASE
#define PSOC_SPI_MAX_OFFSET
#define PSOC_SPI_SECTION
#define mmPSOC_EMMC_BASE
#define PSOC_EMMC_MAX_OFFSET
#define PSOC_EMMC_SECTION
#define mmPSOC_UART_0_BASE
#define PSOC_UART_0_MAX_OFFSET
#define PSOC_UART_0_SECTION
#define mmPSOC_UART_1_BASE
#define PSOC_UART_1_MAX_OFFSET
#define PSOC_UART_1_SECTION
#define mmPSOC_TIMER_BASE
#define PSOC_TIMER_MAX_OFFSET
#define PSOC_TIMER_SECTION
#define mmPSOC_WDOG_BASE
#define PSOC_WDOG_MAX_OFFSET
#define PSOC_WDOG_SECTION
#define mmPSOC_TIMESTAMP_BASE
#define PSOC_TIMESTAMP_MAX_OFFSET
#define PSOC_TIMESTAMP_SECTION
#define mmPSOC_EFUSE_BASE
#define PSOC_EFUSE_MAX_OFFSET
#define PSOC_EFUSE_SECTION
#define mmPSOC_GLOBAL_CONF_BASE
#define PSOC_GLOBAL_CONF_MAX_OFFSET
#define PSOC_GLOBAL_CONF_SECTION
#define mmPSOC_GPIO0_BASE
#define PSOC_GPIO0_MAX_OFFSET
#define PSOC_GPIO0_SECTION
#define mmPSOC_GPIO1_BASE
#define PSOC_GPIO1_MAX_OFFSET
#define PSOC_GPIO1_SECTION
#define mmPSOC_BTL_BASE
#define PSOC_BTL_MAX_OFFSET
#define PSOC_BTL_SECTION
#define mmPSOC_CS_TRACE_BASE
#define PSOC_CS_TRACE_MAX_OFFSET
#define PSOC_CS_TRACE_SECTION
#define mmPSOC_GPIO2_BASE
#define PSOC_GPIO2_MAX_OFFSET
#define PSOC_GPIO2_SECTION
#define mmPSOC_GPIO3_BASE
#define PSOC_GPIO3_MAX_OFFSET
#define PSOC_GPIO3_SECTION
#define mmPSOC_GPIO4_BASE
#define PSOC_GPIO4_MAX_OFFSET
#define PSOC_GPIO4_SECTION
#define mmPSOC_DFT_EFUSE_BASE
#define PSOC_DFT_EFUSE_MAX_OFFSET
#define PSOC_DFT_EFUSE_SECTION
#define mmPSOC_PM_BASE
#define PSOC_PM_MAX_OFFSET
#define PSOC_PM_SECTION
#define mmPSOC_TS_BASE
#define PSOC_TS_MAX_OFFSET
#define PSOC_TS_SECTION
#define mmPSOC_MII_BASE
#define PSOC_MII_MAX_OFFSET
#define PSOC_MII_SECTION
#define mmPSOC_EMMC_PLL_BASE
#define PSOC_EMMC_PLL_MAX_OFFSET
#define PSOC_EMMC_PLL_SECTION
#define mmPSOC_MME_PLL_BASE
#define PSOC_MME_PLL_MAX_OFFSET
#define PSOC_MME_PLL_SECTION
#define mmPSOC_PCI_PLL_BASE
#define PSOC_PCI_PLL_MAX_OFFSET
#define PSOC_PCI_PLL_SECTION
#define mmPSOC_PWM0_BASE
#define PSOC_PWM0_MAX_OFFSET
#define PSOC_PWM0_SECTION
#define mmPSOC_PWM1_BASE
#define PSOC_PWM1_MAX_OFFSET
#define PSOC_PWM1_SECTION
#define mmPSOC_PWM2_BASE
#define PSOC_PWM2_MAX_OFFSET
#define PSOC_PWM2_SECTION
#define mmPSOC_PWM3_BASE
#define PSOC_PWM3_MAX_OFFSET
#define PSOC_PWM3_SECTION
#define mmTPC0_NRTR_BASE
#define TPC0_NRTR_MAX_OFFSET
#define TPC0_NRTR_SECTION
#define mmTPC_PLL_BASE
#define TPC_PLL_MAX_OFFSET
#define TPC_PLL_SECTION
#define mmTPC_THEMAL_SENSOR_BASE
#define TPC_THEMAL_SENSOR_MAX_OFFSET
#define TPC_THEMAL_SENSOR_SECTION
#define mmTPC_PROCESS_MON_BASE
#define TPC_PROCESS_MON_MAX_OFFSET
#define TPC_PROCESS_MON_SECTION
#define mmTPC0_RD_REGULATOR_BASE
#define TPC0_RD_REGULATOR_MAX_OFFSET
#define TPC0_RD_REGULATOR_SECTION
#define mmTPC0_WR_REGULATOR_BASE
#define TPC0_WR_REGULATOR_MAX_OFFSET
#define TPC0_WR_REGULATOR_SECTION
#define mmTPC0_CFG_BASE
#define TPC0_CFG_MAX_OFFSET
#define TPC0_CFG_SECTION
#define mmTPC0_QM_BASE
#define TPC0_QM_MAX_OFFSET
#define TPC0_QM_SECTION
#define mmTPC0_CMDQ_BASE
#define TPC0_CMDQ_MAX_OFFSET
#define TPC0_CMDQ_SECTION
#define mmTPC1_RTR_BASE
#define TPC1_RTR_MAX_OFFSET
#define TPC1_RTR_SECTION
#define mmTPC1_WR_REGULATOR_BASE
#define TPC1_WR_REGULATOR_MAX_OFFSET
#define TPC1_WR_REGULATOR_SECTION
#define mmTPC1_RD_REGULATOR_BASE
#define TPC1_RD_REGULATOR_MAX_OFFSET
#define TPC1_RD_REGULATOR_SECTION
#define mmTPC1_CFG_BASE
#define TPC1_CFG_MAX_OFFSET
#define TPC1_CFG_SECTION
#define mmTPC1_QM_BASE
#define TPC1_QM_MAX_OFFSET
#define TPC1_QM_SECTION
#define mmTPC1_CMDQ_BASE
#define TPC1_CMDQ_MAX_OFFSET
#define TPC1_CMDQ_SECTION
#define mmTPC2_RTR_BASE
#define TPC2_RTR_MAX_OFFSET
#define TPC2_RTR_SECTION
#define mmTPC2_RD_REGULATOR_BASE
#define TPC2_RD_REGULATOR_MAX_OFFSET
#define TPC2_RD_REGULATOR_SECTION
#define mmTPC2_WR_REGULATOR_BASE
#define TPC2_WR_REGULATOR_MAX_OFFSET
#define TPC2_WR_REGULATOR_SECTION
#define mmTPC2_CFG_BASE
#define TPC2_CFG_MAX_OFFSET
#define TPC2_CFG_SECTION
#define mmTPC2_QM_BASE
#define TPC2_QM_MAX_OFFSET
#define TPC2_QM_SECTION
#define mmTPC2_CMDQ_BASE
#define TPC2_CMDQ_MAX_OFFSET
#define TPC2_CMDQ_SECTION
#define mmTPC3_RTR_BASE
#define TPC3_RTR_MAX_OFFSET
#define TPC3_RTR_SECTION
#define mmTPC3_RD_REGULATOR_BASE
#define TPC3_RD_REGULATOR_MAX_OFFSET
#define TPC3_RD_REGULATOR_SECTION
#define mmTPC3_WR_REGULATOR_BASE
#define TPC3_WR_REGULATOR_MAX_OFFSET
#define TPC3_WR_REGULATOR_SECTION
#define mmTPC3_CFG_BASE
#define TPC3_CFG_MAX_OFFSET
#define TPC3_CFG_SECTION
#define mmTPC3_QM_BASE
#define TPC3_QM_MAX_OFFSET
#define TPC3_QM_SECTION
#define mmTPC3_CMDQ_BASE
#define TPC3_CMDQ_MAX_OFFSET
#define TPC3_CMDQ_SECTION
#define mmTPC4_RTR_BASE
#define TPC4_RTR_MAX_OFFSET
#define TPC4_RTR_SECTION
#define mmTPC4_RD_REGULATOR_BASE
#define TPC4_RD_REGULATOR_MAX_OFFSET
#define TPC4_RD_REGULATOR_SECTION
#define mmTPC4_WR_REGULATOR_BASE
#define TPC4_WR_REGULATOR_MAX_OFFSET
#define TPC4_WR_REGULATOR_SECTION
#define mmTPC4_CFG_BASE
#define TPC4_CFG_MAX_OFFSET
#define TPC4_CFG_SECTION
#define mmTPC4_QM_BASE
#define TPC4_QM_MAX_OFFSET
#define TPC4_QM_SECTION
#define mmTPC4_CMDQ_BASE
#define TPC4_CMDQ_MAX_OFFSET
#define TPC4_CMDQ_SECTION
#define mmTPC5_RTR_BASE
#define TPC5_RTR_MAX_OFFSET
#define TPC5_RTR_SECTION
#define mmTPC5_RD_REGULATOR_BASE
#define TPC5_RD_REGULATOR_MAX_OFFSET
#define TPC5_RD_REGULATOR_SECTION
#define mmTPC5_WR_REGULATOR_BASE
#define TPC5_WR_REGULATOR_MAX_OFFSET
#define TPC5_WR_REGULATOR_SECTION
#define mmTPC5_CFG_BASE
#define TPC5_CFG_MAX_OFFSET
#define TPC5_CFG_SECTION
#define mmTPC5_QM_BASE
#define TPC5_QM_MAX_OFFSET
#define TPC5_QM_SECTION
#define mmTPC5_CMDQ_BASE
#define TPC5_CMDQ_MAX_OFFSET
#define TPC5_CMDQ_SECTION
#define mmTPC6_RTR_BASE
#define TPC6_RTR_MAX_OFFSET
#define TPC6_RTR_SECTION
#define mmTPC6_RD_REGULATOR_BASE
#define TPC6_RD_REGULATOR_MAX_OFFSET
#define TPC6_RD_REGULATOR_SECTION
#define mmTPC6_WR_REGULATOR_BASE
#define TPC6_WR_REGULATOR_MAX_OFFSET
#define TPC6_WR_REGULATOR_SECTION
#define mmTPC6_CFG_BASE
#define TPC6_CFG_MAX_OFFSET
#define TPC6_CFG_SECTION
#define mmTPC6_QM_BASE
#define TPC6_QM_MAX_OFFSET
#define TPC6_QM_SECTION
#define mmTPC6_CMDQ_BASE
#define TPC6_CMDQ_MAX_OFFSET
#define TPC6_CMDQ_SECTION
#define mmTPC7_NRTR_BASE
#define TPC7_NRTR_MAX_OFFSET
#define TPC7_NRTR_SECTION
#define mmTPC7_RD_REGULATOR_BASE
#define TPC7_RD_REGULATOR_MAX_OFFSET
#define TPC7_RD_REGULATOR_SECTION
#define mmTPC7_WR_REGULATOR_BASE
#define TPC7_WR_REGULATOR_MAX_OFFSET
#define TPC7_WR_REGULATOR_SECTION
#define mmTPC7_CFG_BASE
#define TPC7_CFG_MAX_OFFSET
#define TPC7_CFG_SECTION
#define mmTPC7_QM_BASE
#define TPC7_QM_MAX_OFFSET
#define TPC7_QM_SECTION
#define mmTPC7_CMDQ_BASE
#define TPC7_CMDQ_MAX_OFFSET
#define TPC7_CMDQ_SECTION
#define mmMME_TOP_TABLE_BASE
#define MME_TOP_TABLE_MAX_OFFSET
#define MME_TOP_TABLE_SECTION
#define mmMME0_RTR_FUNNEL_BASE
#define MME0_RTR_FUNNEL_MAX_OFFSET
#define MME0_RTR_FUNNEL_SECTION
#define mmMME1_RTR_FUNNEL_BASE
#define MME1_RTR_FUNNEL_MAX_OFFSET
#define MME1_RTR_FUNNEL_SECTION
#define mmMME1_SBA_STM_BASE
#define MME1_SBA_STM_MAX_OFFSET
#define MME1_SBA_STM_SECTION
#define mmMME1_SBA_CTI_BASE
#define MME1_SBA_CTI_MAX_OFFSET
#define MME1_SBA_CTI_SECTION
#define mmMME1_SBA_ETF_BASE
#define MME1_SBA_ETF_MAX_OFFSET
#define MME1_SBA_ETF_SECTION
#define mmMME1_SBA_SPMU_BASE
#define MME1_SBA_SPMU_MAX_OFFSET
#define MME1_SBA_SPMU_SECTION
#define mmMME1_SBA_CTI0_BASE
#define MME1_SBA_CTI0_MAX_OFFSET
#define MME1_SBA_CTI0_SECTION
#define mmMME1_SBA_CTI1_BASE
#define MME1_SBA_CTI1_MAX_OFFSET
#define MME1_SBA_CTI1_SECTION
#define mmMME1_SBA_BMON0_BASE
#define MME1_SBA_BMON0_MAX_OFFSET
#define MME1_SBA_BMON0_SECTION
#define mmMME1_SBA_BMON1_BASE
#define MME1_SBA_BMON1_MAX_OFFSET
#define MME1_SBA_BMON1_SECTION
#define mmMME2_RTR_FUNNEL_BASE
#define MME2_RTR_FUNNEL_MAX_OFFSET
#define MME2_RTR_FUNNEL_SECTION
#define mmMME3_RTR_FUNNEL_BASE
#define MME3_RTR_FUNNEL_MAX_OFFSET
#define MME3_RTR_FUNNEL_SECTION
#define mmMME3_SBB_STM_BASE
#define MME3_SBB_STM_MAX_OFFSET
#define MME3_SBB_STM_SECTION
#define mmMME3_SBB_CTI_BASE
#define MME3_SBB_CTI_MAX_OFFSET
#define MME3_SBB_CTI_SECTION
#define mmMME3_SBB_ETF_BASE
#define MME3_SBB_ETF_MAX_OFFSET
#define MME3_SBB_ETF_SECTION
#define mmMME3_SBB_SPMU_BASE
#define MME3_SBB_SPMU_MAX_OFFSET
#define MME3_SBB_SPMU_SECTION
#define mmMME3_SBB_CTI0_BASE
#define MME3_SBB_CTI0_MAX_OFFSET
#define MME3_SBB_CTI0_SECTION
#define mmMME3_SBB_CTI1_BASE
#define MME3_SBB_CTI1_MAX_OFFSET
#define MME3_SBB_CTI1_SECTION
#define mmMME3_SBB_BMON0_BASE
#define MME3_SBB_BMON0_MAX_OFFSET
#define MME3_SBB_BMON0_SECTION
#define mmMME3_SBB_BMON1_BASE
#define MME3_SBB_BMON1_MAX_OFFSET
#define MME3_SBB_BMON1_SECTION
#define mmMME4_RTR_FUNNEL_BASE
#define MME4_RTR_FUNNEL_MAX_OFFSET
#define MME4_RTR_FUNNEL_SECTION
#define mmMME4_WACS_STM_BASE
#define MME4_WACS_STM_MAX_OFFSET
#define MME4_WACS_STM_SECTION
#define mmMME4_WACS_CTI_BASE
#define MME4_WACS_CTI_MAX_OFFSET
#define MME4_WACS_CTI_SECTION
#define mmMME4_WACS_ETF_BASE
#define MME4_WACS_ETF_MAX_OFFSET
#define MME4_WACS_ETF_SECTION
#define mmMME4_WACS_SPMU_BASE
#define MME4_WACS_SPMU_MAX_OFFSET
#define MME4_WACS_SPMU_SECTION
#define mmMME4_WACS_CTI0_BASE
#define MME4_WACS_CTI0_MAX_OFFSET
#define MME4_WACS_CTI0_SECTION
#define mmMME4_WACS_CTI1_BASE
#define MME4_WACS_CTI1_MAX_OFFSET
#define MME4_WACS_CTI1_SECTION
#define mmMME4_WACS_BMON0_BASE
#define MME4_WACS_BMON0_MAX_OFFSET
#define MME4_WACS_BMON0_SECTION
#define mmMME4_WACS_BMON1_BASE
#define MME4_WACS_BMON1_MAX_OFFSET
#define MME4_WACS_BMON1_SECTION
#define mmMME4_WACS_BMON2_BASE
#define MME4_WACS_BMON2_MAX_OFFSET
#define MME4_WACS_BMON2_SECTION
#define mmMME4_WACS_BMON3_BASE
#define MME4_WACS_BMON3_MAX_OFFSET
#define MME4_WACS_BMON3_SECTION
#define mmMME4_WACS_BMON4_BASE
#define MME4_WACS_BMON4_MAX_OFFSET
#define MME4_WACS_BMON4_SECTION
#define mmMME4_WACS_BMON5_BASE
#define MME4_WACS_BMON5_MAX_OFFSET
#define MME4_WACS_BMON5_SECTION
#define mmMME4_WACS_BMON6_BASE
#define MME4_WACS_BMON6_MAX_OFFSET
#define MME4_WACS_BMON6_SECTION
#define mmMME4_WACS2_STM_BASE
#define MME4_WACS2_STM_MAX_OFFSET
#define MME4_WACS2_STM_SECTION
#define mmMME4_WACS2_CTI_BASE
#define MME4_WACS2_CTI_MAX_OFFSET
#define MME4_WACS2_CTI_SECTION
#define mmMME4_WACS2_ETF_BASE
#define MME4_WACS2_ETF_MAX_OFFSET
#define MME4_WACS2_ETF_SECTION
#define mmMME4_WACS2_SPMU_BASE
#define MME4_WACS2_SPMU_MAX_OFFSET
#define MME4_WACS2_SPMU_SECTION
#define mmMME4_WACS2_CTI0_BASE
#define MME4_WACS2_CTI0_MAX_OFFSET
#define MME4_WACS2_CTI0_SECTION
#define mmMME4_WACS2_CTI1_BASE
#define MME4_WACS2_CTI1_MAX_OFFSET
#define MME4_WACS2_CTI1_SECTION
#define mmMME4_WACS2_BMON0_BASE
#define MME4_WACS2_BMON0_MAX_OFFSET
#define MME4_WACS2_BMON0_SECTION
#define mmMME4_WACS2_BMON1_BASE
#define MME4_WACS2_BMON1_MAX_OFFSET
#define MME4_WACS2_BMON1_SECTION
#define mmMME4_WACS2_BMON2_BASE
#define MME4_WACS2_BMON2_MAX_OFFSET
#define MME4_WACS2_BMON2_SECTION
#define mmMME5_RTR_FUNNEL_BASE
#define MME5_RTR_FUNNEL_MAX_OFFSET
#define MME5_RTR_FUNNEL_SECTION
#define mmDMA_ROM_TABLE_BASE
#define DMA_ROM_TABLE_MAX_OFFSET
#define DMA_ROM_TABLE_SECTION
#define mmDMA_CH_0_CS_STM_BASE
#define DMA_CH_0_CS_STM_MAX_OFFSET
#define DMA_CH_0_CS_STM_SECTION
#define mmDMA_CH_0_CS_CTI_BASE
#define DMA_CH_0_CS_CTI_MAX_OFFSET
#define DMA_CH_0_CS_CTI_SECTION
#define mmDMA_CH_0_CS_ETF_BASE
#define DMA_CH_0_CS_ETF_MAX_OFFSET
#define DMA_CH_0_CS_ETF_SECTION
#define mmDMA_CH_0_CS_SPMU_BASE
#define DMA_CH_0_CS_SPMU_MAX_OFFSET
#define DMA_CH_0_CS_SPMU_SECTION
#define mmDMA_CH_0_BMON_CTI_BASE
#define DMA_CH_0_BMON_CTI_MAX_OFFSET
#define DMA_CH_0_BMON_CTI_SECTION
#define mmDMA_CH_0_USER_CTI_BASE
#define DMA_CH_0_USER_CTI_MAX_OFFSET
#define DMA_CH_0_USER_CTI_SECTION
#define mmDMA_CH_0_BMON_0_BASE
#define DMA_CH_0_BMON_0_MAX_OFFSET
#define DMA_CH_0_BMON_0_SECTION
#define mmDMA_CH_0_BMON_1_BASE
#define DMA_CH_0_BMON_1_MAX_OFFSET
#define DMA_CH_0_BMON_1_SECTION
#define mmDMA_CH_1_CS_STM_BASE
#define DMA_CH_1_CS_STM_MAX_OFFSET
#define DMA_CH_1_CS_STM_SECTION
#define mmDMA_CH_1_CS_CTI_BASE
#define DMA_CH_1_CS_CTI_MAX_OFFSET
#define DMA_CH_1_CS_CTI_SECTION
#define mmDMA_CH_1_CS_ETF_BASE
#define DMA_CH_1_CS_ETF_MAX_OFFSET
#define DMA_CH_1_CS_ETF_SECTION
#define mmDMA_CH_1_CS_SPMU_BASE
#define DMA_CH_1_CS_SPMU_MAX_OFFSET
#define DMA_CH_1_CS_SPMU_SECTION
#define mmDMA_CH_1_BMON_CTI_BASE
#define DMA_CH_1_BMON_CTI_MAX_OFFSET
#define DMA_CH_1_BMON_CTI_SECTION
#define mmDMA_CH_1_USER_CTI_BASE
#define DMA_CH_1_USER_CTI_MAX_OFFSET
#define DMA_CH_1_USER_CTI_SECTION
#define mmDMA_CH_1_BMON_0_BASE
#define DMA_CH_1_BMON_0_MAX_OFFSET
#define DMA_CH_1_BMON_0_SECTION
#define mmDMA_CH_1_BMON_1_BASE
#define DMA_CH_1_BMON_1_MAX_OFFSET
#define DMA_CH_1_BMON_1_SECTION
#define mmDMA_CH_2_CS_STM_BASE
#define DMA_CH_2_CS_STM_MAX_OFFSET
#define DMA_CH_2_CS_STM_SECTION
#define mmDMA_CH_2_CS_CTI_BASE
#define DMA_CH_2_CS_CTI_MAX_OFFSET
#define DMA_CH_2_CS_CTI_SECTION
#define mmDMA_CH_2_CS_ETF_BASE
#define DMA_CH_2_CS_ETF_MAX_OFFSET
#define DMA_CH_2_CS_ETF_SECTION
#define mmDMA_CH_2_CS_SPMU_BASE
#define DMA_CH_2_CS_SPMU_MAX_OFFSET
#define DMA_CH_2_CS_SPMU_SECTION
#define mmDMA_CH_2_BMON_CTI_BASE
#define DMA_CH_2_BMON_CTI_MAX_OFFSET
#define DMA_CH_2_BMON_CTI_SECTION
#define mmDMA_CH_2_USER_CTI_BASE
#define DMA_CH_2_USER_CTI_MAX_OFFSET
#define DMA_CH_2_USER_CTI_SECTION
#define mmDMA_CH_2_BMON_0_BASE
#define DMA_CH_2_BMON_0_MAX_OFFSET
#define DMA_CH_2_BMON_0_SECTION
#define mmDMA_CH_2_BMON_1_BASE
#define DMA_CH_2_BMON_1_MAX_OFFSET
#define DMA_CH_2_BMON_1_SECTION
#define mmDMA_CH_3_CS_STM_BASE
#define DMA_CH_3_CS_STM_MAX_OFFSET
#define DMA_CH_3_CS_STM_SECTION
#define mmDMA_CH_3_CS_CTI_BASE
#define DMA_CH_3_CS_CTI_MAX_OFFSET
#define DMA_CH_3_CS_CTI_SECTION
#define mmDMA_CH_3_CS_ETF_BASE
#define DMA_CH_3_CS_ETF_MAX_OFFSET
#define DMA_CH_3_CS_ETF_SECTION
#define mmDMA_CH_3_CS_SPMU_BASE
#define DMA_CH_3_CS_SPMU_MAX_OFFSET
#define DMA_CH_3_CS_SPMU_SECTION
#define mmDMA_CH_3_BMON_CTI_BASE
#define DMA_CH_3_BMON_CTI_MAX_OFFSET
#define DMA_CH_3_BMON_CTI_SECTION
#define mmDMA_CH_3_USER_CTI_BASE
#define DMA_CH_3_USER_CTI_MAX_OFFSET
#define DMA_CH_3_USER_CTI_SECTION
#define mmDMA_CH_3_BMON_0_BASE
#define DMA_CH_3_BMON_0_MAX_OFFSET
#define DMA_CH_3_BMON_0_SECTION
#define mmDMA_CH_3_BMON_1_BASE
#define DMA_CH_3_BMON_1_MAX_OFFSET
#define DMA_CH_3_BMON_1_SECTION
#define mmDMA_CH_4_CS_STM_BASE
#define DMA_CH_4_CS_STM_MAX_OFFSET
#define DMA_CH_4_CS_STM_SECTION
#define mmDMA_CH_4_CS_CTI_BASE
#define DMA_CH_4_CS_CTI_MAX_OFFSET
#define DMA_CH_4_CS_CTI_SECTION
#define mmDMA_CH_4_CS_ETF_BASE
#define DMA_CH_4_CS_ETF_MAX_OFFSET
#define DMA_CH_4_CS_ETF_SECTION
#define mmDMA_CH_4_CS_SPMU_BASE
#define DMA_CH_4_CS_SPMU_MAX_OFFSET
#define DMA_CH_4_CS_SPMU_SECTION
#define mmDMA_CH_4_BMON_CTI_BASE
#define DMA_CH_4_BMON_CTI_MAX_OFFSET
#define DMA_CH_4_BMON_CTI_SECTION
#define mmDMA_CH_4_USER_CTI_BASE
#define DMA_CH_4_USER_CTI_MAX_OFFSET
#define DMA_CH_4_USER_CTI_SECTION
#define mmDMA_CH_4_BMON_0_BASE
#define DMA_CH_4_BMON_0_MAX_OFFSET
#define DMA_CH_4_BMON_0_SECTION
#define mmDMA_CH_4_BMON_1_BASE
#define DMA_CH_4_BMON_1_MAX_OFFSET
#define DMA_CH_4_BMON_1_SECTION
#define mmDMA_CH_FUNNEL_6_1_BASE
#define DMA_CH_FUNNEL_6_1_MAX_OFFSET
#define DMA_CH_FUNNEL_6_1_SECTION
#define mmDMA_MACRO_CS_STM_BASE
#define DMA_MACRO_CS_STM_MAX_OFFSET
#define DMA_MACRO_CS_STM_SECTION
#define mmDMA_MACRO_CS_CTI_BASE
#define DMA_MACRO_CS_CTI_MAX_OFFSET
#define DMA_MACRO_CS_CTI_SECTION
#define mmDMA_MACRO_CS_ETF_BASE
#define DMA_MACRO_CS_ETF_MAX_OFFSET
#define DMA_MACRO_CS_ETF_SECTION
#define mmDMA_MACRO_CS_SPMU_BASE
#define DMA_MACRO_CS_SPMU_MAX_OFFSET
#define DMA_MACRO_CS_SPMU_SECTION
#define mmDMA_MACRO_BMON_CTI_BASE
#define DMA_MACRO_BMON_CTI_MAX_OFFSET
#define DMA_MACRO_BMON_CTI_SECTION
#define mmDMA_MACRO_USER_CTI_BASE
#define DMA_MACRO_USER_CTI_MAX_OFFSET
#define DMA_MACRO_USER_CTI_SECTION
#define mmDMA_MACRO_BMON_0_BASE
#define DMA_MACRO_BMON_0_MAX_OFFSET
#define DMA_MACRO_BMON_0_SECTION
#define mmDMA_MACRO_BMON_1_BASE
#define DMA_MACRO_BMON_1_MAX_OFFSET
#define DMA_MACRO_BMON_1_SECTION
#define mmDMA_MACRO_BMON_2_BASE
#define DMA_MACRO_BMON_2_MAX_OFFSET
#define DMA_MACRO_BMON_2_SECTION
#define mmDMA_MACRO_BMON_3_BASE
#define DMA_MACRO_BMON_3_MAX_OFFSET
#define DMA_MACRO_BMON_3_SECTION
#define mmDMA_MACRO_BMON_4_BASE
#define DMA_MACRO_BMON_4_MAX_OFFSET
#define DMA_MACRO_BMON_4_SECTION
#define mmDMA_MACRO_BMON_5_BASE
#define DMA_MACRO_BMON_5_MAX_OFFSET
#define DMA_MACRO_BMON_5_SECTION
#define mmDMA_MACRO_BMON_6_BASE
#define DMA_MACRO_BMON_6_MAX_OFFSET
#define DMA_MACRO_BMON_6_SECTION
#define mmDMA_MACRO_BMON_7_BASE
#define DMA_MACRO_BMON_7_MAX_OFFSET
#define DMA_MACRO_BMON_7_SECTION
#define mmDMA_MACRO_FUNNEL_3_1_BASE
#define DMA_MACRO_FUNNEL_3_1_MAX_OFFSET
#define DMA_MACRO_FUNNEL_3_1_SECTION
#define mmCPU_ROM_TABLE_BASE
#define CPU_ROM_TABLE_MAX_OFFSET
#define CPU_ROM_TABLE_SECTION
#define mmCPU_ETF_0_BASE
#define CPU_ETF_0_MAX_OFFSET
#define CPU_ETF_0_SECTION
#define mmCPU_ETF_1_BASE
#define CPU_ETF_1_MAX_OFFSET
#define CPU_ETF_1_SECTION
#define mmCPU_CTI_BASE
#define CPU_CTI_MAX_OFFSET
#define CPU_CTI_SECTION
#define mmCPU_FUNNEL_BASE
#define CPU_FUNNEL_MAX_OFFSET
#define CPU_FUNNEL_SECTION
#define mmCPU_STM_BASE
#define CPU_STM_MAX_OFFSET
#define CPU_STM_SECTION
#define mmCPU_CTI_TRACE_BASE
#define CPU_CTI_TRACE_MAX_OFFSET
#define CPU_CTI_TRACE_SECTION
#define mmCPU_ETF_TRACE_BASE
#define CPU_ETF_TRACE_MAX_OFFSET
#define CPU_ETF_TRACE_SECTION
#define mmCPU_WR_BMON_BASE
#define CPU_WR_BMON_MAX_OFFSET
#define CPU_WR_BMON_SECTION
#define mmCPU_RD_BMON_BASE
#define CPU_RD_BMON_MAX_OFFSET
#define CPU_RD_BMON_SECTION
#define mmMMU_CS_STM_BASE
#define MMU_CS_STM_MAX_OFFSET
#define MMU_CS_STM_SECTION
#define mmMMU_CS_CTI_BASE
#define MMU_CS_CTI_MAX_OFFSET
#define MMU_CS_CTI_SECTION
#define mmMMU_CS_ETF_BASE
#define MMU_CS_ETF_MAX_OFFSET
#define MMU_CS_ETF_SECTION
#define mmMMU_CS_SPMU_BASE
#define MMU_CS_SPMU_MAX_OFFSET
#define MMU_CS_SPMU_SECTION
#define mmMMU_BMON_CTI_BASE
#define MMU_BMON_CTI_MAX_OFFSET
#define MMU_BMON_CTI_SECTION
#define mmMMU_USER_CTI_BASE
#define MMU_USER_CTI_MAX_OFFSET
#define MMU_USER_CTI_SECTION
#define mmMMU_BMON_0_BASE
#define MMU_BMON_0_MAX_OFFSET
#define MMU_BMON_0_SECTION
#define mmMMU_BMON_1_BASE
#define MMU_BMON_1_MAX_OFFSET
#define MMU_BMON_1_SECTION
#define mmCA53_BASE
#define CA53_MAX_OFFSET
#define CA53_SECTION
#define mmPCI_ROM_TABLE_BASE
#define PCI_ROM_TABLE_MAX_OFFSET
#define PCI_ROM_TABLE_SECTION
#define mmPCIE_STM_BASE
#define PCIE_STM_MAX_OFFSET
#define PCIE_STM_SECTION
#define mmPCIE_ETF_BASE
#define PCIE_ETF_MAX_OFFSET
#define PCIE_ETF_SECTION
#define mmPCIE_CTI_0_BASE
#define PCIE_CTI_0_MAX_OFFSET
#define PCIE_CTI_0_SECTION
#define mmPCIE_SPMU_BASE
#define PCIE_SPMU_MAX_OFFSET
#define PCIE_SPMU_SECTION
#define mmPCIE_CTI_1_BASE
#define PCIE_CTI_1_MAX_OFFSET
#define PCIE_CTI_1_SECTION
#define mmPCIE_FUNNEL_BASE
#define PCIE_FUNNEL_MAX_OFFSET
#define PCIE_FUNNEL_SECTION
#define mmPCIE_BMON_MSTR_WR_BASE
#define PCIE_BMON_MSTR_WR_MAX_OFFSET
#define PCIE_BMON_MSTR_WR_SECTION
#define mmPCIE_BMON_MSTR_RD_BASE
#define PCIE_BMON_MSTR_RD_MAX_OFFSET
#define PCIE_BMON_MSTR_RD_SECTION
#define mmPCIE_BMON_SLV_WR_BASE
#define PCIE_BMON_SLV_WR_MAX_OFFSET
#define PCIE_BMON_SLV_WR_SECTION
#define mmPCIE_BMON_SLV_RD_BASE
#define PCIE_BMON_SLV_RD_MAX_OFFSET
#define PCIE_BMON_SLV_RD_SECTION
#define mmPSOC_CTI_BASE
#define PSOC_CTI_MAX_OFFSET
#define PSOC_CTI_SECTION
#define mmPSOC_STM_BASE
#define PSOC_STM_MAX_OFFSET
#define PSOC_STM_SECTION
#define mmPSOC_FUNNEL_BASE
#define PSOC_FUNNEL_MAX_OFFSET
#define PSOC_FUNNEL_SECTION
#define mmPSOC_ETR_BASE
#define PSOC_ETR_MAX_OFFSET
#define PSOC_ETR_SECTION
#define mmPSOC_ETF_BASE
#define PSOC_ETF_MAX_OFFSET
#define PSOC_ETF_SECTION
#define mmPSOC_TS_CTI_BASE
#define PSOC_TS_CTI_MAX_OFFSET
#define PSOC_TS_CTI_SECTION
#define mmTOP_ROM_TABLE_BASE
#define TOP_ROM_TABLE_MAX_OFFSET
#define TOP_ROM_TABLE_SECTION
#define mmTPC1_RTR_FUNNEL_BASE
#define TPC1_RTR_FUNNEL_MAX_OFFSET
#define TPC1_RTR_FUNNEL_SECTION
#define mmTPC2_RTR_FUNNEL_BASE
#define TPC2_RTR_FUNNEL_MAX_OFFSET
#define TPC2_RTR_FUNNEL_SECTION
#define mmTPC3_RTR_FUNNEL_BASE
#define TPC3_RTR_FUNNEL_MAX_OFFSET
#define TPC3_RTR_FUNNEL_SECTION
#define mmTPC4_RTR_FUNNEL_BASE
#define TPC4_RTR_FUNNEL_MAX_OFFSET
#define TPC4_RTR_FUNNEL_SECTION
#define mmTPC5_RTR_FUNNEL_BASE
#define TPC5_RTR_FUNNEL_MAX_OFFSET
#define TPC5_RTR_FUNNEL_SECTION
#define mmTPC6_RTR_FUNNEL_BASE
#define TPC6_RTR_FUNNEL_MAX_OFFSET
#define TPC6_RTR_FUNNEL_SECTION
#define mmTPC0_EML_SPMU_BASE
#define TPC0_EML_SPMU_MAX_OFFSET
#define TPC0_EML_SPMU_SECTION
#define mmTPC0_EML_ETF_BASE
#define TPC0_EML_ETF_MAX_OFFSET
#define TPC0_EML_ETF_SECTION
#define mmTPC0_EML_STM_BASE
#define TPC0_EML_STM_MAX_OFFSET
#define TPC0_EML_STM_SECTION
#define mmTPC0_EML_ETM_R4_BASE
#define TPC0_EML_ETM_R4_MAX_OFFSET
#define TPC0_EML_ETM_R4_SECTION
#define mmTPC0_EML_CTI_BASE
#define TPC0_EML_CTI_MAX_OFFSET
#define TPC0_EML_CTI_SECTION
#define mmTPC0_EML_FUNNEL_BASE
#define TPC0_EML_FUNNEL_MAX_OFFSET
#define TPC0_EML_FUNNEL_SECTION
#define mmTPC0_EML_BUSMON_0_BASE
#define TPC0_EML_BUSMON_0_MAX_OFFSET
#define TPC0_EML_BUSMON_0_SECTION
#define mmTPC0_EML_BUSMON_1_BASE
#define TPC0_EML_BUSMON_1_MAX_OFFSET
#define TPC0_EML_BUSMON_1_SECTION
#define mmTPC0_EML_BUSMON_2_BASE
#define TPC0_EML_BUSMON_2_MAX_OFFSET
#define TPC0_EML_BUSMON_2_SECTION
#define mmTPC0_EML_BUSMON_3_BASE
#define TPC0_EML_BUSMON_3_MAX_OFFSET
#define TPC0_EML_BUSMON_3_SECTION
#define mmTPC0_EML_CFG_BASE
#define TPC0_EML_CFG_MAX_OFFSET
#define TPC0_EML_CFG_SECTION
#define mmTPC0_EML_CS_BASE
#define TPC0_EML_CS_MAX_OFFSET
#define TPC0_EML_CS_SECTION
#define mmTPC1_EML_SPMU_BASE
#define TPC1_EML_SPMU_MAX_OFFSET
#define TPC1_EML_SPMU_SECTION
#define mmTPC1_EML_ETF_BASE
#define TPC1_EML_ETF_MAX_OFFSET
#define TPC1_EML_ETF_SECTION
#define mmTPC1_EML_STM_BASE
#define TPC1_EML_STM_MAX_OFFSET
#define TPC1_EML_STM_SECTION
#define mmTPC1_EML_ETM_R4_BASE
#define TPC1_EML_ETM_R4_MAX_OFFSET
#define TPC1_EML_ETM_R4_SECTION
#define mmTPC1_EML_CTI_BASE
#define TPC1_EML_CTI_MAX_OFFSET
#define TPC1_EML_CTI_SECTION
#define mmTPC1_EML_FUNNEL_BASE
#define TPC1_EML_FUNNEL_MAX_OFFSET
#define TPC1_EML_FUNNEL_SECTION
#define mmTPC1_EML_BUSMON_0_BASE
#define TPC1_EML_BUSMON_0_MAX_OFFSET
#define TPC1_EML_BUSMON_0_SECTION
#define mmTPC1_EML_BUSMON_1_BASE
#define TPC1_EML_BUSMON_1_MAX_OFFSET
#define TPC1_EML_BUSMON_1_SECTION
#define mmTPC1_EML_BUSMON_2_BASE
#define TPC1_EML_BUSMON_2_MAX_OFFSET
#define TPC1_EML_BUSMON_2_SECTION
#define mmTPC1_EML_BUSMON_3_BASE
#define TPC1_EML_BUSMON_3_MAX_OFFSET
#define TPC1_EML_BUSMON_3_SECTION
#define mmTPC1_EML_CFG_BASE
#define TPC1_EML_CFG_MAX_OFFSET
#define TPC1_EML_CFG_SECTION
#define mmTPC1_EML_CS_BASE
#define TPC1_EML_CS_MAX_OFFSET
#define TPC1_EML_CS_SECTION
#define mmTPC2_EML_SPMU_BASE
#define TPC2_EML_SPMU_MAX_OFFSET
#define TPC2_EML_SPMU_SECTION
#define mmTPC2_EML_ETF_BASE
#define TPC2_EML_ETF_MAX_OFFSET
#define TPC2_EML_ETF_SECTION
#define mmTPC2_EML_STM_BASE
#define TPC2_EML_STM_MAX_OFFSET
#define TPC2_EML_STM_SECTION
#define mmTPC2_EML_ETM_R4_BASE
#define TPC2_EML_ETM_R4_MAX_OFFSET
#define TPC2_EML_ETM_R4_SECTION
#define mmTPC2_EML_CTI_BASE
#define TPC2_EML_CTI_MAX_OFFSET
#define TPC2_EML_CTI_SECTION
#define mmTPC2_EML_FUNNEL_BASE
#define TPC2_EML_FUNNEL_MAX_OFFSET
#define TPC2_EML_FUNNEL_SECTION
#define mmTPC2_EML_BUSMON_0_BASE
#define TPC2_EML_BUSMON_0_MAX_OFFSET
#define TPC2_EML_BUSMON_0_SECTION
#define mmTPC2_EML_BUSMON_1_BASE
#define TPC2_EML_BUSMON_1_MAX_OFFSET
#define TPC2_EML_BUSMON_1_SECTION
#define mmTPC2_EML_BUSMON_2_BASE
#define TPC2_EML_BUSMON_2_MAX_OFFSET
#define TPC2_EML_BUSMON_2_SECTION
#define mmTPC2_EML_BUSMON_3_BASE
#define TPC2_EML_BUSMON_3_MAX_OFFSET
#define TPC2_EML_BUSMON_3_SECTION
#define mmTPC2_EML_CFG_BASE
#define TPC2_EML_CFG_MAX_OFFSET
#define TPC2_EML_CFG_SECTION
#define mmTPC2_EML_CS_BASE
#define TPC2_EML_CS_MAX_OFFSET
#define TPC2_EML_CS_SECTION
#define mmTPC3_EML_SPMU_BASE
#define TPC3_EML_SPMU_MAX_OFFSET
#define TPC3_EML_SPMU_SECTION
#define mmTPC3_EML_ETF_BASE
#define TPC3_EML_ETF_MAX_OFFSET
#define TPC3_EML_ETF_SECTION
#define mmTPC3_EML_STM_BASE
#define TPC3_EML_STM_MAX_OFFSET
#define TPC3_EML_STM_SECTION
#define mmTPC3_EML_ETM_R4_BASE
#define TPC3_EML_ETM_R4_MAX_OFFSET
#define TPC3_EML_ETM_R4_SECTION
#define mmTPC3_EML_CTI_BASE
#define TPC3_EML_CTI_MAX_OFFSET
#define TPC3_EML_CTI_SECTION
#define mmTPC3_EML_FUNNEL_BASE
#define TPC3_EML_FUNNEL_MAX_OFFSET
#define TPC3_EML_FUNNEL_SECTION
#define mmTPC3_EML_BUSMON_0_BASE
#define TPC3_EML_BUSMON_0_MAX_OFFSET
#define TPC3_EML_BUSMON_0_SECTION
#define mmTPC3_EML_BUSMON_1_BASE
#define TPC3_EML_BUSMON_1_MAX_OFFSET
#define TPC3_EML_BUSMON_1_SECTION
#define mmTPC3_EML_BUSMON_2_BASE
#define TPC3_EML_BUSMON_2_MAX_OFFSET
#define TPC3_EML_BUSMON_2_SECTION
#define mmTPC3_EML_BUSMON_3_BASE
#define TPC3_EML_BUSMON_3_MAX_OFFSET
#define TPC3_EML_BUSMON_3_SECTION
#define mmTPC3_EML_CFG_BASE
#define TPC3_EML_CFG_MAX_OFFSET
#define TPC3_EML_CFG_SECTION
#define mmTPC3_EML_CS_BASE
#define TPC3_EML_CS_MAX_OFFSET
#define TPC3_EML_CS_SECTION
#define mmTPC4_EML_SPMU_BASE
#define TPC4_EML_SPMU_MAX_OFFSET
#define TPC4_EML_SPMU_SECTION
#define mmTPC4_EML_ETF_BASE
#define TPC4_EML_ETF_MAX_OFFSET
#define TPC4_EML_ETF_SECTION
#define mmTPC4_EML_STM_BASE
#define TPC4_EML_STM_MAX_OFFSET
#define TPC4_EML_STM_SECTION
#define mmTPC4_EML_ETM_R4_BASE
#define TPC4_EML_ETM_R4_MAX_OFFSET
#define TPC4_EML_ETM_R4_SECTION
#define mmTPC4_EML_CTI_BASE
#define TPC4_EML_CTI_MAX_OFFSET
#define TPC4_EML_CTI_SECTION
#define mmTPC4_EML_FUNNEL_BASE
#define TPC4_EML_FUNNEL_MAX_OFFSET
#define TPC4_EML_FUNNEL_SECTION
#define mmTPC4_EML_BUSMON_0_BASE
#define TPC4_EML_BUSMON_0_MAX_OFFSET
#define TPC4_EML_BUSMON_0_SECTION
#define mmTPC4_EML_BUSMON_1_BASE
#define TPC4_EML_BUSMON_1_MAX_OFFSET
#define TPC4_EML_BUSMON_1_SECTION
#define mmTPC4_EML_BUSMON_2_BASE
#define TPC4_EML_BUSMON_2_MAX_OFFSET
#define TPC4_EML_BUSMON_2_SECTION
#define mmTPC4_EML_BUSMON_3_BASE
#define TPC4_EML_BUSMON_3_MAX_OFFSET
#define TPC4_EML_BUSMON_3_SECTION
#define mmTPC4_EML_CFG_BASE
#define TPC4_EML_CFG_MAX_OFFSET
#define TPC4_EML_CFG_SECTION
#define mmTPC4_EML_CS_BASE
#define TPC4_EML_CS_MAX_OFFSET
#define TPC4_EML_CS_SECTION
#define mmTPC5_EML_SPMU_BASE
#define TPC5_EML_SPMU_MAX_OFFSET
#define TPC5_EML_SPMU_SECTION
#define mmTPC5_EML_ETF_BASE
#define TPC5_EML_ETF_MAX_OFFSET
#define TPC5_EML_ETF_SECTION
#define mmTPC5_EML_STM_BASE
#define TPC5_EML_STM_MAX_OFFSET
#define TPC5_EML_STM_SECTION
#define mmTPC5_EML_ETM_R4_BASE
#define TPC5_EML_ETM_R4_MAX_OFFSET
#define TPC5_EML_ETM_R4_SECTION
#define mmTPC5_EML_CTI_BASE
#define TPC5_EML_CTI_MAX_OFFSET
#define TPC5_EML_CTI_SECTION
#define mmTPC5_EML_FUNNEL_BASE
#define TPC5_EML_FUNNEL_MAX_OFFSET
#define TPC5_EML_FUNNEL_SECTION
#define mmTPC5_EML_BUSMON_0_BASE
#define TPC5_EML_BUSMON_0_MAX_OFFSET
#define TPC5_EML_BUSMON_0_SECTION
#define mmTPC5_EML_BUSMON_1_BASE
#define TPC5_EML_BUSMON_1_MAX_OFFSET
#define TPC5_EML_BUSMON_1_SECTION
#define mmTPC5_EML_BUSMON_2_BASE
#define TPC5_EML_BUSMON_2_MAX_OFFSET
#define TPC5_EML_BUSMON_2_SECTION
#define mmTPC5_EML_BUSMON_3_BASE
#define TPC5_EML_BUSMON_3_MAX_OFFSET
#define TPC5_EML_BUSMON_3_SECTION
#define mmTPC5_EML_CFG_BASE
#define TPC5_EML_CFG_MAX_OFFSET
#define TPC5_EML_CFG_SECTION
#define mmTPC5_EML_CS_BASE
#define TPC5_EML_CS_MAX_OFFSET
#define TPC5_EML_CS_SECTION
#define mmTPC6_EML_SPMU_BASE
#define TPC6_EML_SPMU_MAX_OFFSET
#define TPC6_EML_SPMU_SECTION
#define mmTPC6_EML_ETF_BASE
#define TPC6_EML_ETF_MAX_OFFSET
#define TPC6_EML_ETF_SECTION
#define mmTPC6_EML_STM_BASE
#define TPC6_EML_STM_MAX_OFFSET
#define TPC6_EML_STM_SECTION
#define mmTPC6_EML_ETM_R4_BASE
#define TPC6_EML_ETM_R4_MAX_OFFSET
#define TPC6_EML_ETM_R4_SECTION
#define mmTPC6_EML_CTI_BASE
#define TPC6_EML_CTI_MAX_OFFSET
#define TPC6_EML_CTI_SECTION
#define mmTPC6_EML_FUNNEL_BASE
#define TPC6_EML_FUNNEL_MAX_OFFSET
#define TPC6_EML_FUNNEL_SECTION
#define mmTPC6_EML_BUSMON_0_BASE
#define TPC6_EML_BUSMON_0_MAX_OFFSET
#define TPC6_EML_BUSMON_0_SECTION
#define mmTPC6_EML_BUSMON_1_BASE
#define TPC6_EML_BUSMON_1_MAX_OFFSET
#define TPC6_EML_BUSMON_1_SECTION
#define mmTPC6_EML_BUSMON_2_BASE
#define TPC6_EML_BUSMON_2_MAX_OFFSET
#define TPC6_EML_BUSMON_2_SECTION
#define mmTPC6_EML_BUSMON_3_BASE
#define TPC6_EML_BUSMON_3_MAX_OFFSET
#define TPC6_EML_BUSMON_3_SECTION
#define mmTPC6_EML_CFG_BASE
#define TPC6_EML_CFG_MAX_OFFSET
#define TPC6_EML_CFG_SECTION
#define mmTPC6_EML_CS_BASE
#define TPC6_EML_CS_MAX_OFFSET
#define TPC6_EML_CS_SECTION
#define mmTPC7_EML_SPMU_BASE
#define TPC7_EML_SPMU_MAX_OFFSET
#define TPC7_EML_SPMU_SECTION
#define mmTPC7_EML_ETF_BASE
#define TPC7_EML_ETF_MAX_OFFSET
#define TPC7_EML_ETF_SECTION
#define mmTPC7_EML_STM_BASE
#define TPC7_EML_STM_MAX_OFFSET
#define TPC7_EML_STM_SECTION
#define mmTPC7_EML_ETM_R4_BASE
#define TPC7_EML_ETM_R4_MAX_OFFSET
#define TPC7_EML_ETM_R4_SECTION
#define mmTPC7_EML_CTI_BASE
#define TPC7_EML_CTI_MAX_OFFSET
#define TPC7_EML_CTI_SECTION
#define mmTPC7_EML_FUNNEL_BASE
#define TPC7_EML_FUNNEL_MAX_OFFSET
#define TPC7_EML_FUNNEL_SECTION
#define mmTPC7_EML_BUSMON_0_BASE
#define TPC7_EML_BUSMON_0_MAX_OFFSET
#define TPC7_EML_BUSMON_0_SECTION
#define mmTPC7_EML_BUSMON_1_BASE
#define TPC7_EML_BUSMON_1_MAX_OFFSET
#define TPC7_EML_BUSMON_1_SECTION
#define mmTPC7_EML_BUSMON_2_BASE
#define TPC7_EML_BUSMON_2_MAX_OFFSET
#define TPC7_EML_BUSMON_2_SECTION
#define mmTPC7_EML_BUSMON_3_BASE
#define TPC7_EML_BUSMON_3_MAX_OFFSET
#define TPC7_EML_BUSMON_3_SECTION
#define mmTPC7_EML_CFG_BASE
#define TPC7_EML_CFG_MAX_OFFSET
#define TPC7_EML_CFG_SECTION
#define mmTPC7_EML_CS_BASE
#define TPC7_EML_CS_MAX_OFFSET

#endif /* GOYA_BLOCKS_H_ */