/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2020-2024 Intel Corporation */ #ifndef __IVPU_DRV_H__ #define __IVPU_DRV_H__ #include <drm/drm_device.h> #include <drm/drm_drv.h> #include <drm/drm_managed.h> #include <drm/drm_mm.h> #include <drm/drm_print.h> #include <linux/pci.h> #include <linux/xarray.h> #include <uapi/drm/ivpu_accel.h> #include "ivpu_mmu_context.h" #include "ivpu_ipc.h" #define DRIVER_NAME … #define DRIVER_DESC … #define DRIVER_DATE … #define PCI_DEVICE_ID_MTL … #define PCI_DEVICE_ID_ARL … #define PCI_DEVICE_ID_LNL … #define IVPU_HW_IP_37XX … #define IVPU_HW_IP_40XX … #define IVPU_HW_IP_50XX … #define IVPU_HW_IP_60XX … #define IVPU_HW_IP_REV_LNL_B0 … #define IVPU_HW_BTRS_MTL … #define IVPU_HW_BTRS_LNL … #define IVPU_GLOBAL_CONTEXT_MMU_SSID … /* SSID 1 is used by the VPU to represent reserved context */ #define IVPU_RESERVED_CONTEXT_MMU_SSID … #define IVPU_USER_CONTEXT_MIN_SSID … #define IVPU_USER_CONTEXT_MAX_SSID … #define IVPU_MIN_DB … #define IVPU_MAX_DB … #define IVPU_NUM_ENGINES … #define IVPU_NUM_PRIORITIES … #define IVPU_NUM_CMDQS_PER_CTX … #define IVPU_CMDQ_INDEX(engine, priority) … #define IVPU_PLATFORM_SILICON … #define IVPU_PLATFORM_SIMICS … #define IVPU_PLATFORM_FPGA … #define IVPU_PLATFORM_INVALID … #define IVPU_DBG_REG … #define IVPU_DBG_IRQ … #define IVPU_DBG_MMU … #define IVPU_DBG_FILE … #define IVPU_DBG_MISC … #define IVPU_DBG_FW_BOOT … #define IVPU_DBG_PM … #define IVPU_DBG_IPC … #define IVPU_DBG_BO … #define IVPU_DBG_JOB … #define IVPU_DBG_JSM … #define IVPU_DBG_KREF … #define IVPU_DBG_RPM … #define IVPU_DBG_MMU_MAP … #define ivpu_err(vdev, fmt, ...) … #define ivpu_err_ratelimited(vdev, fmt, ...) … #define ivpu_warn(vdev, fmt, ...) … #define ivpu_warn_ratelimited(vdev, fmt, ...) … #define ivpu_info(vdev, fmt, ...) … #define ivpu_dbg(vdev, type, fmt, args...) … #define IVPU_WA(wa_name) … #define IVPU_PRINT_WA(wa_name) … struct ivpu_wa_table { … }; struct ivpu_hw_info; struct ivpu_mmu_info; struct ivpu_fw_info; struct ivpu_ipc_info; struct ivpu_pm_info; struct ivpu_device { … }; /* * file_priv has its own refcount (ref) that allows user space to close the fd * without blocking even if VPU is still processing some jobs. */ struct ivpu_file_priv { … }; extern int ivpu_dbg_mask; extern u8 ivpu_pll_min_ratio; extern u8 ivpu_pll_max_ratio; extern int ivpu_sched_mode; extern bool ivpu_disable_mmu_cont_pages; extern bool ivpu_force_snoop; #define IVPU_TEST_MODE_FW_TEST … #define IVPU_TEST_MODE_NULL_HW … #define IVPU_TEST_MODE_NULL_SUBMISSION … #define IVPU_TEST_MODE_D0I3_MSG_DISABLE … #define IVPU_TEST_MODE_D0I3_MSG_ENABLE … #define IVPU_TEST_MODE_PREEMPTION_DISABLE … #define IVPU_TEST_MODE_HWS_EXTRA_EVENTS … #define IVPU_TEST_MODE_DISABLE_TIMEOUTS … extern int ivpu_test_mode; struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv); void ivpu_file_priv_put(struct ivpu_file_priv **link); int ivpu_boot(struct ivpu_device *vdev); int ivpu_shutdown(struct ivpu_device *vdev); void ivpu_prepare_for_reset(struct ivpu_device *vdev); static inline u8 ivpu_revision(struct ivpu_device *vdev) { … } static inline u16 ivpu_device_id(struct ivpu_device *vdev) { … } static inline int ivpu_hw_ip_gen(struct ivpu_device *vdev) { … } static inline int ivpu_hw_btrs_gen(struct ivpu_device *vdev) { … } static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev) { … } static inline u32 ivpu_get_context_count(struct ivpu_device *vdev) { … } static inline u32 ivpu_get_platform(struct ivpu_device *vdev) { … } static inline bool ivpu_is_silicon(struct ivpu_device *vdev) { … } static inline bool ivpu_is_simics(struct ivpu_device *vdev) { … } static inline bool ivpu_is_fpga(struct ivpu_device *vdev) { … } static inline bool ivpu_is_force_snoop_enabled(struct ivpu_device *vdev) { … } #endif /* __IVPU_DRV_H__ */
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