/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2018 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_MMU_UP_REGS_H_ #define ASIC_REG_MMU_UP_REGS_H_ /* ***************************************** * MMU_UP (Prototype: MMU) ***************************************** */ #define mmMMU_UP_MMU_ENABLE … #define mmMMU_UP_FORCE_ORDERING … #define mmMMU_UP_FEATURE_ENABLE … #define mmMMU_UP_VA_ORDERING_MASK_31_7 … #define mmMMU_UP_VA_ORDERING_MASK_49_32 … #define mmMMU_UP_LOG2_DDR_SIZE … #define mmMMU_UP_SCRAMBLER … #define mmMMU_UP_MEM_INIT_BUSY … #define mmMMU_UP_SPI_MASK … #define mmMMU_UP_SPI_CAUSE … #define mmMMU_UP_PAGE_ERROR_CAPTURE … #define mmMMU_UP_PAGE_ERROR_CAPTURE_VA … #define mmMMU_UP_ACCESS_ERROR_CAPTURE … #define mmMMU_UP_ACCESS_ERROR_CAPTURE_VA … #define mmMMU_UP_SPI_INTERRUPT_CLR … #define mmMMU_UP_SPI_INTERRUPT_MASK … #define mmMMU_UP_DBG_MEM_WRAP_RM … #define mmMMU_UP_SPI_CAUSE_CLR … #define mmMMU_UP_SLICE_CREDIT … #define mmMMU_UP_PIPE_CREDIT … #define mmMMU_UP_RAZWI_WRITE_VLD … #define mmMMU_UP_RAZWI_WRITE_ID … #define mmMMU_UP_RAZWI_READ_VLD … #define mmMMU_UP_RAZWI_READ_ID … #define mmMMU_UP_MMU_BYPASS … #endif /* ASIC_REG_MMU_UP_REGS_H_ */
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