/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2018 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DMA0_QM_REGS_H_ #define ASIC_REG_DMA0_QM_REGS_H_ /* ***************************************** * DMA0_QM (Prototype: QMAN) ***************************************** */ #define mmDMA0_QM_GLBL_CFG0 … #define mmDMA0_QM_GLBL_CFG1 … #define mmDMA0_QM_GLBL_PROT … #define mmDMA0_QM_GLBL_ERR_CFG … #define mmDMA0_QM_GLBL_SECURE_PROPS_0 … #define mmDMA0_QM_GLBL_SECURE_PROPS_1 … #define mmDMA0_QM_GLBL_SECURE_PROPS_2 … #define mmDMA0_QM_GLBL_SECURE_PROPS_3 … #define mmDMA0_QM_GLBL_SECURE_PROPS_4 … #define mmDMA0_QM_GLBL_NON_SECURE_PROPS_0 … #define mmDMA0_QM_GLBL_NON_SECURE_PROPS_1 … #define mmDMA0_QM_GLBL_NON_SECURE_PROPS_2 … #define mmDMA0_QM_GLBL_NON_SECURE_PROPS_3 … #define mmDMA0_QM_GLBL_NON_SECURE_PROPS_4 … #define mmDMA0_QM_GLBL_STS0 … #define mmDMA0_QM_GLBL_STS1_0 … #define mmDMA0_QM_GLBL_STS1_1 … #define mmDMA0_QM_GLBL_STS1_2 … #define mmDMA0_QM_GLBL_STS1_3 … #define mmDMA0_QM_GLBL_STS1_4 … #define mmDMA0_QM_GLBL_MSG_EN_0 … #define mmDMA0_QM_GLBL_MSG_EN_1 … #define mmDMA0_QM_GLBL_MSG_EN_2 … #define mmDMA0_QM_GLBL_MSG_EN_3 … #define mmDMA0_QM_GLBL_MSG_EN_4 … #define mmDMA0_QM_PQ_BASE_LO_0 … #define mmDMA0_QM_PQ_BASE_LO_1 … #define mmDMA0_QM_PQ_BASE_LO_2 … #define mmDMA0_QM_PQ_BASE_LO_3 … #define mmDMA0_QM_PQ_BASE_HI_0 … #define mmDMA0_QM_PQ_BASE_HI_1 … #define mmDMA0_QM_PQ_BASE_HI_2 … #define mmDMA0_QM_PQ_BASE_HI_3 … #define mmDMA0_QM_PQ_SIZE_0 … #define mmDMA0_QM_PQ_SIZE_1 … #define mmDMA0_QM_PQ_SIZE_2 … #define mmDMA0_QM_PQ_SIZE_3 … #define mmDMA0_QM_PQ_PI_0 … #define mmDMA0_QM_PQ_PI_1 … #define mmDMA0_QM_PQ_PI_2 … #define mmDMA0_QM_PQ_PI_3 … #define mmDMA0_QM_PQ_CI_0 … #define mmDMA0_QM_PQ_CI_1 … #define mmDMA0_QM_PQ_CI_2 … #define mmDMA0_QM_PQ_CI_3 … #define mmDMA0_QM_PQ_CFG0_0 … #define mmDMA0_QM_PQ_CFG0_1 … #define mmDMA0_QM_PQ_CFG0_2 … #define mmDMA0_QM_PQ_CFG0_3 … #define mmDMA0_QM_PQ_CFG1_0 … #define mmDMA0_QM_PQ_CFG1_1 … #define mmDMA0_QM_PQ_CFG1_2 … #define mmDMA0_QM_PQ_CFG1_3 … #define mmDMA0_QM_PQ_ARUSER_31_11_0 … #define mmDMA0_QM_PQ_ARUSER_31_11_1 … #define mmDMA0_QM_PQ_ARUSER_31_11_2 … #define mmDMA0_QM_PQ_ARUSER_31_11_3 … #define mmDMA0_QM_PQ_STS0_0 … #define mmDMA0_QM_PQ_STS0_1 … #define mmDMA0_QM_PQ_STS0_2 … #define mmDMA0_QM_PQ_STS0_3 … #define mmDMA0_QM_PQ_STS1_0 … #define mmDMA0_QM_PQ_STS1_1 … #define mmDMA0_QM_PQ_STS1_2 … #define mmDMA0_QM_PQ_STS1_3 … #define mmDMA0_QM_CQ_CFG0_0 … #define mmDMA0_QM_CQ_CFG0_1 … #define mmDMA0_QM_CQ_CFG0_2 … #define mmDMA0_QM_CQ_CFG0_3 … #define mmDMA0_QM_CQ_CFG0_4 … #define mmDMA0_QM_CQ_CFG1_0 … #define mmDMA0_QM_CQ_CFG1_1 … #define mmDMA0_QM_CQ_CFG1_2 … #define mmDMA0_QM_CQ_CFG1_3 … #define mmDMA0_QM_CQ_CFG1_4 … #define mmDMA0_QM_CQ_ARUSER_31_11_0 … #define mmDMA0_QM_CQ_ARUSER_31_11_1 … #define mmDMA0_QM_CQ_ARUSER_31_11_2 … #define mmDMA0_QM_CQ_ARUSER_31_11_3 … #define mmDMA0_QM_CQ_ARUSER_31_11_4 … #define mmDMA0_QM_CQ_STS0_0 … #define mmDMA0_QM_CQ_STS0_1 … #define mmDMA0_QM_CQ_STS0_2 … #define mmDMA0_QM_CQ_STS0_3 … #define mmDMA0_QM_CQ_STS0_4 … #define mmDMA0_QM_CQ_STS1_0 … #define mmDMA0_QM_CQ_STS1_1 … #define mmDMA0_QM_CQ_STS1_2 … #define mmDMA0_QM_CQ_STS1_3 … #define mmDMA0_QM_CQ_STS1_4 … #define mmDMA0_QM_CQ_PTR_LO_0 … #define mmDMA0_QM_CQ_PTR_HI_0 … #define mmDMA0_QM_CQ_TSIZE_0 … #define mmDMA0_QM_CQ_CTL_0 … #define mmDMA0_QM_CQ_PTR_LO_1 … #define mmDMA0_QM_CQ_PTR_HI_1 … #define mmDMA0_QM_CQ_TSIZE_1 … #define mmDMA0_QM_CQ_CTL_1 … #define mmDMA0_QM_CQ_PTR_LO_2 … #define mmDMA0_QM_CQ_PTR_HI_2 … #define mmDMA0_QM_CQ_TSIZE_2 … #define mmDMA0_QM_CQ_CTL_2 … #define mmDMA0_QM_CQ_PTR_LO_3 … #define mmDMA0_QM_CQ_PTR_HI_3 … #define mmDMA0_QM_CQ_TSIZE_3 … #define mmDMA0_QM_CQ_CTL_3 … #define mmDMA0_QM_CQ_PTR_LO_4 … #define mmDMA0_QM_CQ_PTR_HI_4 … #define mmDMA0_QM_CQ_TSIZE_4 … #define mmDMA0_QM_CQ_CTL_4 … #define mmDMA0_QM_CQ_PTR_LO_STS_0 … #define mmDMA0_QM_CQ_PTR_LO_STS_1 … #define mmDMA0_QM_CQ_PTR_LO_STS_2 … #define mmDMA0_QM_CQ_PTR_LO_STS_3 … #define mmDMA0_QM_CQ_PTR_LO_STS_4 … #define mmDMA0_QM_CQ_PTR_HI_STS_0 … #define mmDMA0_QM_CQ_PTR_HI_STS_1 … #define mmDMA0_QM_CQ_PTR_HI_STS_2 … #define mmDMA0_QM_CQ_PTR_HI_STS_3 … #define mmDMA0_QM_CQ_PTR_HI_STS_4 … #define mmDMA0_QM_CQ_TSIZE_STS_0 … #define mmDMA0_QM_CQ_TSIZE_STS_1 … #define mmDMA0_QM_CQ_TSIZE_STS_2 … #define mmDMA0_QM_CQ_TSIZE_STS_3 … #define mmDMA0_QM_CQ_TSIZE_STS_4 … #define mmDMA0_QM_CQ_CTL_STS_0 … #define mmDMA0_QM_CQ_CTL_STS_1 … #define mmDMA0_QM_CQ_CTL_STS_2 … #define mmDMA0_QM_CQ_CTL_STS_3 … #define mmDMA0_QM_CQ_CTL_STS_4 … #define mmDMA0_QM_CQ_IFIFO_CNT_0 … #define mmDMA0_QM_CQ_IFIFO_CNT_1 … #define mmDMA0_QM_CQ_IFIFO_CNT_2 … #define mmDMA0_QM_CQ_IFIFO_CNT_3 … #define mmDMA0_QM_CQ_IFIFO_CNT_4 … #define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 … #define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_1 … #define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_2 … #define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_3 … #define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_4 … #define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 … #define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_1 … #define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_2 … #define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_3 … #define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_4 … #define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 … #define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_1 … #define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_2 … #define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_3 … #define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_4 … #define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 … #define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_1 … #define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_2 … #define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_3 … #define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_4 … #define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 … #define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_1 … #define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 … #define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_3 … #define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_4 … #define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 … #define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_1 … #define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_2 … #define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_3 … #define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_4 … #define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 … #define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_1 … #define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_2 … #define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_3 … #define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_4 … #define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 … #define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_1 … #define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_2 … #define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_3 … #define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_4 … #define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 … #define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_1 … #define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_2 … #define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_3 … #define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_4 … #define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 … #define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 … #define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 … #define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 … #define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 … #define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 … #define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 … #define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 … #define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 … #define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 … #define mmDMA0_QM_CP_FENCE0_RDATA_0 … #define mmDMA0_QM_CP_FENCE0_RDATA_1 … #define mmDMA0_QM_CP_FENCE0_RDATA_2 … #define mmDMA0_QM_CP_FENCE0_RDATA_3 … #define mmDMA0_QM_CP_FENCE0_RDATA_4 … #define mmDMA0_QM_CP_FENCE1_RDATA_0 … #define mmDMA0_QM_CP_FENCE1_RDATA_1 … #define mmDMA0_QM_CP_FENCE1_RDATA_2 … #define mmDMA0_QM_CP_FENCE1_RDATA_3 … #define mmDMA0_QM_CP_FENCE1_RDATA_4 … #define mmDMA0_QM_CP_FENCE2_RDATA_0 … #define mmDMA0_QM_CP_FENCE2_RDATA_1 … #define mmDMA0_QM_CP_FENCE2_RDATA_2 … #define mmDMA0_QM_CP_FENCE2_RDATA_3 … #define mmDMA0_QM_CP_FENCE2_RDATA_4 … #define mmDMA0_QM_CP_FENCE3_RDATA_0 … #define mmDMA0_QM_CP_FENCE3_RDATA_1 … #define mmDMA0_QM_CP_FENCE3_RDATA_2 … #define mmDMA0_QM_CP_FENCE3_RDATA_3 … #define mmDMA0_QM_CP_FENCE3_RDATA_4 … #define mmDMA0_QM_CP_FENCE0_CNT_0 … #define mmDMA0_QM_CP_FENCE0_CNT_1 … #define mmDMA0_QM_CP_FENCE0_CNT_2 … #define mmDMA0_QM_CP_FENCE0_CNT_3 … #define mmDMA0_QM_CP_FENCE0_CNT_4 … #define mmDMA0_QM_CP_FENCE1_CNT_0 … #define mmDMA0_QM_CP_FENCE1_CNT_1 … #define mmDMA0_QM_CP_FENCE1_CNT_2 … #define mmDMA0_QM_CP_FENCE1_CNT_3 … #define mmDMA0_QM_CP_FENCE1_CNT_4 … #define mmDMA0_QM_CP_FENCE2_CNT_0 … #define mmDMA0_QM_CP_FENCE2_CNT_1 … #define mmDMA0_QM_CP_FENCE2_CNT_2 … #define mmDMA0_QM_CP_FENCE2_CNT_3 … #define mmDMA0_QM_CP_FENCE2_CNT_4 … #define mmDMA0_QM_CP_FENCE3_CNT_0 … #define mmDMA0_QM_CP_FENCE3_CNT_1 … #define mmDMA0_QM_CP_FENCE3_CNT_2 … #define mmDMA0_QM_CP_FENCE3_CNT_3 … #define mmDMA0_QM_CP_FENCE3_CNT_4 … #define mmDMA0_QM_CP_STS_0 … #define mmDMA0_QM_CP_STS_1 … #define mmDMA0_QM_CP_STS_2 … #define mmDMA0_QM_CP_STS_3 … #define mmDMA0_QM_CP_STS_4 … #define mmDMA0_QM_CP_CURRENT_INST_LO_0 … #define mmDMA0_QM_CP_CURRENT_INST_LO_1 … #define mmDMA0_QM_CP_CURRENT_INST_LO_2 … #define mmDMA0_QM_CP_CURRENT_INST_LO_3 … #define mmDMA0_QM_CP_CURRENT_INST_LO_4 … #define mmDMA0_QM_CP_CURRENT_INST_HI_0 … #define mmDMA0_QM_CP_CURRENT_INST_HI_1 … #define mmDMA0_QM_CP_CURRENT_INST_HI_2 … #define mmDMA0_QM_CP_CURRENT_INST_HI_3 … #define mmDMA0_QM_CP_CURRENT_INST_HI_4 … #define mmDMA0_QM_CP_BARRIER_CFG_0 … #define mmDMA0_QM_CP_BARRIER_CFG_1 … #define mmDMA0_QM_CP_BARRIER_CFG_2 … #define mmDMA0_QM_CP_BARRIER_CFG_3 … #define mmDMA0_QM_CP_BARRIER_CFG_4 … #define mmDMA0_QM_CP_DBG_0_0 … #define mmDMA0_QM_CP_DBG_0_1 … #define mmDMA0_QM_CP_DBG_0_2 … #define mmDMA0_QM_CP_DBG_0_3 … #define mmDMA0_QM_CP_DBG_0_4 … #define mmDMA0_QM_CP_ARUSER_31_11_0 … #define mmDMA0_QM_CP_ARUSER_31_11_1 … #define mmDMA0_QM_CP_ARUSER_31_11_2 … #define mmDMA0_QM_CP_ARUSER_31_11_3 … #define mmDMA0_QM_CP_ARUSER_31_11_4 … #define mmDMA0_QM_CP_AWUSER_31_11_0 … #define mmDMA0_QM_CP_AWUSER_31_11_1 … #define mmDMA0_QM_CP_AWUSER_31_11_2 … #define mmDMA0_QM_CP_AWUSER_31_11_3 … #define mmDMA0_QM_CP_AWUSER_31_11_4 … #define mmDMA0_QM_ARB_CFG_0 … #define mmDMA0_QM_ARB_CHOISE_Q_PUSH … #define mmDMA0_QM_ARB_WRR_WEIGHT_0 … #define mmDMA0_QM_ARB_WRR_WEIGHT_1 … #define mmDMA0_QM_ARB_WRR_WEIGHT_2 … #define mmDMA0_QM_ARB_WRR_WEIGHT_3 … #define mmDMA0_QM_ARB_CFG_1 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_0 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_1 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_2 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_3 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_4 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_5 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_6 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_7 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_8 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_9 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_10 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_11 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_12 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_13 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_14 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_15 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_16 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_17 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_18 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_19 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_20 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_21 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_22 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_23 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_24 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_25 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_26 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_27 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_28 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_29 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_30 … #define mmDMA0_QM_ARB_MST_AVAIL_CRED_31 … #define mmDMA0_QM_ARB_MST_CRED_INC … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_0 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_1 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_2 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_3 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_4 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_5 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_6 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_7 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_8 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_9 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_10 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_11 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_12 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_13 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_14 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_15 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_16 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_17 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_18 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_19 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_20 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_21 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_22 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_23 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_24 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_25 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_26 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_27 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_28 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_29 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_30 … #define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_31 … #define mmDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST … #define mmDMA0_QM_ARB_MST_SLAVE_EN … #define mmDMA0_QM_ARB_MST_QUIET_PER … #define mmDMA0_QM_ARB_SLV_CHOISE_WDT … #define mmDMA0_QM_ARB_SLV_ID … #define mmDMA0_QM_ARB_MSG_MAX_INFLIGHT … #define mmDMA0_QM_ARB_MSG_AWUSER_31_11 … #define mmDMA0_QM_ARB_MSG_AWUSER_SEC_PROP … #define mmDMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP … #define mmDMA0_QM_ARB_BASE_LO … #define mmDMA0_QM_ARB_BASE_HI … #define mmDMA0_QM_ARB_STATE_STS … #define mmDMA0_QM_ARB_CHOISE_FULLNESS_STS … #define mmDMA0_QM_ARB_MSG_STS … #define mmDMA0_QM_ARB_SLV_CHOISE_Q_HEAD … #define mmDMA0_QM_ARB_ERR_CAUSE … #define mmDMA0_QM_ARB_ERR_MSG_EN … #define mmDMA0_QM_ARB_ERR_STS_DRP … #define mmDMA0_QM_ARB_MST_CRED_STS_0 … #define mmDMA0_QM_ARB_MST_CRED_STS_1 … #define mmDMA0_QM_ARB_MST_CRED_STS_2 … #define mmDMA0_QM_ARB_MST_CRED_STS_3 … #define mmDMA0_QM_ARB_MST_CRED_STS_4 … #define mmDMA0_QM_ARB_MST_CRED_STS_5 … #define mmDMA0_QM_ARB_MST_CRED_STS_6 … #define mmDMA0_QM_ARB_MST_CRED_STS_7 … #define mmDMA0_QM_ARB_MST_CRED_STS_8 … #define mmDMA0_QM_ARB_MST_CRED_STS_9 … #define mmDMA0_QM_ARB_MST_CRED_STS_10 … #define mmDMA0_QM_ARB_MST_CRED_STS_11 … #define mmDMA0_QM_ARB_MST_CRED_STS_12 … #define mmDMA0_QM_ARB_MST_CRED_STS_13 … #define mmDMA0_QM_ARB_MST_CRED_STS_14 … #define mmDMA0_QM_ARB_MST_CRED_STS_15 … #define mmDMA0_QM_ARB_MST_CRED_STS_16 … #define mmDMA0_QM_ARB_MST_CRED_STS_17 … #define mmDMA0_QM_ARB_MST_CRED_STS_18 … #define mmDMA0_QM_ARB_MST_CRED_STS_19 … #define mmDMA0_QM_ARB_MST_CRED_STS_20 … #define mmDMA0_QM_ARB_MST_CRED_STS_21 … #define mmDMA0_QM_ARB_MST_CRED_STS_22 … #define mmDMA0_QM_ARB_MST_CRED_STS_23 … #define mmDMA0_QM_ARB_MST_CRED_STS_24 … #define mmDMA0_QM_ARB_MST_CRED_STS_25 … #define mmDMA0_QM_ARB_MST_CRED_STS_26 … #define mmDMA0_QM_ARB_MST_CRED_STS_27 … #define mmDMA0_QM_ARB_MST_CRED_STS_28 … #define mmDMA0_QM_ARB_MST_CRED_STS_29 … #define mmDMA0_QM_ARB_MST_CRED_STS_30 … #define mmDMA0_QM_ARB_MST_CRED_STS_31 … #define mmDMA0_QM_CGM_CFG … #define mmDMA0_QM_CGM_STS … #define mmDMA0_QM_CGM_CFG1 … #define mmDMA0_QM_LOCAL_RANGE_BASE … #define mmDMA0_QM_LOCAL_RANGE_SIZE … #define mmDMA0_QM_CSMR_STRICT_PRIO_CFG … #define mmDMA0_QM_HBW_RD_RATE_LIM_CFG_1 … #define mmDMA0_QM_LBW_WR_RATE_LIM_CFG_0 … #define mmDMA0_QM_LBW_WR_RATE_LIM_CFG_1 … #define mmDMA0_QM_HBW_RD_RATE_LIM_CFG_0 … #define mmDMA0_QM_GLBL_AXCACHE … #define mmDMA0_QM_IND_GW_APB_CFG … #define mmDMA0_QM_IND_GW_APB_WDATA … #define mmDMA0_QM_IND_GW_APB_RDATA … #define mmDMA0_QM_IND_GW_APB_STATUS … #define mmDMA0_QM_GLBL_ERR_ADDR_LO … #define mmDMA0_QM_GLBL_ERR_ADDR_HI … #define mmDMA0_QM_GLBL_ERR_WDATA … #define mmDMA0_QM_GLBL_MEM_INIT_BUSY … #endif /* ASIC_REG_DMA0_QM_REGS_H_ */
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