/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2018 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DMA0_CORE_REGS_H_ #define ASIC_REG_DMA0_CORE_REGS_H_ /* ***************************************** * DMA0_CORE (Prototype: DMA_CORE) ***************************************** */ #define mmDMA0_CORE_CFG_0 … #define mmDMA0_CORE_CFG_1 … #define mmDMA0_CORE_LBW_MAX_OUTSTAND … #define mmDMA0_CORE_SRC_BASE_LO … #define mmDMA0_CORE_SRC_BASE_HI … #define mmDMA0_CORE_DST_BASE_LO … #define mmDMA0_CORE_DST_BASE_HI … #define mmDMA0_CORE_SRC_TSIZE_1 … #define mmDMA0_CORE_SRC_STRIDE_1 … #define mmDMA0_CORE_SRC_TSIZE_2 … #define mmDMA0_CORE_SRC_STRIDE_2 … #define mmDMA0_CORE_SRC_TSIZE_3 … #define mmDMA0_CORE_SRC_STRIDE_3 … #define mmDMA0_CORE_SRC_TSIZE_4 … #define mmDMA0_CORE_SRC_STRIDE_4 … #define mmDMA0_CORE_SRC_TSIZE_0 … #define mmDMA0_CORE_DST_TSIZE_1 … #define mmDMA0_CORE_DST_STRIDE_1 … #define mmDMA0_CORE_DST_TSIZE_2 … #define mmDMA0_CORE_DST_STRIDE_2 … #define mmDMA0_CORE_DST_TSIZE_3 … #define mmDMA0_CORE_DST_STRIDE_3 … #define mmDMA0_CORE_DST_TSIZE_4 … #define mmDMA0_CORE_DST_STRIDE_4 … #define mmDMA0_CORE_DST_TSIZE_0 … #define mmDMA0_CORE_COMMIT … #define mmDMA0_CORE_WR_COMP_WDATA … #define mmDMA0_CORE_WR_COMP_ADDR_LO … #define mmDMA0_CORE_WR_COMP_ADDR_HI … #define mmDMA0_CORE_WR_COMP_AWUSER_31_11 … #define mmDMA0_CORE_TE_NUMROWS … #define mmDMA0_CORE_PROT … #define mmDMA0_CORE_SECURE_PROPS … #define mmDMA0_CORE_NON_SECURE_PROPS … #define mmDMA0_CORE_RD_MAX_OUTSTAND … #define mmDMA0_CORE_RD_MAX_SIZE … #define mmDMA0_CORE_RD_ARCACHE … #define mmDMA0_CORE_RD_ARUSER_31_11 … #define mmDMA0_CORE_RD_INFLIGHTS … #define mmDMA0_CORE_WR_MAX_OUTSTAND … #define mmDMA0_CORE_WR_MAX_AWID … #define mmDMA0_CORE_WR_AWCACHE … #define mmDMA0_CORE_WR_AWUSER_31_11 … #define mmDMA0_CORE_WR_INFLIGHTS … #define mmDMA0_CORE_RD_RATE_LIM_CFG_0 … #define mmDMA0_CORE_RD_RATE_LIM_CFG_1 … #define mmDMA0_CORE_WR_RATE_LIM_CFG_0 … #define mmDMA0_CORE_WR_RATE_LIM_CFG_1 … #define mmDMA0_CORE_ERR_CFG … #define mmDMA0_CORE_ERR_CAUSE … #define mmDMA0_CORE_ERRMSG_ADDR_LO … #define mmDMA0_CORE_ERRMSG_ADDR_HI … #define mmDMA0_CORE_ERRMSG_WDATA … #define mmDMA0_CORE_STS0 … #define mmDMA0_CORE_STS1 … #define mmDMA0_CORE_RD_DBGMEM_ADD … #define mmDMA0_CORE_RD_DBGMEM_DATA_WR … #define mmDMA0_CORE_RD_DBGMEM_DATA_RD … #define mmDMA0_CORE_RD_DBGMEM_CTRL … #define mmDMA0_CORE_RD_DBGMEM_RC … #define mmDMA0_CORE_DBG_HBW_AXI_AR_CNT … #define mmDMA0_CORE_DBG_HBW_AXI_AW_CNT … #define mmDMA0_CORE_DBG_LBW_AXI_AW_CNT … #define mmDMA0_CORE_DBG_DESC_CNT … #define mmDMA0_CORE_DBG_STS … #define mmDMA0_CORE_DBG_RD_DESC_ID … #define mmDMA0_CORE_DBG_WR_DESC_ID … #endif /* ASIC_REG_DMA0_CORE_REGS_H_ */
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