#ifndef ASIC_REG_MMU_REGS_H_
#define ASIC_REG_MMU_REGS_H_
#define mmMMU_INPUT_FIFO_THRESHOLD …
#define mmMMU_MMU_ENABLE …
#define mmMMU_FORCE_ORDERING …
#define mmMMU_FEATURE_ENABLE …
#define mmMMU_VA_ORDERING_MASK_31_7 …
#define mmMMU_VA_ORDERING_MASK_49_32 …
#define mmMMU_LOG2_DDR_SIZE …
#define mmMMU_SCRAMBLER …
#define mmMMU_MEM_INIT_BUSY …
#define mmMMU_SPI_MASK …
#define mmMMU_SPI_CAUSE …
#define mmMMU_PAGE_ERROR_CAPTURE …
#define mmMMU_PAGE_ERROR_CAPTURE_VA …
#define mmMMU_ACCESS_ERROR_CAPTURE …
#define mmMMU_ACCESS_ERROR_CAPTURE_VA …
#endif