#ifndef ASIC_REG_PSOC_SPI_REGS_H_
#define ASIC_REG_PSOC_SPI_REGS_H_
#define mmPSOC_SPI_CTRLR0 …
#define mmPSOC_SPI_CTRLR1 …
#define mmPSOC_SPI_SSIENR …
#define mmPSOC_SPI_MWCR …
#define mmPSOC_SPI_SER …
#define mmPSOC_SPI_BAUDR …
#define mmPSOC_SPI_TXFTLR …
#define mmPSOC_SPI_RXFTLR …
#define mmPSOC_SPI_TXFLR …
#define mmPSOC_SPI_RXFLR …
#define mmPSOC_SPI_SR …
#define mmPSOC_SPI_IMR …
#define mmPSOC_SPI_ISR …
#define mmPSOC_SPI_RISR …
#define mmPSOC_SPI_TXOICR …
#define mmPSOC_SPI_RXOICR …
#define mmPSOC_SPI_RXUICR …
#define mmPSOC_SPI_MSTICR …
#define mmPSOC_SPI_ICR …
#define mmPSOC_SPI_IDR …
#define mmPSOC_SPI_SSI_VERSION_ID …
#define mmPSOC_SPI_DR0 …
#define mmPSOC_SPI_DR1 …
#define mmPSOC_SPI_DR2 …
#define mmPSOC_SPI_DR3 …
#define mmPSOC_SPI_DR4 …
#define mmPSOC_SPI_DR5 …
#define mmPSOC_SPI_DR6 …
#define mmPSOC_SPI_DR7 …
#define mmPSOC_SPI_DR8 …
#define mmPSOC_SPI_DR9 …
#define mmPSOC_SPI_DR10 …
#define mmPSOC_SPI_DR11 …
#define mmPSOC_SPI_DR12 …
#define mmPSOC_SPI_DR13 …
#define mmPSOC_SPI_DR14 …
#define mmPSOC_SPI_DR15 …
#define mmPSOC_SPI_DR16 …
#define mmPSOC_SPI_DR17 …
#define mmPSOC_SPI_DR18 …
#define mmPSOC_SPI_DR19 …
#define mmPSOC_SPI_DR20 …
#define mmPSOC_SPI_DR21 …
#define mmPSOC_SPI_DR22 …
#define mmPSOC_SPI_DR23 …
#define mmPSOC_SPI_DR24 …
#define mmPSOC_SPI_DR25 …
#define mmPSOC_SPI_DR26 …
#define mmPSOC_SPI_DR27 …
#define mmPSOC_SPI_DR28 …
#define mmPSOC_SPI_DR29 …
#define mmPSOC_SPI_DR30 …
#define mmPSOC_SPI_DR31 …
#define mmPSOC_SPI_DR32 …
#define mmPSOC_SPI_DR33 …
#define mmPSOC_SPI_DR34 …
#define mmPSOC_SPI_DR35 …
#define mmPSOC_SPI_RX_SAMPLE_DLY …
#define mmPSOC_SPI_RSVD_1 …
#define mmPSOC_SPI_RSVD_2 …
#endif