/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2018 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_CPU_CA53_CFG_REGS_H_ #define ASIC_REG_CPU_CA53_CFG_REGS_H_ /* ***************************************** * CPU_CA53_CFG (Prototype: CA53_CFG) ***************************************** */ #define mmCPU_CA53_CFG_ARM_CFG … #define mmCPU_CA53_CFG_RST_ADDR_LSB_0 … #define mmCPU_CA53_CFG_RST_ADDR_LSB_1 … #define mmCPU_CA53_CFG_RST_ADDR_MSB_0 … #define mmCPU_CA53_CFG_RST_ADDR_MSB_1 … #define mmCPU_CA53_CFG_ARM_RST_CONTROL … #define mmCPU_CA53_CFG_ARM_AFFINITY … #define mmCPU_CA53_CFG_ARM_DISABLE … #define mmCPU_CA53_CFG_ARM_GIC_PERIPHBASE … #define mmCPU_CA53_CFG_ARM_GIC_IRQ_CFG … #define mmCPU_CA53_CFG_ARM_PWR_MNG … #define mmCPU_CA53_CFG_ARB_DBG_ROM_ADDR … #define mmCPU_CA53_CFG_ARM_DBG_MODES … #define mmCPU_CA53_CFG_ARM_PWR_STAT_0 … #define mmCPU_CA53_CFG_ARM_PWR_STAT_1 … #define mmCPU_CA53_CFG_ARM_DBG_STATUS … #define mmCPU_CA53_CFG_ARM_MEM_ATTR … #define mmCPU_CA53_CFG_ARM_PMU_0 … #define mmCPU_CA53_CFG_ARM_PMU_1 … #endif /* ASIC_REG_CPU_CA53_CFG_REGS_H_ */
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