/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2018 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_TPC4_CMDQ_REGS_H_ #define ASIC_REG_TPC4_CMDQ_REGS_H_ /* ***************************************** * TPC4_CMDQ (Prototype: CMDQ) ***************************************** */ #define mmTPC4_CMDQ_GLBL_CFG0 … #define mmTPC4_CMDQ_GLBL_CFG1 … #define mmTPC4_CMDQ_GLBL_PROT … #define mmTPC4_CMDQ_GLBL_ERR_CFG … #define mmTPC4_CMDQ_GLBL_ERR_ADDR_LO … #define mmTPC4_CMDQ_GLBL_ERR_ADDR_HI … #define mmTPC4_CMDQ_GLBL_ERR_WDATA … #define mmTPC4_CMDQ_GLBL_SECURE_PROPS … #define mmTPC4_CMDQ_GLBL_NON_SECURE_PROPS … #define mmTPC4_CMDQ_GLBL_STS0 … #define mmTPC4_CMDQ_GLBL_STS1 … #define mmTPC4_CMDQ_CQ_CFG0 … #define mmTPC4_CMDQ_CQ_CFG1 … #define mmTPC4_CMDQ_CQ_ARUSER … #define mmTPC4_CMDQ_CQ_PTR_LO … #define mmTPC4_CMDQ_CQ_PTR_HI … #define mmTPC4_CMDQ_CQ_TSIZE … #define mmTPC4_CMDQ_CQ_CTL … #define mmTPC4_CMDQ_CQ_PTR_LO_STS … #define mmTPC4_CMDQ_CQ_PTR_HI_STS … #define mmTPC4_CMDQ_CQ_TSIZE_STS … #define mmTPC4_CMDQ_CQ_CTL_STS … #define mmTPC4_CMDQ_CQ_STS0 … #define mmTPC4_CMDQ_CQ_STS1 … #define mmTPC4_CMDQ_CQ_RD_RATE_LIM_EN … #define mmTPC4_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN … #define mmTPC4_CMDQ_CQ_RD_RATE_LIM_SAT … #define mmTPC4_CMDQ_CQ_RD_RATE_LIM_TOUT … #define mmTPC4_CMDQ_CQ_IFIFO_CNT … #define mmTPC4_CMDQ_CP_MSG_BASE0_ADDR_LO … #define mmTPC4_CMDQ_CP_MSG_BASE0_ADDR_HI … #define mmTPC4_CMDQ_CP_MSG_BASE1_ADDR_LO … #define mmTPC4_CMDQ_CP_MSG_BASE1_ADDR_HI … #define mmTPC4_CMDQ_CP_MSG_BASE2_ADDR_LO … #define mmTPC4_CMDQ_CP_MSG_BASE2_ADDR_HI … #define mmTPC4_CMDQ_CP_MSG_BASE3_ADDR_LO … #define mmTPC4_CMDQ_CP_MSG_BASE3_ADDR_HI … #define mmTPC4_CMDQ_CP_LDMA_TSIZE_OFFSET … #define mmTPC4_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET … #define mmTPC4_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET … #define mmTPC4_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET … #define mmTPC4_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET … #define mmTPC4_CMDQ_CP_LDMA_COMMIT_OFFSET … #define mmTPC4_CMDQ_CP_FENCE0_RDATA … #define mmTPC4_CMDQ_CP_FENCE1_RDATA … #define mmTPC4_CMDQ_CP_FENCE2_RDATA … #define mmTPC4_CMDQ_CP_FENCE3_RDATA … #define mmTPC4_CMDQ_CP_FENCE0_CNT … #define mmTPC4_CMDQ_CP_FENCE1_CNT … #define mmTPC4_CMDQ_CP_FENCE2_CNT … #define mmTPC4_CMDQ_CP_FENCE3_CNT … #define mmTPC4_CMDQ_CP_STS … #define mmTPC4_CMDQ_CP_CURRENT_INST_LO … #define mmTPC4_CMDQ_CP_CURRENT_INST_HI … #define mmTPC4_CMDQ_CP_BARRIER_CFG … #define mmTPC4_CMDQ_CP_DBG_0 … #define mmTPC4_CMDQ_CQ_BUF_ADDR … #define mmTPC4_CMDQ_CQ_BUF_RDATA … #endif /* ASIC_REG_TPC4_CMDQ_REGS_H_ */
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