linux/drivers/accel/habanalabs/include/goya/asic_reg/tpc0_nrtr_regs.h

/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2018 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_TPC0_NRTR_REGS_H_
#define ASIC_REG_TPC0_NRTR_REGS_H_

/*
 *****************************************
 *   TPC0_NRTR (Prototype: IF_NRTR)
 *****************************************
 */

#define mmTPC0_NRTR_HBW_MAX_CRED

#define mmTPC0_NRTR_LBW_MAX_CRED

#define mmTPC0_NRTR_DBG_E_ARB

#define mmTPC0_NRTR_DBG_W_ARB

#define mmTPC0_NRTR_DBG_N_ARB

#define mmTPC0_NRTR_DBG_S_ARB

#define mmTPC0_NRTR_DBG_L_ARB

#define mmTPC0_NRTR_DBG_E_ARB_MAX

#define mmTPC0_NRTR_DBG_W_ARB_MAX

#define mmTPC0_NRTR_DBG_N_ARB_MAX

#define mmTPC0_NRTR_DBG_S_ARB_MAX

#define mmTPC0_NRTR_DBG_L_ARB_MAX

#define mmTPC0_NRTR_SPLIT_COEF_0

#define mmTPC0_NRTR_SPLIT_COEF_1

#define mmTPC0_NRTR_SPLIT_COEF_2

#define mmTPC0_NRTR_SPLIT_COEF_3

#define mmTPC0_NRTR_SPLIT_COEF_4

#define mmTPC0_NRTR_SPLIT_COEF_5

#define mmTPC0_NRTR_SPLIT_COEF_6

#define mmTPC0_NRTR_SPLIT_COEF_7

#define mmTPC0_NRTR_SPLIT_COEF_8

#define mmTPC0_NRTR_SPLIT_COEF_9

#define mmTPC0_NRTR_SPLIT_CFG

#define mmTPC0_NRTR_SPLIT_RD_SAT

#define mmTPC0_NRTR_SPLIT_RD_RST_TOKEN

#define mmTPC0_NRTR_SPLIT_RD_TIMEOUT_0

#define mmTPC0_NRTR_SPLIT_RD_TIMEOUT_1

#define mmTPC0_NRTR_SPLIT_WR_SAT

#define mmTPC0_NRTR_WPLIT_WR_TST_TOLEN

#define mmTPC0_NRTR_SPLIT_WR_TIMEOUT_0

#define mmTPC0_NRTR_SPLIT_WR_TIMEOUT_1

#define mmTPC0_NRTR_HBW_RANGE_HIT

#define mmTPC0_NRTR_HBW_RANGE_MASK_L_0

#define mmTPC0_NRTR_HBW_RANGE_MASK_L_1

#define mmTPC0_NRTR_HBW_RANGE_MASK_L_2

#define mmTPC0_NRTR_HBW_RANGE_MASK_L_3

#define mmTPC0_NRTR_HBW_RANGE_MASK_L_4

#define mmTPC0_NRTR_HBW_RANGE_MASK_L_5

#define mmTPC0_NRTR_HBW_RANGE_MASK_L_6

#define mmTPC0_NRTR_HBW_RANGE_MASK_L_7

#define mmTPC0_NRTR_HBW_RANGE_MASK_H_0

#define mmTPC0_NRTR_HBW_RANGE_MASK_H_1

#define mmTPC0_NRTR_HBW_RANGE_MASK_H_2

#define mmTPC0_NRTR_HBW_RANGE_MASK_H_3

#define mmTPC0_NRTR_HBW_RANGE_MASK_H_4

#define mmTPC0_NRTR_HBW_RANGE_MASK_H_5

#define mmTPC0_NRTR_HBW_RANGE_MASK_H_6

#define mmTPC0_NRTR_HBW_RANGE_MASK_H_7

#define mmTPC0_NRTR_HBW_RANGE_BASE_L_0

#define mmTPC0_NRTR_HBW_RANGE_BASE_L_1

#define mmTPC0_NRTR_HBW_RANGE_BASE_L_2

#define mmTPC0_NRTR_HBW_RANGE_BASE_L_3

#define mmTPC0_NRTR_HBW_RANGE_BASE_L_4

#define mmTPC0_NRTR_HBW_RANGE_BASE_L_5

#define mmTPC0_NRTR_HBW_RANGE_BASE_L_6

#define mmTPC0_NRTR_HBW_RANGE_BASE_L_7

#define mmTPC0_NRTR_HBW_RANGE_BASE_H_0

#define mmTPC0_NRTR_HBW_RANGE_BASE_H_1

#define mmTPC0_NRTR_HBW_RANGE_BASE_H_2

#define mmTPC0_NRTR_HBW_RANGE_BASE_H_3

#define mmTPC0_NRTR_HBW_RANGE_BASE_H_4

#define mmTPC0_NRTR_HBW_RANGE_BASE_H_5

#define mmTPC0_NRTR_HBW_RANGE_BASE_H_6

#define mmTPC0_NRTR_HBW_RANGE_BASE_H_7

#define mmTPC0_NRTR_LBW_RANGE_HIT

#define mmTPC0_NRTR_LBW_RANGE_MASK_0

#define mmTPC0_NRTR_LBW_RANGE_MASK_1

#define mmTPC0_NRTR_LBW_RANGE_MASK_2

#define mmTPC0_NRTR_LBW_RANGE_MASK_3

#define mmTPC0_NRTR_LBW_RANGE_MASK_4

#define mmTPC0_NRTR_LBW_RANGE_MASK_5

#define mmTPC0_NRTR_LBW_RANGE_MASK_6

#define mmTPC0_NRTR_LBW_RANGE_MASK_7

#define mmTPC0_NRTR_LBW_RANGE_MASK_8

#define mmTPC0_NRTR_LBW_RANGE_MASK_9

#define mmTPC0_NRTR_LBW_RANGE_MASK_10

#define mmTPC0_NRTR_LBW_RANGE_MASK_11

#define mmTPC0_NRTR_LBW_RANGE_MASK_12

#define mmTPC0_NRTR_LBW_RANGE_MASK_13

#define mmTPC0_NRTR_LBW_RANGE_MASK_14

#define mmTPC0_NRTR_LBW_RANGE_MASK_15

#define mmTPC0_NRTR_LBW_RANGE_BASE_0

#define mmTPC0_NRTR_LBW_RANGE_BASE_1

#define mmTPC0_NRTR_LBW_RANGE_BASE_2

#define mmTPC0_NRTR_LBW_RANGE_BASE_3

#define mmTPC0_NRTR_LBW_RANGE_BASE_4

#define mmTPC0_NRTR_LBW_RANGE_BASE_5

#define mmTPC0_NRTR_LBW_RANGE_BASE_6

#define mmTPC0_NRTR_LBW_RANGE_BASE_7

#define mmTPC0_NRTR_LBW_RANGE_BASE_8

#define mmTPC0_NRTR_LBW_RANGE_BASE_9

#define mmTPC0_NRTR_LBW_RANGE_BASE_10

#define mmTPC0_NRTR_LBW_RANGE_BASE_11

#define mmTPC0_NRTR_LBW_RANGE_BASE_12

#define mmTPC0_NRTR_LBW_RANGE_BASE_13

#define mmTPC0_NRTR_LBW_RANGE_BASE_14

#define mmTPC0_NRTR_LBW_RANGE_BASE_15

#define mmTPC0_NRTR_RGLTR

#define mmTPC0_NRTR_RGLTR_WR_RESULT

#define mmTPC0_NRTR_RGLTR_RD_RESULT

#define mmTPC0_NRTR_SCRAMB_EN

#define mmTPC0_NRTR_NON_LIN_SCRAMB

#endif /* ASIC_REG_TPC0_NRTR_REGS_H_ */