linux/drivers/accel/habanalabs/include/goya/asic_reg/psoc_global_conf_masks.h

/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2018 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_
#define ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_

/*
 *****************************************
 *   PSOC_GLOBAL_CONF (Prototype: GLOBAL_CONF)
 *****************************************
 */

/* PSOC_GLOBAL_CONF_NON_RST_FLOPS */
#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT
#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK

/* PSOC_GLOBAL_CONF_PCI_FW_FSM */
#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT
#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK

/* PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START */
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK

/* PSOC_GLOBAL_CONF_BTM_FSM */
#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT
#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK

/* PSOC_GLOBAL_CONF_SW_BTM_FSM */
#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT
#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK

/* PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM */
#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_SHIFT
#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_MASK

/* PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT */
#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_SHIFT
#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_MASK

/* PSOC_GLOBAL_CONF_SPI_MEM_EN */
#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SHIFT
#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_MASK

/* PSOC_GLOBAL_CONF_PRSTN */
#define PSOC_GLOBAL_CONF_PRSTN_VAL_SHIFT
#define PSOC_GLOBAL_CONF_PRSTN_VAL_MASK

/* PSOC_GLOBAL_CONF_PCIE_EN */
#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_SHIFT
#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_MASK

/* PSOC_GLOBAL_CONF_SPI_IMG_STS */
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_SHIFT
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_MASK
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_SHIFT
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_MASK
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_SHIFT
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_MASK
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_SHIFT
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_MASK

/* PSOC_GLOBAL_CONF_BOOT_SEQ_FSM */
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_SHIFT
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_MASK
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_SHIFT
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_MASK
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_SHIFT
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_MASK
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_SHIFT
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_MASK
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_SHIFT
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_MASK
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_SHIFT
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_MASK
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_SHIFT
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_MASK
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_SHIFT
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_MASK
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_SHIFT
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_MASK

/* PSOC_GLOBAL_CONF_SCRATCHPAD */
#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_SHIFT
#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_MASK

/* PSOC_GLOBAL_CONF_SEMAPHORE */
#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_SHIFT
#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_MASK

/* PSOC_GLOBAL_CONF_WARM_REBOOT */
#define PSOC_GLOBAL_CONF_WARM_REBOOT_CNTR_SHIFT
#define PSOC_GLOBAL_CONF_WARM_REBOOT_CNTR_MASK

/* PSOC_GLOBAL_CONF_UBOOT_MAGIC */
#define PSOC_GLOBAL_CONF_UBOOT_MAGIC_VAL_SHIFT
#define PSOC_GLOBAL_CONF_UBOOT_MAGIC_VAL_MASK

/* PSOC_GLOBAL_CONF_SPL_SOURCE */
#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_SHIFT
#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_MASK

/* PSOC_GLOBAL_CONF_I2C_MSTR1_DBG */
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_SHIFT
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_MASK
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_SHIFT
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_MASK
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_SHIFT
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_MASK
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_SHIFT
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_MASK
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_SHIFT
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_MASK
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_SHIFT
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_MASK
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_SHIFT
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_MASK
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_SHIFT
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_MASK
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_SHIFT
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_MASK
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_SHIFT
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_MASK
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_SHIFT
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_MASK
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_SHIFT
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_MASK
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_SHIFT
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_MASK

/* PSOC_GLOBAL_CONF_I2C_SLV */
#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_SHIFT
#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_MASK

/* PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK */
#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_FLD_INT_SHIFT
#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_FLD_INT_MASK

/* PSOC_GLOBAL_CONF_APP_STATUS */
#define PSOC_GLOBAL_CONF_APP_STATUS_IND_SHIFT
#define PSOC_GLOBAL_CONF_APP_STATUS_IND_MASK

/* PSOC_GLOBAL_CONF_BTL_STS */
#define PSOC_GLOBAL_CONF_BTL_STS_DONE_SHIFT
#define PSOC_GLOBAL_CONF_BTL_STS_DONE_MASK
#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_SHIFT
#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_MASK
#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_SHIFT
#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_MASK

/* PSOC_GLOBAL_CONF_TIMEOUT_INTR */
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_SHIFT
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_MASK
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_SHIFT
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_MASK
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_SHIFT
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_MASK
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_SHIFT
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_MASK
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_SHIFT
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_MASK
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_SHIFT
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_MASK
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_SHIFT
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_MASK
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_SHIFT
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_MASK

/* PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR */
#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_SHIFT
#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_MASK

/* PSOC_GLOBAL_CONF_PERIPH_INTR */
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_SHIFT
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_MASK
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_SHIFT
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_MASK
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_SHIFT
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_MASK
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_SHIFT
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_MASK
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_SHIFT
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_MASK
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_SHIFT
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_MASK
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_SHIFT
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_MASK
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_SHIFT
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_MASK
#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_SHIFT
#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_MASK
#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_SHIFT
#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_MASK
#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_SHIFT
#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_MASK

/* PSOC_GLOBAL_CONF_COMB_PERIPH_INTR */
#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_SHIFT
#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_MASK

/* PSOC_GLOBAL_CONF_AXI_ERR_INTR */
#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_SHIFT
#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_MASK

/* PSOC_GLOBAL_CONF_TARGETID */
#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_SHIFT
#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_MASK
#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_SHIFT
#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_MASK
#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_SHIFT
#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_MASK

/* PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE */
#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_SHIFT
#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_MASK

/* PSOC_GLOBAL_CONF_MII_ADDR */
#define PSOC_GLOBAL_CONF_MII_ADDR_VAL_SHIFT
#define PSOC_GLOBAL_CONF_MII_ADDR_VAL_MASK

/* PSOC_GLOBAL_CONF_MII_SPEED */
#define PSOC_GLOBAL_CONF_MII_SPEED_VAL_SHIFT
#define PSOC_GLOBAL_CONF_MII_SPEED_VAL_MASK

/* PSOC_GLOBAL_CONF_BOOT_STRAP_PINS */
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPOL_SHIFT
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPOL_MASK
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPHA_SHIFT
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPHA_MASK
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_EN_SHIFT
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_EN_MASK
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_ROM_EN_SHIFT
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_ROM_EN_MASK
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PCIE_EN_SHIFT
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PCIE_EN_MASK
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SLV_ADDR_SHIFT
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SLV_ADDR_MASK
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BOOT_STG2_SRC_SHIFT
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BOOT_STG2_SRC_MASK
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PLL_BPS_SHIFT
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PLL_BPS_MASK
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_SHIFT
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_MASK
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PLL_CFG_SHIFT
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PLL_CFG_MASK
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_MEM_REPAIR_BPS_SHIFT
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_MEM_REPAIR_BPS_MASK
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SPARE_SHIFT
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SPARE_MASK

/* PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL */
#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_SHIFT
#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_MASK
#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_CLR_SHIFT
#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_CLR_MASK

/* PSOC_GLOBAL_CONF_MEM_REPAIR_STS */
#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_SHIFT
#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_MASK

/* PSOC_GLOBAL_CONF_OUTSTANT_TRANS */
#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_SHIFT
#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_MASK
#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_SHIFT
#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_MASK

/* PSOC_GLOBAL_CONF_MASK_REQ */
#define PSOC_GLOBAL_CONF_MASK_REQ_IND_SHIFT
#define PSOC_GLOBAL_CONF_MASK_REQ_IND_MASK

/* PSOC_GLOBAL_CONF_PRSTN_RST_CFG */
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PCI_SHIFT
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PCI_MASK
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PCI_IF_SHIFT
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PCI_IF_MASK
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PLL_SHIFT
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PLL_MASK
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_TPC_SHIFT
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_TPC_MASK
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_MME_SHIFT
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_MME_MASK
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_MC_SHIFT
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_MC_MASK
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_CPU_SHIFT
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_CPU_MASK
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_IC_IF_SHIFT
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_IC_IF_MASK
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PSOC_SHIFT
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PSOC_MASK
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_SRAM_SHIFT
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_SRAM_MASK
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_DMA_SHIFT
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_DMA_MASK
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_DMA_IF_SHIFT
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_DMA_IF_MASK

/* PSOC_GLOBAL_CONF_SW_ALL_RST_CFG */
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PCI_SHIFT
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PCI_MASK
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PCI_IF_SHIFT
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PCI_IF_MASK
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PLL_SHIFT
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PLL_MASK
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_TPC_SHIFT
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_TPC_MASK
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MME_SHIFT
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MME_MASK
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MC_SHIFT
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MC_MASK
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_CPU_SHIFT
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_CPU_MASK
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_IC_IF_SHIFT
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_IC_IF_MASK
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PSOC_SHIFT
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PSOC_MASK
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_SRAM_SHIFT
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_SRAM_MASK
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_SHIFT
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_MASK
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_IF_SHIFT
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_IF_MASK

/* PSOC_GLOBAL_CONF_WD_RST_CFG */
#define PSOC_GLOBAL_CONF_WD_RST_CFG_PCI_SHIFT
#define PSOC_GLOBAL_CONF_WD_RST_CFG_PCI_MASK
#define PSOC_GLOBAL_CONF_WD_RST_CFG_PCI_IF_SHIFT
#define PSOC_GLOBAL_CONF_WD_RST_CFG_PCI_IF_MASK
#define PSOC_GLOBAL_CONF_WD_RST_CFG_PLL_SHIFT
#define PSOC_GLOBAL_CONF_WD_RST_CFG_PLL_MASK
#define PSOC_GLOBAL_CONF_WD_RST_CFG_TPC_SHIFT
#define PSOC_GLOBAL_CONF_WD_RST_CFG_TPC_MASK
#define PSOC_GLOBAL_CONF_WD_RST_CFG_MME_SHIFT
#define PSOC_GLOBAL_CONF_WD_RST_CFG_MME_MASK
#define PSOC_GLOBAL_CONF_WD_RST_CFG_MC_SHIFT
#define PSOC_GLOBAL_CONF_WD_RST_CFG_MC_MASK
#define PSOC_GLOBAL_CONF_WD_RST_CFG_CPU_SHIFT
#define PSOC_GLOBAL_CONF_WD_RST_CFG_CPU_MASK
#define PSOC_GLOBAL_CONF_WD_RST_CFG_IC_IF_SHIFT
#define PSOC_GLOBAL_CONF_WD_RST_CFG_IC_IF_MASK
#define PSOC_GLOBAL_CONF_WD_RST_CFG_PSOC_SHIFT
#define PSOC_GLOBAL_CONF_WD_RST_CFG_PSOC_MASK
#define PSOC_GLOBAL_CONF_WD_RST_CFG_SRAM_SHIFT
#define PSOC_GLOBAL_CONF_WD_RST_CFG_SRAM_MASK
#define PSOC_GLOBAL_CONF_WD_RST_CFG_DMA_SHIFT
#define PSOC_GLOBAL_CONF_WD_RST_CFG_DMA_MASK
#define PSOC_GLOBAL_CONF_WD_RST_CFG_DMA_IF_SHIFT
#define PSOC_GLOBAL_CONF_WD_RST_CFG_DMA_IF_MASK

/* PSOC_GLOBAL_CONF_MNL_RST_CFG */
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_PCI_SHIFT
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_PCI_MASK
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_PCI_IF_SHIFT
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_PCI_IF_MASK
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_PLL_SHIFT
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_PLL_MASK
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_TPC_SHIFT
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_TPC_MASK
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_MME_SHIFT
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_MME_MASK
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_MC_SHIFT
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_MC_MASK
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_CPU_SHIFT
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_CPU_MASK
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_IC_IF_SHIFT
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_IC_IF_MASK
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_PSOC_SHIFT
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_PSOC_MASK
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_SRAM_SHIFT
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_SRAM_MASK
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_DMA_SHIFT
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_DMA_MASK
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_DMA_IF_SHIFT
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_DMA_IF_MASK

/* PSOC_GLOBAL_CONF_UNIT_RST_N */
#define PSOC_GLOBAL_CONF_UNIT_RST_N_PCI_SHIFT
#define PSOC_GLOBAL_CONF_UNIT_RST_N_PCI_MASK
#define PSOC_GLOBAL_CONF_UNIT_RST_N_PCI_IF_SHIFT
#define PSOC_GLOBAL_CONF_UNIT_RST_N_PCI_IF_MASK
#define PSOC_GLOBAL_CONF_UNIT_RST_N_PLL_SHIFT
#define PSOC_GLOBAL_CONF_UNIT_RST_N_PLL_MASK
#define PSOC_GLOBAL_CONF_UNIT_RST_N_TPC_SHIFT
#define PSOC_GLOBAL_CONF_UNIT_RST_N_TPC_MASK
#define PSOC_GLOBAL_CONF_UNIT_RST_N_MME_SHIFT
#define PSOC_GLOBAL_CONF_UNIT_RST_N_MME_MASK
#define PSOC_GLOBAL_CONF_UNIT_RST_N_MC_SHIFT
#define PSOC_GLOBAL_CONF_UNIT_RST_N_MC_MASK
#define PSOC_GLOBAL_CONF_UNIT_RST_N_CPU_SHIFT
#define PSOC_GLOBAL_CONF_UNIT_RST_N_CPU_MASK
#define PSOC_GLOBAL_CONF_UNIT_RST_N_IC_IF_SHIFT
#define PSOC_GLOBAL_CONF_UNIT_RST_N_IC_IF_MASK
#define PSOC_GLOBAL_CONF_UNIT_RST_N_PSOC_SHIFT
#define PSOC_GLOBAL_CONF_UNIT_RST_N_PSOC_MASK
#define PSOC_GLOBAL_CONF_UNIT_RST_N_SRAM_SHIFT
#define PSOC_GLOBAL_CONF_UNIT_RST_N_SRAM_MASK
#define PSOC_GLOBAL_CONF_UNIT_RST_N_DMA_SHIFT
#define PSOC_GLOBAL_CONF_UNIT_RST_N_DMA_MASK
#define PSOC_GLOBAL_CONF_UNIT_RST_N_DMA_IF_SHIFT
#define PSOC_GLOBAL_CONF_UNIT_RST_N_DMA_IF_MASK

/* PSOC_GLOBAL_CONF_PRSTN_MASK */
#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_SHIFT
#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_MASK

/* PSOC_GLOBAL_CONF_WD_MASK */
#define PSOC_GLOBAL_CONF_WD_MASK_IND_SHIFT
#define PSOC_GLOBAL_CONF_WD_MASK_IND_MASK

/* PSOC_GLOBAL_CONF_RST_SRC */
#define PSOC_GLOBAL_CONF_RST_SRC_VAL_SHIFT
#define PSOC_GLOBAL_CONF_RST_SRC_VAL_MASK

/* PSOC_GLOBAL_CONF_PAD_1V8_CFG */
#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_SHIFT
#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_MASK

/* PSOC_GLOBAL_CONF_PAD_3V3_CFG */
#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_SHIFT
#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_MASK

/* PSOC_GLOBAL_CONF_PAD_1V8_INPUT */
#define PSOC_GLOBAL_CONF_PAD_1V8_INPUT_CFG_SHIFT
#define PSOC_GLOBAL_CONF_PAD_1V8_INPUT_CFG_MASK

/* PSOC_GLOBAL_CONF_BNK3V3_MS */
#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_SHIFT
#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_MASK

/* PSOC_GLOBAL_CONF_PAD_DEFAULT */
#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_SHIFT
#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_MASK

/* PSOC_GLOBAL_CONF_PAD_SEL */
#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_SHIFT
#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_MASK

#endif /* ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ */