/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2018 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_TPC0_CMDQ_MASKS_H_ #define ASIC_REG_TPC0_CMDQ_MASKS_H_ /* ***************************************** * TPC0_CMDQ (Prototype: CMDQ) ***************************************** */ /* TPC0_CMDQ_GLBL_CFG0 */ #define TPC0_CMDQ_GLBL_CFG0_PQF_EN_SHIFT … #define TPC0_CMDQ_GLBL_CFG0_PQF_EN_MASK … #define TPC0_CMDQ_GLBL_CFG0_CQF_EN_SHIFT … #define TPC0_CMDQ_GLBL_CFG0_CQF_EN_MASK … #define TPC0_CMDQ_GLBL_CFG0_CP_EN_SHIFT … #define TPC0_CMDQ_GLBL_CFG0_CP_EN_MASK … #define TPC0_CMDQ_GLBL_CFG0_DMA_EN_SHIFT … #define TPC0_CMDQ_GLBL_CFG0_DMA_EN_MASK … /* TPC0_CMDQ_GLBL_CFG1 */ #define TPC0_CMDQ_GLBL_CFG1_PQF_STOP_SHIFT … #define TPC0_CMDQ_GLBL_CFG1_PQF_STOP_MASK … #define TPC0_CMDQ_GLBL_CFG1_CQF_STOP_SHIFT … #define TPC0_CMDQ_GLBL_CFG1_CQF_STOP_MASK … #define TPC0_CMDQ_GLBL_CFG1_CP_STOP_SHIFT … #define TPC0_CMDQ_GLBL_CFG1_CP_STOP_MASK … #define TPC0_CMDQ_GLBL_CFG1_DMA_STOP_SHIFT … #define TPC0_CMDQ_GLBL_CFG1_DMA_STOP_MASK … #define TPC0_CMDQ_GLBL_CFG1_PQF_FLUSH_SHIFT … #define TPC0_CMDQ_GLBL_CFG1_PQF_FLUSH_MASK … #define TPC0_CMDQ_GLBL_CFG1_CQF_FLUSH_SHIFT … #define TPC0_CMDQ_GLBL_CFG1_CQF_FLUSH_MASK … #define TPC0_CMDQ_GLBL_CFG1_CP_FLUSH_SHIFT … #define TPC0_CMDQ_GLBL_CFG1_CP_FLUSH_MASK … #define TPC0_CMDQ_GLBL_CFG1_DMA_FLUSH_SHIFT … #define TPC0_CMDQ_GLBL_CFG1_DMA_FLUSH_MASK … /* TPC0_CMDQ_GLBL_PROT */ #define TPC0_CMDQ_GLBL_PROT_PQF_PROT_SHIFT … #define TPC0_CMDQ_GLBL_PROT_PQF_PROT_MASK … #define TPC0_CMDQ_GLBL_PROT_CQF_PROT_SHIFT … #define TPC0_CMDQ_GLBL_PROT_CQF_PROT_MASK … #define TPC0_CMDQ_GLBL_PROT_CP_PROT_SHIFT … #define TPC0_CMDQ_GLBL_PROT_CP_PROT_MASK … #define TPC0_CMDQ_GLBL_PROT_DMA_PROT_SHIFT … #define TPC0_CMDQ_GLBL_PROT_DMA_PROT_MASK … #define TPC0_CMDQ_GLBL_PROT_PQF_ERR_PROT_SHIFT … #define TPC0_CMDQ_GLBL_PROT_PQF_ERR_PROT_MASK … #define TPC0_CMDQ_GLBL_PROT_CQF_ERR_PROT_SHIFT … #define TPC0_CMDQ_GLBL_PROT_CQF_ERR_PROT_MASK … #define TPC0_CMDQ_GLBL_PROT_CP_ERR_PROT_SHIFT … #define TPC0_CMDQ_GLBL_PROT_CP_ERR_PROT_MASK … #define TPC0_CMDQ_GLBL_PROT_DMA_ERR_PROT_SHIFT … #define TPC0_CMDQ_GLBL_PROT_DMA_ERR_PROT_MASK … /* TPC0_CMDQ_GLBL_ERR_CFG */ #define TPC0_CMDQ_GLBL_ERR_CFG_PQF_ERR_INT_EN_SHIFT … #define TPC0_CMDQ_GLBL_ERR_CFG_PQF_ERR_INT_EN_MASK … #define TPC0_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT … #define TPC0_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK … #define TPC0_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT … #define TPC0_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK … #define TPC0_CMDQ_GLBL_ERR_CFG_CQF_ERR_INT_EN_SHIFT … #define TPC0_CMDQ_GLBL_ERR_CFG_CQF_ERR_INT_EN_MASK … #define TPC0_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT … #define TPC0_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK … #define TPC0_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT … #define TPC0_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK … #define TPC0_CMDQ_GLBL_ERR_CFG_CP_ERR_INT_EN_SHIFT … #define TPC0_CMDQ_GLBL_ERR_CFG_CP_ERR_INT_EN_MASK … #define TPC0_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT … #define TPC0_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK … #define TPC0_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT … #define TPC0_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK … #define TPC0_CMDQ_GLBL_ERR_CFG_DMA_ERR_INT_EN_SHIFT … #define TPC0_CMDQ_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK … #define TPC0_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT … #define TPC0_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_MASK … #define TPC0_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT … #define TPC0_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK … /* TPC0_CMDQ_GLBL_ERR_ADDR_LO */ #define TPC0_CMDQ_GLBL_ERR_ADDR_LO_VAL_SHIFT … #define TPC0_CMDQ_GLBL_ERR_ADDR_LO_VAL_MASK … /* TPC0_CMDQ_GLBL_ERR_ADDR_HI */ #define TPC0_CMDQ_GLBL_ERR_ADDR_HI_VAL_SHIFT … #define TPC0_CMDQ_GLBL_ERR_ADDR_HI_VAL_MASK … /* TPC0_CMDQ_GLBL_ERR_WDATA */ #define TPC0_CMDQ_GLBL_ERR_WDATA_VAL_SHIFT … #define TPC0_CMDQ_GLBL_ERR_WDATA_VAL_MASK … /* TPC0_CMDQ_GLBL_SECURE_PROPS */ #define TPC0_CMDQ_GLBL_SECURE_PROPS_ASID_SHIFT … #define TPC0_CMDQ_GLBL_SECURE_PROPS_ASID_MASK … #define TPC0_CMDQ_GLBL_SECURE_PROPS_MMBP_SHIFT … #define TPC0_CMDQ_GLBL_SECURE_PROPS_MMBP_MASK … /* TPC0_CMDQ_GLBL_NON_SECURE_PROPS */ #define TPC0_CMDQ_GLBL_NON_SECURE_PROPS_ASID_SHIFT … #define TPC0_CMDQ_GLBL_NON_SECURE_PROPS_ASID_MASK … #define TPC0_CMDQ_GLBL_NON_SECURE_PROPS_MMBP_SHIFT … #define TPC0_CMDQ_GLBL_NON_SECURE_PROPS_MMBP_MASK … /* TPC0_CMDQ_GLBL_STS0 */ #define TPC0_CMDQ_GLBL_STS0_PQF_IDLE_SHIFT … #define TPC0_CMDQ_GLBL_STS0_PQF_IDLE_MASK … #define TPC0_CMDQ_GLBL_STS0_CQF_IDLE_SHIFT … #define TPC0_CMDQ_GLBL_STS0_CQF_IDLE_MASK … #define TPC0_CMDQ_GLBL_STS0_CP_IDLE_SHIFT … #define TPC0_CMDQ_GLBL_STS0_CP_IDLE_MASK … #define TPC0_CMDQ_GLBL_STS0_DMA_IDLE_SHIFT … #define TPC0_CMDQ_GLBL_STS0_DMA_IDLE_MASK … #define TPC0_CMDQ_GLBL_STS0_PQF_IS_STOP_SHIFT … #define TPC0_CMDQ_GLBL_STS0_PQF_IS_STOP_MASK … #define TPC0_CMDQ_GLBL_STS0_CQF_IS_STOP_SHIFT … #define TPC0_CMDQ_GLBL_STS0_CQF_IS_STOP_MASK … #define TPC0_CMDQ_GLBL_STS0_CP_IS_STOP_SHIFT … #define TPC0_CMDQ_GLBL_STS0_CP_IS_STOP_MASK … #define TPC0_CMDQ_GLBL_STS0_DMA_IS_STOP_SHIFT … #define TPC0_CMDQ_GLBL_STS0_DMA_IS_STOP_MASK … /* TPC0_CMDQ_GLBL_STS1 */ #define TPC0_CMDQ_GLBL_STS1_PQF_RD_ERR_SHIFT … #define TPC0_CMDQ_GLBL_STS1_PQF_RD_ERR_MASK … #define TPC0_CMDQ_GLBL_STS1_CQF_RD_ERR_SHIFT … #define TPC0_CMDQ_GLBL_STS1_CQF_RD_ERR_MASK … #define TPC0_CMDQ_GLBL_STS1_CP_RD_ERR_SHIFT … #define TPC0_CMDQ_GLBL_STS1_CP_RD_ERR_MASK … #define TPC0_CMDQ_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT … #define TPC0_CMDQ_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK … #define TPC0_CMDQ_GLBL_STS1_CP_STOP_OP_SHIFT … #define TPC0_CMDQ_GLBL_STS1_CP_STOP_OP_MASK … #define TPC0_CMDQ_GLBL_STS1_CP_MSG_WR_ERR_SHIFT … #define TPC0_CMDQ_GLBL_STS1_CP_MSG_WR_ERR_MASK … #define TPC0_CMDQ_GLBL_STS1_DMA_RD_ERR_SHIFT … #define TPC0_CMDQ_GLBL_STS1_DMA_RD_ERR_MASK … #define TPC0_CMDQ_GLBL_STS1_DMA_WR_ERR_SHIFT … #define TPC0_CMDQ_GLBL_STS1_DMA_WR_ERR_MASK … #define TPC0_CMDQ_GLBL_STS1_DMA_RD_MSG_ERR_SHIFT … #define TPC0_CMDQ_GLBL_STS1_DMA_RD_MSG_ERR_MASK … #define TPC0_CMDQ_GLBL_STS1_DMA_WR_MSG_ERR_SHIFT … #define TPC0_CMDQ_GLBL_STS1_DMA_WR_MSG_ERR_MASK … /* TPC0_CMDQ_CQ_CFG0 */ #define TPC0_CMDQ_CQ_CFG0_RESERVED_SHIFT … #define TPC0_CMDQ_CQ_CFG0_RESERVED_MASK … /* TPC0_CMDQ_CQ_CFG1 */ #define TPC0_CMDQ_CQ_CFG1_CREDIT_LIM_SHIFT … #define TPC0_CMDQ_CQ_CFG1_CREDIT_LIM_MASK … #define TPC0_CMDQ_CQ_CFG1_MAX_INFLIGHT_SHIFT … #define TPC0_CMDQ_CQ_CFG1_MAX_INFLIGHT_MASK … /* TPC0_CMDQ_CQ_ARUSER */ #define TPC0_CMDQ_CQ_ARUSER_NOSNOOP_SHIFT … #define TPC0_CMDQ_CQ_ARUSER_NOSNOOP_MASK … #define TPC0_CMDQ_CQ_ARUSER_WORD_SHIFT … #define TPC0_CMDQ_CQ_ARUSER_WORD_MASK … /* TPC0_CMDQ_CQ_PTR_LO */ #define TPC0_CMDQ_CQ_PTR_LO_VAL_SHIFT … #define TPC0_CMDQ_CQ_PTR_LO_VAL_MASK … /* TPC0_CMDQ_CQ_PTR_HI */ #define TPC0_CMDQ_CQ_PTR_HI_VAL_SHIFT … #define TPC0_CMDQ_CQ_PTR_HI_VAL_MASK … /* TPC0_CMDQ_CQ_TSIZE */ #define TPC0_CMDQ_CQ_TSIZE_VAL_SHIFT … #define TPC0_CMDQ_CQ_TSIZE_VAL_MASK … /* TPC0_CMDQ_CQ_CTL */ #define TPC0_CMDQ_CQ_CTL_RPT_SHIFT … #define TPC0_CMDQ_CQ_CTL_RPT_MASK … #define TPC0_CMDQ_CQ_CTL_CTL_SHIFT … #define TPC0_CMDQ_CQ_CTL_CTL_MASK … /* TPC0_CMDQ_CQ_PTR_LO_STS */ #define TPC0_CMDQ_CQ_PTR_LO_STS_VAL_SHIFT … #define TPC0_CMDQ_CQ_PTR_LO_STS_VAL_MASK … /* TPC0_CMDQ_CQ_PTR_HI_STS */ #define TPC0_CMDQ_CQ_PTR_HI_STS_VAL_SHIFT … #define TPC0_CMDQ_CQ_PTR_HI_STS_VAL_MASK … /* TPC0_CMDQ_CQ_TSIZE_STS */ #define TPC0_CMDQ_CQ_TSIZE_STS_VAL_SHIFT … #define TPC0_CMDQ_CQ_TSIZE_STS_VAL_MASK … /* TPC0_CMDQ_CQ_CTL_STS */ #define TPC0_CMDQ_CQ_CTL_STS_RPT_SHIFT … #define TPC0_CMDQ_CQ_CTL_STS_RPT_MASK … #define TPC0_CMDQ_CQ_CTL_STS_CTL_SHIFT … #define TPC0_CMDQ_CQ_CTL_STS_CTL_MASK … /* TPC0_CMDQ_CQ_STS0 */ #define TPC0_CMDQ_CQ_STS0_CQ_CREDIT_CNT_SHIFT … #define TPC0_CMDQ_CQ_STS0_CQ_CREDIT_CNT_MASK … #define TPC0_CMDQ_CQ_STS0_CQ_FREE_CNT_SHIFT … #define TPC0_CMDQ_CQ_STS0_CQ_FREE_CNT_MASK … /* TPC0_CMDQ_CQ_STS1 */ #define TPC0_CMDQ_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT … #define TPC0_CMDQ_CQ_STS1_CQ_INFLIGHT_CNT_MASK … #define TPC0_CMDQ_CQ_STS1_CQ_BUF_EMPTY_SHIFT … #define TPC0_CMDQ_CQ_STS1_CQ_BUF_EMPTY_MASK … #define TPC0_CMDQ_CQ_STS1_CQ_BUSY_SHIFT … #define TPC0_CMDQ_CQ_STS1_CQ_BUSY_MASK … /* TPC0_CMDQ_CQ_RD_RATE_LIM_EN */ #define TPC0_CMDQ_CQ_RD_RATE_LIM_EN_VAL_SHIFT … #define TPC0_CMDQ_CQ_RD_RATE_LIM_EN_VAL_MASK … /* TPC0_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN */ #define TPC0_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT … #define TPC0_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK … /* TPC0_CMDQ_CQ_RD_RATE_LIM_SAT */ #define TPC0_CMDQ_CQ_RD_RATE_LIM_SAT_VAL_SHIFT … #define TPC0_CMDQ_CQ_RD_RATE_LIM_SAT_VAL_MASK … /* TPC0_CMDQ_CQ_RD_RATE_LIM_TOUT */ #define TPC0_CMDQ_CQ_RD_RATE_LIM_TOUT_VAL_SHIFT … #define TPC0_CMDQ_CQ_RD_RATE_LIM_TOUT_VAL_MASK … /* TPC0_CMDQ_CQ_IFIFO_CNT */ #define TPC0_CMDQ_CQ_IFIFO_CNT_VAL_SHIFT … #define TPC0_CMDQ_CQ_IFIFO_CNT_VAL_MASK … /* TPC0_CMDQ_CP_MSG_BASE0_ADDR_LO */ #define TPC0_CMDQ_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT … #define TPC0_CMDQ_CP_MSG_BASE0_ADDR_LO_VAL_MASK … /* TPC0_CMDQ_CP_MSG_BASE0_ADDR_HI */ #define TPC0_CMDQ_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT … #define TPC0_CMDQ_CP_MSG_BASE0_ADDR_HI_VAL_MASK … /* TPC0_CMDQ_CP_MSG_BASE1_ADDR_LO */ #define TPC0_CMDQ_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT … #define TPC0_CMDQ_CP_MSG_BASE1_ADDR_LO_VAL_MASK … /* TPC0_CMDQ_CP_MSG_BASE1_ADDR_HI */ #define TPC0_CMDQ_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT … #define TPC0_CMDQ_CP_MSG_BASE1_ADDR_HI_VAL_MASK … /* TPC0_CMDQ_CP_MSG_BASE2_ADDR_LO */ #define TPC0_CMDQ_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT … #define TPC0_CMDQ_CP_MSG_BASE2_ADDR_LO_VAL_MASK … /* TPC0_CMDQ_CP_MSG_BASE2_ADDR_HI */ #define TPC0_CMDQ_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT … #define TPC0_CMDQ_CP_MSG_BASE2_ADDR_HI_VAL_MASK … /* TPC0_CMDQ_CP_MSG_BASE3_ADDR_LO */ #define TPC0_CMDQ_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT … #define TPC0_CMDQ_CP_MSG_BASE3_ADDR_LO_VAL_MASK … /* TPC0_CMDQ_CP_MSG_BASE3_ADDR_HI */ #define TPC0_CMDQ_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT … #define TPC0_CMDQ_CP_MSG_BASE3_ADDR_HI_VAL_MASK … /* TPC0_CMDQ_CP_LDMA_TSIZE_OFFSET */ #define TPC0_CMDQ_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT … #define TPC0_CMDQ_CP_LDMA_TSIZE_OFFSET_VAL_MASK … /* TPC0_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET */ #define TPC0_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT … #define TPC0_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK … /* TPC0_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET */ #define TPC0_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_SHIFT … #define TPC0_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_MASK … /* TPC0_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET */ #define TPC0_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT … #define TPC0_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK … /* TPC0_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET */ #define TPC0_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET_VAL_SHIFT … #define TPC0_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET_VAL_MASK … /* TPC0_CMDQ_CP_LDMA_COMMIT_OFFSET */ #define TPC0_CMDQ_CP_LDMA_COMMIT_OFFSET_VAL_SHIFT … #define TPC0_CMDQ_CP_LDMA_COMMIT_OFFSET_VAL_MASK … /* TPC0_CMDQ_CP_FENCE0_RDATA */ #define TPC0_CMDQ_CP_FENCE0_RDATA_INC_VAL_SHIFT … #define TPC0_CMDQ_CP_FENCE0_RDATA_INC_VAL_MASK … /* TPC0_CMDQ_CP_FENCE1_RDATA */ #define TPC0_CMDQ_CP_FENCE1_RDATA_INC_VAL_SHIFT … #define TPC0_CMDQ_CP_FENCE1_RDATA_INC_VAL_MASK … /* TPC0_CMDQ_CP_FENCE2_RDATA */ #define TPC0_CMDQ_CP_FENCE2_RDATA_INC_VAL_SHIFT … #define TPC0_CMDQ_CP_FENCE2_RDATA_INC_VAL_MASK … /* TPC0_CMDQ_CP_FENCE3_RDATA */ #define TPC0_CMDQ_CP_FENCE3_RDATA_INC_VAL_SHIFT … #define TPC0_CMDQ_CP_FENCE3_RDATA_INC_VAL_MASK … /* TPC0_CMDQ_CP_FENCE0_CNT */ #define TPC0_CMDQ_CP_FENCE0_CNT_VAL_SHIFT … #define TPC0_CMDQ_CP_FENCE0_CNT_VAL_MASK … /* TPC0_CMDQ_CP_FENCE1_CNT */ #define TPC0_CMDQ_CP_FENCE1_CNT_VAL_SHIFT … #define TPC0_CMDQ_CP_FENCE1_CNT_VAL_MASK … /* TPC0_CMDQ_CP_FENCE2_CNT */ #define TPC0_CMDQ_CP_FENCE2_CNT_VAL_SHIFT … #define TPC0_CMDQ_CP_FENCE2_CNT_VAL_MASK … /* TPC0_CMDQ_CP_FENCE3_CNT */ #define TPC0_CMDQ_CP_FENCE3_CNT_VAL_SHIFT … #define TPC0_CMDQ_CP_FENCE3_CNT_VAL_MASK … /* TPC0_CMDQ_CP_STS */ #define TPC0_CMDQ_CP_STS_MSG_INFLIGHT_CNT_SHIFT … #define TPC0_CMDQ_CP_STS_MSG_INFLIGHT_CNT_MASK … #define TPC0_CMDQ_CP_STS_ERDY_SHIFT … #define TPC0_CMDQ_CP_STS_ERDY_MASK … #define TPC0_CMDQ_CP_STS_RRDY_SHIFT … #define TPC0_CMDQ_CP_STS_RRDY_MASK … #define TPC0_CMDQ_CP_STS_MRDY_SHIFT … #define TPC0_CMDQ_CP_STS_MRDY_MASK … #define TPC0_CMDQ_CP_STS_SW_STOP_SHIFT … #define TPC0_CMDQ_CP_STS_SW_STOP_MASK … #define TPC0_CMDQ_CP_STS_FENCE_ID_SHIFT … #define TPC0_CMDQ_CP_STS_FENCE_ID_MASK … #define TPC0_CMDQ_CP_STS_FENCE_IN_PROGRESS_SHIFT … #define TPC0_CMDQ_CP_STS_FENCE_IN_PROGRESS_MASK … /* TPC0_CMDQ_CP_CURRENT_INST_LO */ #define TPC0_CMDQ_CP_CURRENT_INST_LO_VAL_SHIFT … #define TPC0_CMDQ_CP_CURRENT_INST_LO_VAL_MASK … /* TPC0_CMDQ_CP_CURRENT_INST_HI */ #define TPC0_CMDQ_CP_CURRENT_INST_HI_VAL_SHIFT … #define TPC0_CMDQ_CP_CURRENT_INST_HI_VAL_MASK … /* TPC0_CMDQ_CP_BARRIER_CFG */ #define TPC0_CMDQ_CP_BARRIER_CFG_EBGUARD_SHIFT … #define TPC0_CMDQ_CP_BARRIER_CFG_EBGUARD_MASK … /* TPC0_CMDQ_CP_DBG_0 */ #define TPC0_CMDQ_CP_DBG_0_VAL_SHIFT … #define TPC0_CMDQ_CP_DBG_0_VAL_MASK … /* TPC0_CMDQ_CQ_BUF_ADDR */ #define TPC0_CMDQ_CQ_BUF_ADDR_VAL_SHIFT … #define TPC0_CMDQ_CQ_BUF_ADDR_VAL_MASK … /* TPC0_CMDQ_CQ_BUF_RDATA */ #define TPC0_CMDQ_CQ_BUF_RDATA_VAL_SHIFT … #define TPC0_CMDQ_CQ_BUF_RDATA_VAL_MASK … #endif /* ASIC_REG_TPC0_CMDQ_MASKS_H_ */
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