/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2018 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_CPU_CA53_CFG_MASKS_H_ #define ASIC_REG_CPU_CA53_CFG_MASKS_H_ /* ***************************************** * CPU_CA53_CFG (Prototype: CA53_CFG) ***************************************** */ /* CPU_CA53_CFG_ARM_CFG */ #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_SHIFT … #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_MASK … #define CPU_CA53_CFG_ARM_CFG_END_SHIFT … #define CPU_CA53_CFG_ARM_CFG_END_MASK … #define CPU_CA53_CFG_ARM_CFG_TE_SHIFT … #define CPU_CA53_CFG_ARM_CFG_TE_MASK … #define CPU_CA53_CFG_ARM_CFG_VINITHI_SHIFT … #define CPU_CA53_CFG_ARM_CFG_VINITHI_MASK … /* CPU_CA53_CFG_RST_ADDR_LSB */ #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_SHIFT … #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_MASK … /* CPU_CA53_CFG_RST_ADDR_MSB */ #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_SHIFT … #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_MASK … /* CPU_CA53_CFG_ARM_RST_CONTROL */ #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT … #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_MASK … #define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT … #define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_MASK … #define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT … #define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_MASK … #define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_SHIFT … #define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_MASK … #define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT … #define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_MASK … #define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_SHIFT … #define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_MASK … /* CPU_CA53_CFG_ARM_AFFINITY */ #define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_1_SHIFT … #define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_1_MASK … #define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_2_SHIFT … #define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_2_MASK … /* CPU_CA53_CFG_ARM_DISABLE */ #define CPU_CA53_CFG_ARM_DISABLE_CP15S_SHIFT … #define CPU_CA53_CFG_ARM_DISABLE_CP15S_MASK … #define CPU_CA53_CFG_ARM_DISABLE_CRYPTO_SHIFT … #define CPU_CA53_CFG_ARM_DISABLE_CRYPTO_MASK … #define CPU_CA53_CFG_ARM_DISABLE_L2_RST_SHIFT … #define CPU_CA53_CFG_ARM_DISABLE_L2_RST_MASK … #define CPU_CA53_CFG_ARM_DISABLE_DBG_L1_RST_SHIFT … #define CPU_CA53_CFG_ARM_DISABLE_DBG_L1_RST_MASK … /* CPU_CA53_CFG_ARM_GIC_PERIPHBASE */ #define CPU_CA53_CFG_ARM_GIC_PERIPHBASE_PERIPHBASE_SHIFT … #define CPU_CA53_CFG_ARM_GIC_PERIPHBASE_PERIPHBASE_MASK … /* CPU_CA53_CFG_ARM_GIC_IRQ_CFG */ #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NREI_SHIFT … #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NREI_MASK … #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NSEI_SHIFT … #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NSEI_MASK … #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NIRQ_SHIFT … #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NIRQ_MASK … #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NFIQ_SHIFT … #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NFIQ_MASK … #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVFIQ_SHIFT … #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVFIQ_MASK … #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVIRQ_SHIFT … #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVIRQ_MASK … #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVSEI_SHIFT … #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVSEI_MASK … #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_GIC_EN_SHIFT … #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_GIC_EN_MASK … /* CPU_CA53_CFG_ARM_PWR_MNG */ #define CPU_CA53_CFG_ARM_PWR_MNG_CLREXMONREQ_SHIFT … #define CPU_CA53_CFG_ARM_PWR_MNG_CLREXMONREQ_MASK … #define CPU_CA53_CFG_ARM_PWR_MNG_EVENTI_SHIFT … #define CPU_CA53_CFG_ARM_PWR_MNG_EVENTI_MASK … #define CPU_CA53_CFG_ARM_PWR_MNG_L2FLUSHREQ_SHIFT … #define CPU_CA53_CFG_ARM_PWR_MNG_L2FLUSHREQ_MASK … #define CPU_CA53_CFG_ARM_PWR_MNG_L2QREQN_SHIFT … #define CPU_CA53_CFG_ARM_PWR_MNG_L2QREQN_MASK … #define CPU_CA53_CFG_ARM_PWR_MNG_CPUQREQN_SHIFT … #define CPU_CA53_CFG_ARM_PWR_MNG_CPUQREQN_MASK … #define CPU_CA53_CFG_ARM_PWR_MNG_NEONQREQN_SHIFT … #define CPU_CA53_CFG_ARM_PWR_MNG_NEONQREQN_MASK … #define CPU_CA53_CFG_ARM_PWR_MNG_DBGPWRDUP_SHIFT … #define CPU_CA53_CFG_ARM_PWR_MNG_DBGPWRDUP_MASK … /* CPU_CA53_CFG_ARB_DBG_ROM_ADDR */ #define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_SHIFT … #define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_MASK … #define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_VALID_SHIFT … #define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_VALID_MASK … /* CPU_CA53_CFG_ARM_DBG_MODES */ #define CPU_CA53_CFG_ARM_DBG_MODES_EDBGRQ_SHIFT … #define CPU_CA53_CFG_ARM_DBG_MODES_EDBGRQ_MASK … #define CPU_CA53_CFG_ARM_DBG_MODES_DBGEN_SHIFT … #define CPU_CA53_CFG_ARM_DBG_MODES_DBGEN_MASK … #define CPU_CA53_CFG_ARM_DBG_MODES_NIDEN_SHIFT … #define CPU_CA53_CFG_ARM_DBG_MODES_NIDEN_MASK … #define CPU_CA53_CFG_ARM_DBG_MODES_SPIDEN_SHIFT … #define CPU_CA53_CFG_ARM_DBG_MODES_SPIDEN_MASK … #define CPU_CA53_CFG_ARM_DBG_MODES_SPNIDEN_SHIFT … #define CPU_CA53_CFG_ARM_DBG_MODES_SPNIDEN_MASK … /* CPU_CA53_CFG_ARM_PWR_STAT_0 */ #define CPU_CA53_CFG_ARM_PWR_STAT_0_CLREXMONACK_SHIFT … #define CPU_CA53_CFG_ARM_PWR_STAT_0_CLREXMONACK_MASK … #define CPU_CA53_CFG_ARM_PWR_STAT_0_EVENTO_SHIFT … #define CPU_CA53_CFG_ARM_PWR_STAT_0_EVENTO_MASK … #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFI_SHIFT … #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFI_MASK … #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFE_SHIFT … #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFE_MASK … #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFIL2_SHIFT … #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFIL2_MASK … #define CPU_CA53_CFG_ARM_PWR_STAT_0_L2FLUSHDONE_SHIFT … #define CPU_CA53_CFG_ARM_PWR_STAT_0_L2FLUSHDONE_MASK … #define CPU_CA53_CFG_ARM_PWR_STAT_0_SMPEN_SHIFT … #define CPU_CA53_CFG_ARM_PWR_STAT_0_SMPEN_MASK … /* CPU_CA53_CFG_ARM_PWR_STAT_1 */ #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACTIVE_SHIFT … #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACTIVE_MASK … #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQDENY_SHIFT … #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQDENY_MASK … #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACCEPTN_SHIFT … #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACCEPTN_MASK … #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACTIVE_SHIFT … #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACTIVE_MASK … #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQDENY_SHIFT … #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQDENY_MASK … #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACCEPTN_SHIFT … #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACCEPTN_MASK … #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACTIVE_SHIFT … #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACTIVE_MASK … #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QDENY_SHIFT … #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QDENY_MASK … #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACCEPTN_SHIFT … #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACCEPTN_MASK … /* CPU_CA53_CFG_ARM_DBG_STATUS */ #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGACK_SHIFT … #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGACK_MASK … #define CPU_CA53_CFG_ARM_DBG_STATUS_COMMRX_SHIFT … #define CPU_CA53_CFG_ARM_DBG_STATUS_COMMRX_MASK … #define CPU_CA53_CFG_ARM_DBG_STATUS_COMMTX_SHIFT … #define CPU_CA53_CFG_ARM_DBG_STATUS_COMMTX_MASK … #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGRSTREQ_SHIFT … #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGRSTREQ_MASK … #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGNOPWRDWN_SHIFT … #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGNOPWRDWN_MASK … #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGPWRUPREQ_SHIFT … #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGPWRUPREQ_MASK … /* CPU_CA53_CFG_ARM_MEM_ATTR */ #define CPU_CA53_CFG_ARM_MEM_ATTR_RDMEMATTR_SHIFT … #define CPU_CA53_CFG_ARM_MEM_ATTR_RDMEMATTR_MASK … #define CPU_CA53_CFG_ARM_MEM_ATTR_WRMEMATTR_SHIFT … #define CPU_CA53_CFG_ARM_MEM_ATTR_WRMEMATTR_MASK … #define CPU_CA53_CFG_ARM_MEM_ATTR_RACKM_SHIFT … #define CPU_CA53_CFG_ARM_MEM_ATTR_RACKM_MASK … #define CPU_CA53_CFG_ARM_MEM_ATTR_WACKM_SHIFT … #define CPU_CA53_CFG_ARM_MEM_ATTR_WACKM_MASK … /* CPU_CA53_CFG_ARM_PMU */ #define CPU_CA53_CFG_ARM_PMU_EVENT_SHIFT … #define CPU_CA53_CFG_ARM_PMU_EVENT_MASK … #endif /* ASIC_REG_CPU_CA53_CFG_MASKS_H_ */
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