/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2018 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_MMU_MASKS_H_ #define ASIC_REG_MMU_MASKS_H_ /* ***************************************** * MMU (Prototype: MMU) ***************************************** */ /* MMU_INPUT_FIFO_THRESHOLD */ #define MMU_INPUT_FIFO_THRESHOLD_PCI_SHIFT … #define MMU_INPUT_FIFO_THRESHOLD_PCI_MASK … #define MMU_INPUT_FIFO_THRESHOLD_PSOC_SHIFT … #define MMU_INPUT_FIFO_THRESHOLD_PSOC_MASK … #define MMU_INPUT_FIFO_THRESHOLD_DMA_SHIFT … #define MMU_INPUT_FIFO_THRESHOLD_DMA_MASK … #define MMU_INPUT_FIFO_THRESHOLD_CPU_SHIFT … #define MMU_INPUT_FIFO_THRESHOLD_CPU_MASK … #define MMU_INPUT_FIFO_THRESHOLD_MME_SHIFT … #define MMU_INPUT_FIFO_THRESHOLD_MME_MASK … #define MMU_INPUT_FIFO_THRESHOLD_TPC_SHIFT … #define MMU_INPUT_FIFO_THRESHOLD_TPC_MASK … #define MMU_INPUT_FIFO_THRESHOLD_OTHER_SHIFT … #define MMU_INPUT_FIFO_THRESHOLD_OTHER_MASK … /* MMU_MMU_ENABLE */ #define MMU_MMU_ENABLE_R_SHIFT … #define MMU_MMU_ENABLE_R_MASK … /* MMU_FORCE_ORDERING */ #define MMU_FORCE_ORDERING_DMA_WEAK_ORDERING_SHIFT … #define MMU_FORCE_ORDERING_DMA_WEAK_ORDERING_MASK … #define MMU_FORCE_ORDERING_PSOC_WEAK_ORDERING_SHIFT … #define MMU_FORCE_ORDERING_PSOC_WEAK_ORDERING_MASK … #define MMU_FORCE_ORDERING_PCI_WEAK_ORDERING_SHIFT … #define MMU_FORCE_ORDERING_PCI_WEAK_ORDERING_MASK … #define MMU_FORCE_ORDERING_CPU_WEAK_ORDERING_SHIFT … #define MMU_FORCE_ORDERING_CPU_WEAK_ORDERING_MASK … #define MMU_FORCE_ORDERING_MME_WEAK_ORDERING_SHIFT … #define MMU_FORCE_ORDERING_MME_WEAK_ORDERING_MASK … #define MMU_FORCE_ORDERING_TPC_WEAK_ORDERING_SHIFT … #define MMU_FORCE_ORDERING_TPC_WEAK_ORDERING_MASK … #define MMU_FORCE_ORDERING_DEFAULT_WEAK_ORDERING_SHIFT … #define MMU_FORCE_ORDERING_DEFAULT_WEAK_ORDERING_MASK … #define MMU_FORCE_ORDERING_DMA_STRONG_ORDERING_SHIFT … #define MMU_FORCE_ORDERING_DMA_STRONG_ORDERING_MASK … #define MMU_FORCE_ORDERING_PSOC_STRONG_ORDERING_SHIFT … #define MMU_FORCE_ORDERING_PSOC_STRONG_ORDERING_MASK … #define MMU_FORCE_ORDERING_PCI_STRONG_ORDERING_SHIFT … #define MMU_FORCE_ORDERING_PCI_STRONG_ORDERING_MASK … #define MMU_FORCE_ORDERING_CPU_STRONG_ORDERING_SHIFT … #define MMU_FORCE_ORDERING_CPU_STRONG_ORDERING_MASK … #define MMU_FORCE_ORDERING_MME_STRONG_ORDERING_SHIFT … #define MMU_FORCE_ORDERING_MME_STRONG_ORDERING_MASK … #define MMU_FORCE_ORDERING_TPC_STRONG_ORDERING_SHIFT … #define MMU_FORCE_ORDERING_TPC_STRONG_ORDERING_MASK … #define MMU_FORCE_ORDERING_DEFAULT_STRONG_ORDERING_SHIFT … #define MMU_FORCE_ORDERING_DEFAULT_STRONG_ORDERING_MASK … /* MMU_FEATURE_ENABLE */ #define MMU_FEATURE_ENABLE_VA_ORDERING_EN_SHIFT … #define MMU_FEATURE_ENABLE_VA_ORDERING_EN_MASK … #define MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_SHIFT … #define MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_MASK … #define MMU_FEATURE_ENABLE_HOP_OFFSET_EN_SHIFT … #define MMU_FEATURE_ENABLE_HOP_OFFSET_EN_MASK … #define MMU_FEATURE_ENABLE_OBI_ORDERING_EN_SHIFT … #define MMU_FEATURE_ENABLE_OBI_ORDERING_EN_MASK … #define MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_SHIFT … #define MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_MASK … #define MMU_FEATURE_ENABLE_TRACE_ENABLE_SHIFT … #define MMU_FEATURE_ENABLE_TRACE_ENABLE_MASK … /* MMU_VA_ORDERING_MASK_31_7 */ #define MMU_VA_ORDERING_MASK_31_7_R_SHIFT … #define MMU_VA_ORDERING_MASK_31_7_R_MASK … /* MMU_VA_ORDERING_MASK_49_32 */ #define MMU_VA_ORDERING_MASK_49_32_R_SHIFT … #define MMU_VA_ORDERING_MASK_49_32_R_MASK … /* MMU_LOG2_DDR_SIZE */ #define MMU_LOG2_DDR_SIZE_R_SHIFT … #define MMU_LOG2_DDR_SIZE_R_MASK … /* MMU_SCRAMBLER */ #define MMU_SCRAMBLER_ADDR_BIT_SHIFT … #define MMU_SCRAMBLER_ADDR_BIT_MASK … #define MMU_SCRAMBLER_SINGLE_DDR_EN_SHIFT … #define MMU_SCRAMBLER_SINGLE_DDR_EN_MASK … #define MMU_SCRAMBLER_SINGLE_DDR_ID_SHIFT … #define MMU_SCRAMBLER_SINGLE_DDR_ID_MASK … /* MMU_MEM_INIT_BUSY */ #define MMU_MEM_INIT_BUSY_DATA_SHIFT … #define MMU_MEM_INIT_BUSY_DATA_MASK … #define MMU_MEM_INIT_BUSY_OBI0_SHIFT … #define MMU_MEM_INIT_BUSY_OBI0_MASK … #define MMU_MEM_INIT_BUSY_OBI1_SHIFT … #define MMU_MEM_INIT_BUSY_OBI1_MASK … /* MMU_SPI_MASK */ #define MMU_SPI_MASK_R_SHIFT … #define MMU_SPI_MASK_R_MASK … /* MMU_SPI_CAUSE */ #define MMU_SPI_CAUSE_R_SHIFT … #define MMU_SPI_CAUSE_R_MASK … /* MMU_PAGE_ERROR_CAPTURE */ #define MMU_PAGE_ERROR_CAPTURE_VA_49_32_SHIFT … #define MMU_PAGE_ERROR_CAPTURE_VA_49_32_MASK … #define MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_SHIFT … #define MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK … /* MMU_PAGE_ERROR_CAPTURE_VA */ #define MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_SHIFT … #define MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_MASK … /* MMU_ACCESS_ERROR_CAPTURE */ #define MMU_ACCESS_ERROR_CAPTURE_VA_49_32_SHIFT … #define MMU_ACCESS_ERROR_CAPTURE_VA_49_32_MASK … #define MMU_ACCESS_ERROR_CAPTURE_ENTRY_VALID_SHIFT … #define MMU_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK … /* MMU_ACCESS_ERROR_CAPTURE_VA */ #define MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_SHIFT … #define MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_MASK … #endif /* ASIC_REG_MMU_MASKS_H_ */
Codebase Browser
linux