linux/drivers/accel/habanalabs/include/goya/asic_reg/goya_masks.h

/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2018 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

#ifndef ASIC_REG_GOYA_MASKS_H_
#define ASIC_REG_GOYA_MASKS_H_

#include "goya_regs.h"

/* Useful masks for bits in various registers */
#define QMAN_DMA_ENABLE …

#define QMAN_DMA_FULLY_TRUSTED …

#define QMAN_DMA_PARTLY_TRUSTED …

#define QMAN_DMA_STOP …

#define QMAN_DMA_IS_STOPPED …

#define QMAN_DMA_ERR_MSG_EN …

#define QMAN_MME_ENABLE …

#define CMDQ_MME_ENABLE …

#define QMAN_MME_STOP …

#define CMDQ_MME_STOP …

#define QMAN_MME_ERR_MSG_EN …

#define CMDQ_MME_ERR_MSG_EN …

#define QMAN_MME_ERR_PROT …

#define CMDQ_MME_ERR_PROT …

#define QMAN_TPC_ENABLE …

#define CMDQ_TPC_ENABLE …

#define QMAN_TPC_STOP …

#define CMDQ_TPC_STOP …

#define QMAN_TPC_ERR_MSG_EN …

#define CMDQ_TPC_ERR_MSG_EN …

#define QMAN_TPC_ERR_PROT …

#define CMDQ_TPC_ERR_PROT …

/* RESETS */
#define DMA_MME_TPC_RESET …

#define RESET_ALL …

#define CA53_RESET …

#define CPU_RESET_ASSERT …

#define CPU_RESET_CORE0_DEASSERT …

#define GOYA_IRQ_HBW_ID_MASK …
#define GOYA_IRQ_HBW_ID_SHIFT …
#define GOYA_IRQ_HBW_INTERNAL_ID_MASK …
#define GOYA_IRQ_HBW_INTERNAL_ID_SHIFT …
#define GOYA_IRQ_HBW_AGENT_ID_MASK …
#define GOYA_IRQ_HBW_AGENT_ID_SHIFT …
#define GOYA_IRQ_HBW_Y_MASK …
#define GOYA_IRQ_HBW_Y_SHIFT …
#define GOYA_IRQ_HBW_X_MASK …
#define GOYA_IRQ_HBW_X_SHIFT …
#define GOYA_IRQ_LBW_ID_MASK …
#define GOYA_IRQ_LBW_ID_SHIFT …
#define GOYA_IRQ_LBW_INTERNAL_ID_MASK …
#define GOYA_IRQ_LBW_INTERNAL_ID_SHIFT …
#define GOYA_IRQ_LBW_AGENT_ID_MASK …
#define GOYA_IRQ_LBW_AGENT_ID_SHIFT …
#define GOYA_IRQ_LBW_Y_MASK …
#define GOYA_IRQ_LBW_Y_SHIFT …
#define GOYA_IRQ_LBW_X_MASK …
#define GOYA_IRQ_LBW_X_SHIFT …

#define DMA_QM_IDLE_MASK …

#define TPC_QM_IDLE_MASK …

#define TPC_CMDQ_IDLE_MASK …

#define TPC_CFG_IDLE_MASK …

#define MME_QM_IDLE_MASK …

#define MME_CMDQ_IDLE_MASK …

#define MME_ARCH_IDLE_MASK …

#define MME_SHADOW_IDLE_MASK …

#define TPC1_CFG_TPC_STALL_V_SHIFT …
#define TPC2_CFG_TPC_STALL_V_SHIFT …
#define TPC3_CFG_TPC_STALL_V_SHIFT …
#define TPC4_CFG_TPC_STALL_V_SHIFT …
#define TPC5_CFG_TPC_STALL_V_SHIFT …
#define TPC6_CFG_TPC_STALL_V_SHIFT …
#define TPC7_CFG_TPC_STALL_V_SHIFT …

#define DMA_QM_1_GLBL_CFG1_DMA_STOP_SHIFT …
#define DMA_QM_2_GLBL_CFG1_DMA_STOP_SHIFT …
#define DMA_QM_3_GLBL_CFG1_DMA_STOP_SHIFT …
#define DMA_QM_4_GLBL_CFG1_DMA_STOP_SHIFT …

#define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT …
#define PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK …
#define PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK …
#define PSOC_ETR_AXICTL_WRBURSTLEN_MASK …

#endif /* ASIC_REG_GOYA_MASKS_H_ */