/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2018 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DMA0_CORE_MASKS_H_ #define ASIC_REG_DMA0_CORE_MASKS_H_ /* ***************************************** * DMA0_CORE (Prototype: DMA_CORE) ***************************************** */ /* DMA0_CORE_CFG_0 */ #define DMA0_CORE_CFG_0_EN_SHIFT … #define DMA0_CORE_CFG_0_EN_MASK … /* DMA0_CORE_CFG_1 */ #define DMA0_CORE_CFG_1_HALT_SHIFT … #define DMA0_CORE_CFG_1_HALT_MASK … #define DMA0_CORE_CFG_1_FLUSH_SHIFT … #define DMA0_CORE_CFG_1_FLUSH_MASK … #define DMA0_CORE_CFG_1_SB_FORCE_MISS_SHIFT … #define DMA0_CORE_CFG_1_SB_FORCE_MISS_MASK … /* DMA0_CORE_LBW_MAX_OUTSTAND */ #define DMA0_CORE_LBW_MAX_OUTSTAND_VAL_SHIFT … #define DMA0_CORE_LBW_MAX_OUTSTAND_VAL_MASK … /* DMA0_CORE_SRC_BASE_LO */ #define DMA0_CORE_SRC_BASE_LO_VAL_SHIFT … #define DMA0_CORE_SRC_BASE_LO_VAL_MASK … /* DMA0_CORE_SRC_BASE_HI */ #define DMA0_CORE_SRC_BASE_HI_VAL_SHIFT … #define DMA0_CORE_SRC_BASE_HI_VAL_MASK … /* DMA0_CORE_DST_BASE_LO */ #define DMA0_CORE_DST_BASE_LO_VAL_SHIFT … #define DMA0_CORE_DST_BASE_LO_VAL_MASK … /* DMA0_CORE_DST_BASE_HI */ #define DMA0_CORE_DST_BASE_HI_VAL_SHIFT … #define DMA0_CORE_DST_BASE_HI_VAL_MASK … #define DMA0_CORE_DST_BASE_HI_CTX_ID_HI_SHIFT … #define DMA0_CORE_DST_BASE_HI_CTX_ID_HI_MASK … /* DMA0_CORE_SRC_TSIZE_1 */ #define DMA0_CORE_SRC_TSIZE_1_VAL_SHIFT … #define DMA0_CORE_SRC_TSIZE_1_VAL_MASK … /* DMA0_CORE_SRC_STRIDE_1 */ #define DMA0_CORE_SRC_STRIDE_1_VAL_SHIFT … #define DMA0_CORE_SRC_STRIDE_1_VAL_MASK … /* DMA0_CORE_SRC_TSIZE_2 */ #define DMA0_CORE_SRC_TSIZE_2_VAL_SHIFT … #define DMA0_CORE_SRC_TSIZE_2_VAL_MASK … /* DMA0_CORE_SRC_STRIDE_2 */ #define DMA0_CORE_SRC_STRIDE_2_VAL_SHIFT … #define DMA0_CORE_SRC_STRIDE_2_VAL_MASK … /* DMA0_CORE_SRC_TSIZE_3 */ #define DMA0_CORE_SRC_TSIZE_3_VAL_SHIFT … #define DMA0_CORE_SRC_TSIZE_3_VAL_MASK … /* DMA0_CORE_SRC_STRIDE_3 */ #define DMA0_CORE_SRC_STRIDE_3_VAL_SHIFT … #define DMA0_CORE_SRC_STRIDE_3_VAL_MASK … /* DMA0_CORE_SRC_TSIZE_4 */ #define DMA0_CORE_SRC_TSIZE_4_VAL_SHIFT … #define DMA0_CORE_SRC_TSIZE_4_VAL_MASK … /* DMA0_CORE_SRC_STRIDE_4 */ #define DMA0_CORE_SRC_STRIDE_4_VAL_SHIFT … #define DMA0_CORE_SRC_STRIDE_4_VAL_MASK … /* DMA0_CORE_SRC_TSIZE_0 */ #define DMA0_CORE_SRC_TSIZE_0_VAL_SHIFT … #define DMA0_CORE_SRC_TSIZE_0_VAL_MASK … /* DMA0_CORE_DST_TSIZE_1 */ #define DMA0_CORE_DST_TSIZE_1_VAL_SHIFT … #define DMA0_CORE_DST_TSIZE_1_VAL_MASK … /* DMA0_CORE_DST_STRIDE_1 */ #define DMA0_CORE_DST_STRIDE_1_VAL_SHIFT … #define DMA0_CORE_DST_STRIDE_1_VAL_MASK … /* DMA0_CORE_DST_TSIZE_2 */ #define DMA0_CORE_DST_TSIZE_2_VAL_SHIFT … #define DMA0_CORE_DST_TSIZE_2_VAL_MASK … /* DMA0_CORE_DST_STRIDE_2 */ #define DMA0_CORE_DST_STRIDE_2_VAL_SHIFT … #define DMA0_CORE_DST_STRIDE_2_VAL_MASK … /* DMA0_CORE_DST_TSIZE_3 */ #define DMA0_CORE_DST_TSIZE_3_VAL_SHIFT … #define DMA0_CORE_DST_TSIZE_3_VAL_MASK … /* DMA0_CORE_DST_STRIDE_3 */ #define DMA0_CORE_DST_STRIDE_3_VAL_SHIFT … #define DMA0_CORE_DST_STRIDE_3_VAL_MASK … /* DMA0_CORE_DST_TSIZE_4 */ #define DMA0_CORE_DST_TSIZE_4_VAL_SHIFT … #define DMA0_CORE_DST_TSIZE_4_VAL_MASK … /* DMA0_CORE_DST_STRIDE_4 */ #define DMA0_CORE_DST_STRIDE_4_VAL_SHIFT … #define DMA0_CORE_DST_STRIDE_4_VAL_MASK … /* DMA0_CORE_DST_TSIZE_0 */ #define DMA0_CORE_DST_TSIZE_0_VAL_SHIFT … #define DMA0_CORE_DST_TSIZE_0_VAL_MASK … /* DMA0_CORE_COMMIT */ #define DMA0_CORE_COMMIT_WR_COMP_EN_SHIFT … #define DMA0_CORE_COMMIT_WR_COMP_EN_MASK … #define DMA0_CORE_COMMIT_TRANSPOSE_SHIFT … #define DMA0_CORE_COMMIT_TRANSPOSE_MASK … #define DMA0_CORE_COMMIT_DTYPE_SHIFT … #define DMA0_CORE_COMMIT_DTYPE_MASK … #define DMA0_CORE_COMMIT_LIN_SHIFT … #define DMA0_CORE_COMMIT_LIN_MASK … #define DMA0_CORE_COMMIT_MEM_SET_SHIFT … #define DMA0_CORE_COMMIT_MEM_SET_MASK … #define DMA0_CORE_COMMIT_COMPRESS_SHIFT … #define DMA0_CORE_COMMIT_COMPRESS_MASK … #define DMA0_CORE_COMMIT_DECOMPRESS_SHIFT … #define DMA0_CORE_COMMIT_DECOMPRESS_MASK … #define DMA0_CORE_COMMIT_CTX_ID_SHIFT … #define DMA0_CORE_COMMIT_CTX_ID_MASK … /* DMA0_CORE_WR_COMP_WDATA */ #define DMA0_CORE_WR_COMP_WDATA_VAL_SHIFT … #define DMA0_CORE_WR_COMP_WDATA_VAL_MASK … /* DMA0_CORE_WR_COMP_ADDR_LO */ #define DMA0_CORE_WR_COMP_ADDR_LO_VAL_SHIFT … #define DMA0_CORE_WR_COMP_ADDR_LO_VAL_MASK … /* DMA0_CORE_WR_COMP_ADDR_HI */ #define DMA0_CORE_WR_COMP_ADDR_HI_VAL_SHIFT … #define DMA0_CORE_WR_COMP_ADDR_HI_VAL_MASK … /* DMA0_CORE_WR_COMP_AWUSER_31_11 */ #define DMA0_CORE_WR_COMP_AWUSER_31_11_VAL_SHIFT … #define DMA0_CORE_WR_COMP_AWUSER_31_11_VAL_MASK … /* DMA0_CORE_TE_NUMROWS */ #define DMA0_CORE_TE_NUMROWS_VAL_SHIFT … #define DMA0_CORE_TE_NUMROWS_VAL_MASK … /* DMA0_CORE_PROT */ #define DMA0_CORE_PROT_VAL_SHIFT … #define DMA0_CORE_PROT_VAL_MASK … #define DMA0_CORE_PROT_ERR_VAL_SHIFT … #define DMA0_CORE_PROT_ERR_VAL_MASK … /* DMA0_CORE_SECURE_PROPS */ #define DMA0_CORE_SECURE_PROPS_ASID_SHIFT … #define DMA0_CORE_SECURE_PROPS_ASID_MASK … #define DMA0_CORE_SECURE_PROPS_MMBP_SHIFT … #define DMA0_CORE_SECURE_PROPS_MMBP_MASK … /* DMA0_CORE_NON_SECURE_PROPS */ #define DMA0_CORE_NON_SECURE_PROPS_ASID_SHIFT … #define DMA0_CORE_NON_SECURE_PROPS_ASID_MASK … #define DMA0_CORE_NON_SECURE_PROPS_MMBP_SHIFT … #define DMA0_CORE_NON_SECURE_PROPS_MMBP_MASK … /* DMA0_CORE_RD_MAX_OUTSTAND */ #define DMA0_CORE_RD_MAX_OUTSTAND_VAL_SHIFT … #define DMA0_CORE_RD_MAX_OUTSTAND_VAL_MASK … /* DMA0_CORE_RD_MAX_SIZE */ #define DMA0_CORE_RD_MAX_SIZE_DATA_SHIFT … #define DMA0_CORE_RD_MAX_SIZE_DATA_MASK … #define DMA0_CORE_RD_MAX_SIZE_MD_SHIFT … #define DMA0_CORE_RD_MAX_SIZE_MD_MASK … /* DMA0_CORE_RD_ARCACHE */ #define DMA0_CORE_RD_ARCACHE_VAL_SHIFT … #define DMA0_CORE_RD_ARCACHE_VAL_MASK … /* DMA0_CORE_RD_ARUSER_31_11 */ #define DMA0_CORE_RD_ARUSER_31_11_VAL_SHIFT … #define DMA0_CORE_RD_ARUSER_31_11_VAL_MASK … /* DMA0_CORE_RD_INFLIGHTS */ #define DMA0_CORE_RD_INFLIGHTS_VAL_SHIFT … #define DMA0_CORE_RD_INFLIGHTS_VAL_MASK … /* DMA0_CORE_WR_MAX_OUTSTAND */ #define DMA0_CORE_WR_MAX_OUTSTAND_VAL_SHIFT … #define DMA0_CORE_WR_MAX_OUTSTAND_VAL_MASK … /* DMA0_CORE_WR_MAX_AWID */ #define DMA0_CORE_WR_MAX_AWID_VAL_SHIFT … #define DMA0_CORE_WR_MAX_AWID_VAL_MASK … /* DMA0_CORE_WR_AWCACHE */ #define DMA0_CORE_WR_AWCACHE_VAL_SHIFT … #define DMA0_CORE_WR_AWCACHE_VAL_MASK … /* DMA0_CORE_WR_AWUSER_31_11 */ #define DMA0_CORE_WR_AWUSER_31_11_VAL_SHIFT … #define DMA0_CORE_WR_AWUSER_31_11_VAL_MASK … /* DMA0_CORE_WR_INFLIGHTS */ #define DMA0_CORE_WR_INFLIGHTS_VAL_SHIFT … #define DMA0_CORE_WR_INFLIGHTS_VAL_MASK … /* DMA0_CORE_RD_RATE_LIM_CFG_0 */ #define DMA0_CORE_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT … #define DMA0_CORE_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK … #define DMA0_CORE_RD_RATE_LIM_CFG_0_SAT_SHIFT … #define DMA0_CORE_RD_RATE_LIM_CFG_0_SAT_MASK … /* DMA0_CORE_RD_RATE_LIM_CFG_1 */ #define DMA0_CORE_RD_RATE_LIM_CFG_1_TOUT_SHIFT … #define DMA0_CORE_RD_RATE_LIM_CFG_1_TOUT_MASK … #define DMA0_CORE_RD_RATE_LIM_CFG_1_EN_SHIFT … #define DMA0_CORE_RD_RATE_LIM_CFG_1_EN_MASK … /* DMA0_CORE_WR_RATE_LIM_CFG_0 */ #define DMA0_CORE_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT … #define DMA0_CORE_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK … #define DMA0_CORE_WR_RATE_LIM_CFG_0_SAT_SHIFT … #define DMA0_CORE_WR_RATE_LIM_CFG_0_SAT_MASK … /* DMA0_CORE_WR_RATE_LIM_CFG_1 */ #define DMA0_CORE_WR_RATE_LIM_CFG_1_TOUT_SHIFT … #define DMA0_CORE_WR_RATE_LIM_CFG_1_TOUT_MASK … #define DMA0_CORE_WR_RATE_LIM_CFG_1_EN_SHIFT … #define DMA0_CORE_WR_RATE_LIM_CFG_1_EN_MASK … /* DMA0_CORE_ERR_CFG */ #define DMA0_CORE_ERR_CFG_ERR_MSG_EN_SHIFT … #define DMA0_CORE_ERR_CFG_ERR_MSG_EN_MASK … #define DMA0_CORE_ERR_CFG_STOP_ON_ERR_SHIFT … #define DMA0_CORE_ERR_CFG_STOP_ON_ERR_MASK … /* DMA0_CORE_ERR_CAUSE */ #define DMA0_CORE_ERR_CAUSE_HBW_RD_ERR_SHIFT … #define DMA0_CORE_ERR_CAUSE_HBW_RD_ERR_MASK … #define DMA0_CORE_ERR_CAUSE_HBW_WR_ERR_SHIFT … #define DMA0_CORE_ERR_CAUSE_HBW_WR_ERR_MASK … #define DMA0_CORE_ERR_CAUSE_LBW_WR_ERR_SHIFT … #define DMA0_CORE_ERR_CAUSE_LBW_WR_ERR_MASK … #define DMA0_CORE_ERR_CAUSE_DESC_OVF_SHIFT … #define DMA0_CORE_ERR_CAUSE_DESC_OVF_MASK … /* DMA0_CORE_ERRMSG_ADDR_LO */ #define DMA0_CORE_ERRMSG_ADDR_LO_VAL_SHIFT … #define DMA0_CORE_ERRMSG_ADDR_LO_VAL_MASK … /* DMA0_CORE_ERRMSG_ADDR_HI */ #define DMA0_CORE_ERRMSG_ADDR_HI_VAL_SHIFT … #define DMA0_CORE_ERRMSG_ADDR_HI_VAL_MASK … /* DMA0_CORE_ERRMSG_WDATA */ #define DMA0_CORE_ERRMSG_WDATA_VAL_SHIFT … #define DMA0_CORE_ERRMSG_WDATA_VAL_MASK … /* DMA0_CORE_STS0 */ #define DMA0_CORE_STS0_RD_REQ_CNT_SHIFT … #define DMA0_CORE_STS0_RD_REQ_CNT_MASK … #define DMA0_CORE_STS0_WR_REQ_CNT_SHIFT … #define DMA0_CORE_STS0_WR_REQ_CNT_MASK … #define DMA0_CORE_STS0_BUSY_SHIFT … #define DMA0_CORE_STS0_BUSY_MASK … /* DMA0_CORE_STS1 */ #define DMA0_CORE_STS1_IS_HALT_SHIFT … #define DMA0_CORE_STS1_IS_HALT_MASK … /* DMA0_CORE_RD_DBGMEM_ADD */ #define DMA0_CORE_RD_DBGMEM_ADD_VAL_SHIFT … #define DMA0_CORE_RD_DBGMEM_ADD_VAL_MASK … /* DMA0_CORE_RD_DBGMEM_DATA_WR */ #define DMA0_CORE_RD_DBGMEM_DATA_WR_VAL_SHIFT … #define DMA0_CORE_RD_DBGMEM_DATA_WR_VAL_MASK … /* DMA0_CORE_RD_DBGMEM_DATA_RD */ #define DMA0_CORE_RD_DBGMEM_DATA_RD_VAL_SHIFT … #define DMA0_CORE_RD_DBGMEM_DATA_RD_VAL_MASK … /* DMA0_CORE_RD_DBGMEM_CTRL */ #define DMA0_CORE_RD_DBGMEM_CTRL_WR_NRD_SHIFT … #define DMA0_CORE_RD_DBGMEM_CTRL_WR_NRD_MASK … /* DMA0_CORE_RD_DBGMEM_RC */ #define DMA0_CORE_RD_DBGMEM_RC_VALID_SHIFT … #define DMA0_CORE_RD_DBGMEM_RC_VALID_MASK … /* DMA0_CORE_DBG_HBW_AXI_AR_CNT */ /* DMA0_CORE_DBG_HBW_AXI_AW_CNT */ /* DMA0_CORE_DBG_LBW_AXI_AW_CNT */ /* DMA0_CORE_DBG_DESC_CNT */ #define DMA0_CORE_DBG_DESC_CNT_RD_STS_CTX_CNT_SHIFT … #define DMA0_CORE_DBG_DESC_CNT_RD_STS_CTX_CNT_MASK … /* DMA0_CORE_DBG_STS */ #define DMA0_CORE_DBG_STS_RD_CTX_FULL_SHIFT … #define DMA0_CORE_DBG_STS_RD_CTX_FULL_MASK … #define DMA0_CORE_DBG_STS_WR_CTX_FULL_SHIFT … #define DMA0_CORE_DBG_STS_WR_CTX_FULL_MASK … #define DMA0_CORE_DBG_STS_WR_COMP_FULL_SHIFT … #define DMA0_CORE_DBG_STS_WR_COMP_FULL_MASK … #define DMA0_CORE_DBG_STS_RD_CTX_EMPTY_SHIFT … #define DMA0_CORE_DBG_STS_RD_CTX_EMPTY_MASK … #define DMA0_CORE_DBG_STS_WR_CTX_EMPTY_SHIFT … #define DMA0_CORE_DBG_STS_WR_CTX_EMPTY_MASK … #define DMA0_CORE_DBG_STS_WR_COMP_EMPTY_SHIFT … #define DMA0_CORE_DBG_STS_WR_COMP_EMPTY_MASK … #define DMA0_CORE_DBG_STS_TE_EMPTY_SHIFT … #define DMA0_CORE_DBG_STS_TE_EMPTY_MASK … #define DMA0_CORE_DBG_STS_TE_BUSY_SHIFT … #define DMA0_CORE_DBG_STS_TE_BUSY_MASK … #define DMA0_CORE_DBG_STS_GSKT_EMPTY_SHIFT … #define DMA0_CORE_DBG_STS_GSKT_EMPTY_MASK … #define DMA0_CORE_DBG_STS_GSKT_FULL_SHIFT … #define DMA0_CORE_DBG_STS_GSKT_FULL_MASK … #define DMA0_CORE_DBG_STS_RDBUF_FULLNESS_SHIFT … #define DMA0_CORE_DBG_STS_RDBUF_FULLNESS_MASK … /* DMA0_CORE_DBG_RD_DESC_ID */ /* DMA0_CORE_DBG_WR_DESC_ID */ #endif /* ASIC_REG_DMA0_CORE_MASKS_H_ */
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