#ifndef ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_
#define ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_
#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK …
#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT …
#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK …
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT …
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK …
#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT …
#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK …
#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT …
#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK …
#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_SHIFT …
#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_MASK …
#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_MASK …
#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SHIFT …
#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_MASK …
#define PSOC_GLOBAL_CONF_PRSTN_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_PRSTN_VAL_MASK …
#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_SHIFT …
#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_MASK …
#define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_SHIFT …
#define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_MASK …
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_SHIFT …
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_MASK …
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_SHIFT …
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_MASK …
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_SHIFT …
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_MASK …
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_SHIFT …
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_MASK …
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_SHIFT …
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_MASK …
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_SHIFT …
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_MASK …
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_SHIFT …
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_MASK …
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_SHIFT …
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_MASK …
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_SHIFT …
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_MASK …
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_SHIFT …
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_MASK …
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_SHIFT …
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_MASK …
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_SHIFT …
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_MASK …
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_SHIFT …
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_MASK …
#define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_SHIFT …
#define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_MASK …
#define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_SHIFT …
#define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_MASK …
#define PSOC_GLOBAL_CONF_PRSTN_OVR_EN_SHIFT …
#define PSOC_GLOBAL_CONF_PRSTN_OVR_EN_MASK …
#define PSOC_GLOBAL_CONF_PRSTN_OVR_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_PRSTN_OVR_VAL_MASK …
#define PSOC_GLOBAL_CONF_ETR_FLUSH_MASK_SHIFT …
#define PSOC_GLOBAL_CONF_ETR_FLUSH_MASK_MASK …
#define PSOC_GLOBAL_CONF_COLD_RST_FLOPS_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_COLD_RST_FLOPS_VAL_MASK …
#define PSOC_GLOBAL_CONF_DIS_RAZWI_ERR_IND_SHIFT …
#define PSOC_GLOBAL_CONF_DIS_RAZWI_ERR_IND_MASK …
#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_IND_SHIFT …
#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_IND_MASK …
#define PSOC_GLOBAL_CONF_RAZWI_INTR_SHIFT …
#define PSOC_GLOBAL_CONF_RAZWI_INTR_MASK …
#define PSOC_GLOBAL_CONF_RAZWI_MASK_SHIFT …
#define PSOC_GLOBAL_CONF_RAZWI_MASK_MASK …
#define PSOC_GLOBAL_CONF_PROT_AR_SHIFT …
#define PSOC_GLOBAL_CONF_PROT_AR_MASK …
#define PSOC_GLOBAL_CONF_PROT_AW_SHIFT …
#define PSOC_GLOBAL_CONF_PROT_AW_MASK …
#define PSOC_GLOBAL_CONF_ADC_INTR_SHIFT …
#define PSOC_GLOBAL_CONF_ADC_INTR_MASK …
#define PSOC_GLOBAL_CONF_ADC_MASK_SHIFT …
#define PSOC_GLOBAL_CONF_ADC_MASK_MASK …
#define PSOC_GLOBAL_CONF_BOOT_SEQ_TO_MASK_SHIFT …
#define PSOC_GLOBAL_CONF_BOOT_SEQ_TO_MASK_MASK …
#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_SHIFT …
#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_MASK …
#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_SHIFT …
#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_MASK …
#define PSOC_GLOBAL_CONF_CPU_BOOT_STATUS_CNTR_SHIFT …
#define PSOC_GLOBAL_CONF_CPU_BOOT_STATUS_CNTR_MASK …
#define PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU_VAL_MASK …
#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_MASK …
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_SHIFT …
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_MASK …
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_SHIFT …
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_MASK …
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_SHIFT …
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_MASK …
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_SHIFT …
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_MASK …
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_SHIFT …
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_MASK …
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_SHIFT …
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_MASK …
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_SHIFT …
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_MASK …
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_SHIFT …
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_MASK …
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_SHIFT …
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_MASK …
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_SHIFT …
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_MASK …
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_SHIFT …
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_MASK …
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_SHIFT …
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_MASK …
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_SHIFT …
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_MASK …
#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_SHIFT …
#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_MASK …
#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_FLD_INT_SHIFT …
#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_FLD_INT_MASK …
#define PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_SHIFT …
#define PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_MASK …
#define PSOC_GLOBAL_CONF_ARUSER_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_ARUSER_VAL_MASK …
#define PSOC_GLOBAL_CONF_AWUSER_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_AWUSER_VAL_MASK …
#define PSOC_GLOBAL_CONF_TRACE_AWUSER_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_TRACE_AWUSER_VAL_MASK …
#define PSOC_GLOBAL_CONF_TRACE_ARUSER_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_TRACE_ARUSER_VAL_MASK …
#define PSOC_GLOBAL_CONF_BTL_STS_DONE_SHIFT …
#define PSOC_GLOBAL_CONF_BTL_STS_DONE_MASK …
#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_SHIFT …
#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_MASK …
#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_SHIFT …
#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_MASK …
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_SHIFT …
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_MASK …
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_SHIFT …
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_MASK …
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_SHIFT …
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_MASK …
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_SHIFT …
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_MASK …
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_SHIFT …
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_MASK …
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_SHIFT …
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_MASK …
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_SHIFT …
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_MASK …
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_SHIFT …
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_MASK …
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_SHIFT …
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_MASK …
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_SHIFT …
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_MASK …
#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_SHIFT …
#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_MASK …
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_SHIFT …
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_MASK …
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_SHIFT …
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_MASK …
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_SHIFT …
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_MASK …
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_SHIFT …
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_MASK …
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_SHIFT …
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_MASK …
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_SHIFT …
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_MASK …
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_SHIFT …
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_MASK …
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_SHIFT …
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_MASK …
#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_SHIFT …
#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_MASK …
#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_SHIFT …
#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_MASK …
#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_SHIFT …
#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_MASK …
#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_SHIFT …
#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_MASK …
#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_SHIFT …
#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_MASK …
#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_SHIFT …
#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_MASK …
#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_SHIFT …
#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_MASK …
#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_SHIFT …
#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_MASK …
#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_SHIFT …
#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_MASK …
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SLV_ADDR_SHIFT …
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SLV_ADDR_MASK …
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PCIE_EN_SHIFT …
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PCIE_EN_MASK …
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_REPAIR_CFG_SHIFT …
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_REPAIR_CFG_MASK …
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPOL_SHIFT …
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPOL_MASK …
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPHA_SHIFT …
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPHA_MASK …
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_EN_SHIFT …
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_EN_MASK …
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_ROM_EN_SHIFT …
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_ROM_EN_MASK …
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_SEL_SHIFT …
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_SEL_MASK …
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_GRAD_RST_SHIFT …
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_GRAD_RST_MASK …
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_DIS_SHIFT …
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_DIS_MASK …
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SHIFT …
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_MASK …
#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_EN_SHIFT …
#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_EN_MASK …
#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_VAL_MASK …
#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_SHIFT …
#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_MASK …
#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_CLR_SHIFT …
#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_CLR_MASK …
#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_SHIFT …
#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_MASK …
#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_FAIL_SHIFT …
#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_FAIL_MASK …
#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_SHIFT …
#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_MASK …
#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_SHIFT …
#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_MASK …
#define PSOC_GLOBAL_CONF_MASK_REQ_IND_SHIFT …
#define PSOC_GLOBAL_CONF_MASK_REQ_IND_MASK …
#define PSOC_GLOBAL_CONF_WD_RST_CFG_L_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_WD_RST_CFG_L_VAL_MASK …
#define PSOC_GLOBAL_CONF_WD_RST_CFG_H_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_WD_RST_CFG_H_VAL_MASK …
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_L_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_L_VAL_MASK …
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_H_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_MNL_RST_CFG_H_VAL_MASK …
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_L_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_L_VAL_MASK …
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_H_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_H_VAL_MASK …
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L_VAL_MASK …
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H_VAL_MASK …
#define PSOC_GLOBAL_CONF_SW_ALL_RST_IND_SHIFT …
#define PSOC_GLOBAL_CONF_SW_ALL_RST_IND_MASK …
#define PSOC_GLOBAL_CONF_SOFT_RST_IND_SHIFT …
#define PSOC_GLOBAL_CONF_SOFT_RST_IND_MASK …
#define PSOC_GLOBAL_CONF_SOFT_RST_CFG_L_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_SOFT_RST_CFG_L_VAL_MASK …
#define PSOC_GLOBAL_CONF_SOFT_RST_CFG_H_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_SOFT_RST_CFG_H_VAL_MASK …
#define PSOC_GLOBAL_CONF_UNIT_RST_N_IND_SHIFT …
#define PSOC_GLOBAL_CONF_UNIT_RST_N_IND_MASK …
#define PSOC_GLOBAL_CONF_UNIT_RST_N_L_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_UNIT_RST_N_L_VAL_MASK …
#define PSOC_GLOBAL_CONF_UNIT_RST_N_H_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_UNIT_RST_N_H_VAL_MASK …
#define PSOC_GLOBAL_CONF_BTL_IMG_SEL_SHIFT …
#define PSOC_GLOBAL_CONF_BTL_IMG_SEL_MASK …
#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_SHIFT …
#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_MASK …
#define PSOC_GLOBAL_CONF_WD_MASK_IND_SHIFT …
#define PSOC_GLOBAL_CONF_WD_MASK_IND_MASK …
#define PSOC_GLOBAL_CONF_RST_SRC_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_RST_SRC_VAL_MASK …
#define PSOC_GLOBAL_CONF_BOOT_STATE_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_BOOT_STATE_VAL_MASK …
#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_MASK …
#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_MASK …
#define PSOC_GLOBAL_CONF_PAD_1V8_INPUT_CFG_SHIFT …
#define PSOC_GLOBAL_CONF_PAD_1V8_INPUT_CFG_MASK …
#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_MASK …
#define PSOC_GLOBAL_CONF_ADC_CLK_FREQ_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_ADC_CLK_FREQ_VAL_MASK …
#define PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_VAL_MASK …
#define PSOC_GLOBAL_CONF_ADC_DATA_SAMPLES_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_ADC_DATA_SAMPLES_VAL_MASK …
#define PSOC_GLOBAL_CONF_ADC_TPH_CS_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_ADC_TPH_CS_VAL_MASK …
#define PSOC_GLOBAL_CONF_ADC_LSB_NMSB_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_ADC_LSB_NMSB_VAL_MASK …
#define PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_VAL_MASK …
#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_VAL_MASK …
#define PSOC_GLOBAL_CONF_ADC_CFG_DATA_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_ADC_CFG_DATA_VAL_MASK …
#define PSOC_GLOBAL_CONF_ADC_TDV_CSDO_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_ADC_TDV_CSDO_VAL_MASK …
#define PSOC_GLOBAL_CONF_ADC_TSU_CSCK_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_ADC_TSU_CSCK_VAL_MASK …
#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_MASK …
#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_SHIFT …
#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_MASK …
#define PSOC_GLOBAL_CONF_RST_CTRL_SEL_SHIFT …
#define PSOC_GLOBAL_CONF_RST_CTRL_SEL_MASK …
#endif