linux/drivers/accel/habanalabs/include/gaudi/asic_reg/gaudi_regs.h

/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2020 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

#ifndef ASIC_REG_GAUDI_REGS_H_
#define ASIC_REG_GAUDI_REGS_H_

#include "gaudi_blocks.h"
#include "psoc_global_conf_regs.h"
#include "psoc_timestamp_regs.h"
#include "cpu_if_regs.h"
#include "mmu_up_regs.h"
#include "stlb_regs.h"
#include "dma0_qm_regs.h"
#include "dma1_qm_regs.h"
#include "dma2_qm_regs.h"
#include "dma3_qm_regs.h"
#include "dma4_qm_regs.h"
#include "dma5_qm_regs.h"
#include "dma6_qm_regs.h"
#include "dma7_qm_regs.h"
#include "dma0_core_regs.h"
#include "dma1_core_regs.h"
#include "dma2_core_regs.h"
#include "dma3_core_regs.h"
#include "dma4_core_regs.h"
#include "dma5_core_regs.h"
#include "dma6_core_regs.h"
#include "dma7_core_regs.h"
#include "mme0_ctrl_regs.h"
#include "mme1_ctrl_regs.h"
#include "mme2_ctrl_regs.h"
#include "mme3_ctrl_regs.h"
#include "mme0_qm_regs.h"
#include "mme2_qm_regs.h"
#include "tpc0_cfg_regs.h"
#include "tpc1_cfg_regs.h"
#include "tpc2_cfg_regs.h"
#include "tpc3_cfg_regs.h"
#include "tpc4_cfg_regs.h"
#include "tpc5_cfg_regs.h"
#include "tpc6_cfg_regs.h"
#include "tpc7_cfg_regs.h"
#include "tpc0_qm_regs.h"
#include "tpc1_qm_regs.h"
#include "tpc2_qm_regs.h"
#include "tpc3_qm_regs.h"
#include "tpc4_qm_regs.h"
#include "tpc5_qm_regs.h"
#include "tpc6_qm_regs.h"
#include "tpc7_qm_regs.h"
#include "dma_if_e_n_down_ch0_regs.h"
#include "dma_if_e_n_down_ch1_regs.h"
#include "dma_if_e_s_down_ch0_regs.h"
#include "dma_if_e_s_down_ch1_regs.h"
#include "dma_if_w_n_down_ch0_regs.h"
#include "dma_if_w_n_down_ch1_regs.h"
#include "dma_if_w_s_down_ch0_regs.h"
#include "dma_if_w_s_down_ch1_regs.h"
#include "dma_if_e_n_regs.h"
#include "dma_if_e_s_regs.h"
#include "dma_if_w_n_regs.h"
#include "dma_if_w_s_regs.h"
#include "nif_rtr_ctrl_0_regs.h"
#include "nif_rtr_ctrl_1_regs.h"
#include "nif_rtr_ctrl_2_regs.h"
#include "nif_rtr_ctrl_3_regs.h"
#include "nif_rtr_ctrl_4_regs.h"
#include "nif_rtr_ctrl_5_regs.h"
#include "nif_rtr_ctrl_6_regs.h"
#include "nif_rtr_ctrl_7_regs.h"
#include "sif_rtr_ctrl_0_regs.h"
#include "sif_rtr_ctrl_1_regs.h"
#include "sif_rtr_ctrl_2_regs.h"
#include "sif_rtr_ctrl_3_regs.h"
#include "sif_rtr_ctrl_4_regs.h"
#include "sif_rtr_ctrl_5_regs.h"
#include "sif_rtr_ctrl_6_regs.h"
#include "sif_rtr_ctrl_7_regs.h"
#include "psoc_etr_regs.h"
#include "psoc_cpu_pll_regs.h"

#include "dma0_qm_masks.h"
#include "mme0_qm_masks.h"
#include "tpc0_qm_masks.h"
#include "dma0_core_masks.h"
#include "tpc0_cfg_masks.h"
#include "psoc_global_conf_masks.h"

#include "nic0_qm0_regs.h"
#include "nic1_qm0_regs.h"
#include "nic2_qm0_regs.h"
#include "nic3_qm0_regs.h"
#include "nic4_qm0_regs.h"
#include "nic0_qm1_regs.h"
#include "nic1_qm1_regs.h"
#include "nic2_qm1_regs.h"
#include "nic3_qm1_regs.h"
#include "nic4_qm1_regs.h"

#include "nic0_qm0_masks.h"

#define GAUDI_ECC_MEM_SEL_OFFSET
#define GAUDI_ECC_ADDRESS_OFFSET
#define GAUDI_ECC_SYNDROME_OFFSET
#define GAUDI_ECC_MEM_INFO_CLR_OFFSET
#define GAUDI_ECC_MEM_INFO_CLR_SERR_MASK
#define GAUDI_ECC_MEM_INFO_CLR_DERR_MASK
#define GAUDI_ECC_SERR0_OFFSET
#define GAUDI_ECC_DERR0_OFFSET

#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0
#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0
#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0
#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_DATA_0
#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0
#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0
#define mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_SOB_OBJ_0
#define mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_MON_STATUS_0
#define mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_SOB_OBJ_0
#define mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_MON_STATUS_0
#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0
#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_1
#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_2047
#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0
#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0
#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_DATA_0
#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_ARM_0
#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0
#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_511

#define mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AW
#define mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AW
#define mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AW
#define mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AW
#define mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AW
#define mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AW
#define mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AW
#define mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AW

#define mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AR
#define mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AR
#define mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AR
#define mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AR
#define mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AR
#define mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AR
#define mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AR
#define mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AR

#define mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0
#define mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0
#define mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0
#define mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0
#define mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0
#define mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0
#define mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0
#define mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0

#define mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0
#define mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0
#define mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0
#define mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0
#define mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0
#define mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0
#define mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0
#define mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0

#define mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0
#define mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0
#define mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0
#define mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0
#define mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0
#define mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0
#define mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0
#define mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0

#define mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0
#define mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0
#define mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0
#define mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0
#define mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0
#define mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0
#define mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0
#define mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0

#define mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AW
#define mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AW
#define mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AW
#define mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AW
#define mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AW
#define mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AW
#define mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AW
#define mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AW

#define mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AR
#define mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AR
#define mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AR
#define mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AR
#define mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AR
#define mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AR
#define mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AR
#define mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AR

#define mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0
#define mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0
#define mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0
#define mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0
#define mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0
#define mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0
#define mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0
#define mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0

#define mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0
#define mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0
#define mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0
#define mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0
#define mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0
#define mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0
#define mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0
#define mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0

#define mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0
#define mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0
#define mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0
#define mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0
#define mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0
#define mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0
#define mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0
#define mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0

#define mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0
#define mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0
#define mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0
#define mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0
#define mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0
#define mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0
#define mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0
#define mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0

#define mmDMA_IF_W_S_DOWN_RSP_MID_WGHT_0
#define mmDMA_IF_W_S_DOWN_RSP_MID_WGHT_1

#define mmDMA_IF_E_S_DOWN_RSP_MID_WGHT_0
#define mmDMA_IF_E_S_DOWN_RSP_MID_WGHT_1

#define mmDMA_IF_W_N_DOWN_RSP_MID_WGHT_0
#define mmDMA_IF_W_N_DOWN_RSP_MID_WGHT_1

#define mmDMA_IF_E_N_DOWN_RSP_MID_WGHT_0
#define mmDMA_IF_E_N_DOWN_RSP_MID_WGHT_1

#define mmMME1_QM_GLBL_CFG0
#define mmMME1_QM_GLBL_STS0

#define mmMME0_SBAB_SB_STALL
#define mmMME0_SBAB_ARUSER0
#define mmMME0_SBAB_ARUSER1
#define mmMME0_SBAB_PROT

#define mmMME1_SBAB_SB_STALL
#define mmMME1_SBAB_ARUSER0
#define mmMME1_SBAB_ARUSER1
#define mmMME1_SBAB_PROT

#define mmMME2_SBAB_SB_STALL
#define mmMME2_SBAB_ARUSER0
#define mmMME2_SBAB_ARUSER1
#define mmMME2_SBAB_PROT

#define mmMME3_SBAB_SB_STALL
#define mmMME3_SBAB_ARUSER0
#define mmMME3_SBAB_ARUSER1
#define mmMME3_SBAB_PROT

#define mmMME0_ACC_ACC_STALL
#define mmMME0_ACC_WBC
#define mmMME0_ACC_PROT

#define mmMME1_ACC_ACC_STALL
#define mmMME1_ACC_WBC
#define mmMME1_ACC_PROT

#define mmMME2_ACC_ACC_STALL
#define mmMME2_ACC_WBC
#define mmMME2_ACC_PROT

#define mmMME3_ACC_ACC_STALL
#define mmMME3_ACC_WBC
#define mmMME3_ACC_PROT

#define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR

#define mmPSOC_EFUSE_READ
#define mmPSOC_EFUSE_DATA_0

#define mmPCIE_WRAP_MAX_OUTSTAND
#define mmPCIE_WRAP_LBW_PROT_OVR
#define mmPCIE_WRAP_HBW_DRAIN_CFG
#define mmPCIE_WRAP_LBW_DRAIN_CFG

#define mmPCIE_MSI_INTR_0

#define mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG

#define mmPCIE_AUX_FLR_CTRL
#define mmPCIE_AUX_DBI

#define mmPCIE_CORE_MSI_REQ

#define mmPSOC_PCI_PLL_NR
#define mmSRAM_W_PLL_NR
#define mmPSOC_HBM_PLL_NR
#define mmNIC0_PLL_NR
#define mmDMA_W_PLL_NR
#define mmMESH_W_PLL_NR
#define mmPSOC_MME_PLL_NR
#define mmPSOC_TPC_PLL_NR
#define mmIF_W_PLL_NR

#define mmPCIE_WRAP_RR_ELBI_RD_SEC_REG_CTRL

#endif /* ASIC_REG_GAUDI_REGS_H_ */