/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __SOUND_AK4113_H #define __SOUND_AK4113_H /* * Routines for Asahi Kasei AK4113 * Copyright (c) by Jaroslav Kysela <[email protected]>, * Copyright (c) by Pavel Hofman <[email protected]>, */ /* AK4113 registers */ /* power down */ #define AK4113_REG_PWRDN … /* format control */ #define AK4113_REG_FORMAT … /* input/output control */ #define AK4113_REG_IO0 … /* input/output control */ #define AK4113_REG_IO1 … /* interrupt0 mask */ #define AK4113_REG_INT0_MASK … /* interrupt1 mask */ #define AK4113_REG_INT1_MASK … /* DAT mask & DTS select */ #define AK4113_REG_DATDTS … /* receiver status 0 */ #define AK4113_REG_RCS0 … /* receiver status 1 */ #define AK4113_REG_RCS1 … /* receiver status 2 */ #define AK4113_REG_RCS2 … /* RX channel status byte 0 */ #define AK4113_REG_RXCSB0 … /* RX channel status byte 1 */ #define AK4113_REG_RXCSB1 … /* RX channel status byte 2 */ #define AK4113_REG_RXCSB2 … /* RX channel status byte 3 */ #define AK4113_REG_RXCSB3 … /* RX channel status byte 4 */ #define AK4113_REG_RXCSB4 … /* burst preamble Pc byte 0 */ #define AK4113_REG_Pc0 … /* burst preamble Pc byte 1 */ #define AK4113_REG_Pc1 … /* burst preamble Pd byte 0 */ #define AK4113_REG_Pd0 … /* burst preamble Pd byte 1 */ #define AK4113_REG_Pd1 … /* Q-subcode address + control */ #define AK4113_REG_QSUB_ADDR … /* Q-subcode track */ #define AK4113_REG_QSUB_TRACK … /* Q-subcode index */ #define AK4113_REG_QSUB_INDEX … /* Q-subcode minute */ #define AK4113_REG_QSUB_MINUTE … /* Q-subcode second */ #define AK4113_REG_QSUB_SECOND … /* Q-subcode frame */ #define AK4113_REG_QSUB_FRAME … /* Q-subcode zero */ #define AK4113_REG_QSUB_ZERO … /* Q-subcode absolute minute */ #define AK4113_REG_QSUB_ABSMIN … /* Q-subcode absolute second */ #define AK4113_REG_QSUB_ABSSEC … /* Q-subcode absolute frame */ #define AK4113_REG_QSUB_ABSFRM … /* sizes */ #define AK4113_REG_RXCSB_SIZE … #define AK4113_REG_QSUB_SIZE … #define AK4113_WRITABLE_REGS … /* AK4113_REG_PWRDN bits */ /* Channel Status Select */ #define AK4113_CS12 … /* Block Start & C/U Output Mode */ #define AK4113_BCU … /* Master Clock Operation Select */ #define AK4113_CM1 … /* Master Clock Operation Select */ #define AK4113_CM0 … /* Master Clock Frequency Select */ #define AK4113_OCKS1 … /* Master Clock Frequency Select */ #define AK4113_OCKS0 … /* 0 = power down, 1 = normal operation */ #define AK4113_PWN … /* 0 = reset & initialize (except thisregister), 1 = normal operation */ #define AK4113_RST … /* AK4113_REQ_FORMAT bits */ /* V/TX Output select: 0 = Validity Flag Output, 1 = TX */ #define AK4113_VTX … /* Audio Data Control */ #define AK4113_DIF2 … /* Audio Data Control */ #define AK4113_DIF1 … /* Audio Data Control */ #define AK4113_DIF0 … /* Deemphasis Autodetect Enable (1 = enable) */ #define AK4113_DEAU … /* 32kHz-48kHz Deemphasis Control */ #define AK4113_DEM1 … /* 32kHz-48kHz Deemphasis Control */ #define AK4113_DEM0 … #define AK4113_DEM_OFF … #define AK4113_DEM_44KHZ … #define AK4113_DEM_48KHZ … #define AK4113_DEM_32KHZ … /* STDO: 16-bit, right justified */ #define AK4113_DIF_16R … /* STDO: 18-bit, right justified */ #define AK4113_DIF_18R … /* STDO: 20-bit, right justified */ #define AK4113_DIF_20R … /* STDO: 24-bit, right justified */ #define AK4113_DIF_24R … /* STDO: 24-bit, left justified */ #define AK4113_DIF_24L … /* STDO: I2S */ #define AK4113_DIF_24I2S … /* STDO: 24-bit, left justified; LRCLK, BICK = Input */ #define AK4113_DIF_I24L … /* STDO: I2S; LRCLK, BICK = Input */ #define AK4113_DIF_I24I2S … /* AK4113_REG_IO0 */ /* XTL1=0,XTL0=0 -> 11.2896Mhz; XTL1=0,XTL0=1 -> 12.288Mhz */ #define AK4113_XTL1 … /* XTL1=1,XTL0=0 -> 24.576Mhz; XTL1=1,XTL0=1 -> use channel status */ #define AK4113_XTL0 … /* Block Start Signal Output: 0 = U-bit, 1 = C-bit (req. BCU = 1) */ #define AK4113_UCE … /* TX Output Enable (1 = enable) */ #define AK4113_TXE … /* Output Through Data Selector for TX pin */ #define AK4113_OPS2 … /* Output Through Data Selector for TX pin */ #define AK4113_OPS1 … /* Output Through Data Selector for TX pin */ #define AK4113_OPS0 … /* 11.2896 MHz ref. Xtal freq. */ #define AK4113_XTL_11_2896M … /* 12.288 MHz ref. Xtal freq. */ #define AK4113_XTL_12_288M … /* 24.576 MHz ref. Xtal freq. */ #define AK4113_XTL_24_576M … /* AK4113_REG_IO1 */ /* Interrupt 0 pin Hold */ #define AK4113_EFH1 … /* Interrupt 0 pin Hold */ #define AK4113_EFH0 … #define AK4113_EFH_512LRCLK … #define AK4113_EFH_1024LRCLK … #define AK4113_EFH_2048LRCLK … #define AK4113_EFH_4096LRCLK … /* PLL Lock Time: 0 = 384/fs, 1 = 1/fs */ #define AK4113_FAST … /* MCKO2 Output Select: 0 = CMx/OCKSx, 1 = Xtal */ #define AK4113_XMCK … /* MCKO2 Output Freq. Select: 0 = x1, 1 = x0.5 (req. XMCK = 1) */ #define AK4113_DIV … /* Input Recovery Data Select */ #define AK4113_IPS2 … /* Input Recovery Data Select */ #define AK4113_IPS1 … /* Input Recovery Data Select */ #define AK4113_IPS0 … #define AK4113_IPS(x) … /* AK4113_REG_INT0_MASK && AK4113_REG_INT1_MASK*/ /* mask enable for QINT bit */ #define AK4113_MQI … /* mask enable for AUTO bit */ #define AK4113_MAUT … /* mask enable for CINT bit */ #define AK4113_MCIT … /* mask enable for UNLOCK bit */ #define AK4113_MULK … /* mask enable for V bit */ #define AK4113_V … /* mask enable for STC bit */ #define AK4113_STC … /* mask enable for AUDN bit */ #define AK4113_MAN … /* mask enable for PAR bit */ #define AK4113_MPR … /* AK4113_REG_DATDTS */ /* DAT Start ID Counter */ #define AK4113_DCNT … /* DTS-CD 16-bit Sync Word Detect */ #define AK4113_DTS16 … /* DTS-CD 14-bit Sync Word Detect */ #define AK4113_DTS14 … /* mask enable for DAT bit (if 1, no INT1 effect */ #define AK4113_MDAT1 … /* mask enable for DAT bit (if 1, no INT0 effect */ #define AK4113_MDAT0 … /* AK4113_REG_RCS0 */ /* Q-subcode buffer interrupt, 0 = no change, 1 = changed */ #define AK4113_QINT … /* Non-PCM or DTS stream auto detection, 0 = no detect, 1 = detect */ #define AK4113_AUTO … /* channel status buffer interrupt, 0 = no change, 1 = change */ #define AK4113_CINT … /* PLL lock status, 0 = lock, 1 = unlock */ #define AK4113_UNLCK … /* Validity bit, 0 = valid, 1 = invalid */ #define AK4113_V … /* sampling frequency or Pre-emphasis change, 0 = no detect, 1 = detect */ #define AK4113_STC … /* audio bit output, 0 = audio, 1 = non-audio */ #define AK4113_AUDION … /* parity error or biphase error status, 0 = no error, 1 = error */ #define AK4113_PAR … /* AK4113_REG_RCS1 */ /* sampling frequency detection */ #define AK4113_FS3 … #define AK4113_FS2 … #define AK4113_FS1 … #define AK4113_FS0 … /* Pre-emphasis detect, 0 = OFF, 1 = ON */ #define AK4113_PEM … /* DAT Start ID Detect, 0 = no detect, 1 = detect */ #define AK4113_DAT … /* DTS-CD bit audio stream detect, 0 = no detect, 1 = detect */ #define AK4113_DTSCD … /* Non-PCM bit stream detection, 0 = no detect, 1 = detect */ #define AK4113_NPCM … #define AK4113_FS_8000HZ … #define AK4113_FS_11025HZ … #define AK4113_FS_16000HZ … #define AK4113_FS_22050HZ … #define AK4113_FS_24000HZ … #define AK4113_FS_32000HZ … #define AK4113_FS_44100HZ … #define AK4113_FS_48000HZ … #define AK4113_FS_64000HZ … #define AK4113_FS_88200HZ … #define AK4113_FS_96000HZ … #define AK4113_FS_176400HZ … #define AK4113_FS_192000HZ … /* AK4113_REG_RCS2 */ /* CRC for Q-subcode, 0 = no error, 1 = error */ #define AK4113_QCRC … /* CRC for channel status, 0 = no error, 1 = error */ #define AK4113_CCRC … /* flags for snd_ak4113_check_rate_and_errors() */ #define AK4113_CHECK_NO_STAT … #define AK4113_CHECK_NO_RATE … #define AK4113_CONTROLS … ak4113_write_t; ak4113_read_t; enum { … }; struct ak4113 { … }; int snd_ak4113_create(struct snd_card *card, ak4113_read_t *read, ak4113_write_t *write, const unsigned char *pgm, void *private_data, struct ak4113 **r_ak4113); void snd_ak4113_reg_write(struct ak4113 *ak4113, unsigned char reg, unsigned char mask, unsigned char val); void snd_ak4113_reinit(struct ak4113 *ak4113); int snd_ak4113_build(struct ak4113 *ak4113, struct snd_pcm_substream *capture_substream); int snd_ak4113_external_rate(struct ak4113 *ak4113); int snd_ak4113_check_rate_and_errors(struct ak4113 *ak4113, unsigned int flags); #ifdef CONFIG_PM void snd_ak4113_suspend(struct ak4113 *chip); void snd_ak4113_resume(struct ak4113 *chip); #else static inline void snd_ak4113_suspend(struct ak4113 *chip) {} static inline void snd_ak4113_resume(struct ak4113 *chip) {} #endif #endif /* __SOUND_AK4113_H */
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