/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __SOUND_CS46XX_H #define __SOUND_CS46XX_H /* * Copyright (c) by Jaroslav Kysela <[email protected]>, * Cirrus Logic, Inc. * Definitions for Cirrus Logic CS46xx chips */ #include <sound/pcm.h> #include <sound/pcm-indirect.h> #include <sound/rawmidi.h> #include <sound/ac97_codec.h> #include "cs46xx_dsp_spos.h" /* * Direct registers */ /* * The following define the offsets of the registers accessed via base address * register zero on the CS46xx part. */ #define BA0_HISR … #define BA0_HSR0 … #define BA0_HICR … #define BA0_DMSR … #define BA0_HSAR … #define BA0_HDAR … #define BA0_HDMR … #define BA0_HDCR … #define BA0_PFMC … #define BA0_PFCV1 … #define BA0_PFCV2 … #define BA0_PCICFG00 … #define BA0_PCICFG04 … #define BA0_PCICFG08 … #define BA0_PCICFG0C … #define BA0_PCICFG10 … #define BA0_PCICFG14 … #define BA0_PCICFG18 … #define BA0_PCICFG1C … #define BA0_PCICFG20 … #define BA0_PCICFG24 … #define BA0_PCICFG28 … #define BA0_PCICFG2C … #define BA0_PCICFG30 … #define BA0_PCICFG34 … #define BA0_PCICFG38 … #define BA0_PCICFG3C … #define BA0_CLKCR1 … #define BA0_CLKCR2 … #define BA0_PLLM … #define BA0_PLLCC … #define BA0_FRR … #define BA0_CFL1 … #define BA0_CFL2 … #define BA0_SERMC1 … #define BA0_SERMC2 … #define BA0_SERC1 … #define BA0_SERC2 … #define BA0_SERC3 … #define BA0_SERC4 … #define BA0_SERC5 … #define BA0_SERBSP … #define BA0_SERBST … #define BA0_SERBCM … #define BA0_SERBAD … #define BA0_SERBCF … #define BA0_SERBWP … #define BA0_SERBRP … #ifndef NO_CS4612 #define BA0_ASER_FADDR … #endif #define BA0_ACCTL … #define BA0_ACSTS … #define BA0_ACOSV … #define BA0_ACCAD … #define BA0_ACCDA … #define BA0_ACISV … #define BA0_ACSAD … #define BA0_ACSDA … #define BA0_JSPT … #define BA0_JSCTL … #define BA0_JSC1 … #define BA0_JSC2 … #define BA0_MIDCR … #define BA0_MIDSR … #define BA0_MIDWP … #define BA0_MIDRP … #define BA0_JSIO … #ifndef NO_CS4612 #define BA0_ASER_MASTER … #endif #define BA0_CFGI … #define BA0_SSVID … #define BA0_GPIOR … #ifndef NO_CS4612 #define BA0_EGPIODR … #define BA0_EGPIOPTR … #define BA0_EGPIOTR … #define BA0_EGPIOWR … #define BA0_EGPIOSR … #define BA0_SERC6 … #define BA0_SERC7 … #define BA0_SERACC … #define BA0_ACCTL2 … #define BA0_ACSTS2 … #define BA0_ACOSV2 … #define BA0_ACCAD2 … #define BA0_ACCDA2 … #define BA0_ACISV2 … #define BA0_ACSAD2 … #define BA0_ACSDA2 … #define BA0_IOTAC0 … #define BA0_IOTAC1 … #define BA0_IOTAC2 … #define BA0_IOTAC3 … #define BA0_IOTAC4 … #define BA0_IOTAC5 … #define BA0_IOTAC6 … #define BA0_IOTAC7 … #define BA0_IOTAC8 … #define BA0_IOTAC9 … #define BA0_IOTAC10 … #define BA0_IOTAC11 … #define BA0_IOTFR0 … #define BA0_IOTFR1 … #define BA0_IOTFR2 … #define BA0_IOTFR3 … #define BA0_IOTFR4 … #define BA0_IOTFR5 … #define BA0_IOTFR6 … #define BA0_IOTFR7 … #define BA0_IOTFIFO … #define BA0_IOTRRD … #define BA0_IOTFP … #define BA0_IOTCR … #define BA0_DPCID … #define BA0_DPCIA … #define BA0_DPCIC … #define BA0_PCPCIR … #define BA0_PCPCIG … #define BA0_PCPCIEN … #define BA0_EPCIPMC … #endif /* * The following define the offsets of the registers and memories accessed via * base address register one on the CS46xx part. */ #define BA1_SP_DMEM0 … #define BA1_SP_DMEM1 … #define BA1_SP_PMEM … #define BA1_SP_REG … #define BA1_SPCR … #define BA1_DREG … #define BA1_DSRWP … #define BA1_TWPR … #define BA1_SPWR … #define BA1_SPIR … #define BA1_FGR1 … #define BA1_SPCS … #define BA1_SDSR … #define BA1_FRMT … #define BA1_FRCC … #define BA1_FRSC … #define BA1_OMNI_MEM … /* * The following defines are for the flags in the host interrupt status * register. */ #define HISR_VC_MASK … #define HISR_VC0 … #define HISR_VC1 … #define HISR_VC2 … #define HISR_VC3 … #define HISR_VC4 … #define HISR_VC5 … #define HISR_VC6 … #define HISR_VC7 … #define HISR_VC8 … #define HISR_VC9 … #define HISR_VC10 … #define HISR_VC11 … #define HISR_VC12 … #define HISR_VC13 … #define HISR_VC14 … #define HISR_VC15 … #define HISR_INT0 … #define HISR_INT1 … #define HISR_DMAI … #define HISR_FROVR … #define HISR_MIDI … #ifdef NO_CS4612 #define HISR_RESERVED … #else #define HISR_SBINT … #define HISR_RESERVED … #endif #define HISR_H0P … #define HISR_INTENA … /* * The following defines are for the flags in the host signal register 0. */ #define HSR0_VC_MASK … #define HSR0_VC16 … #define HSR0_VC17 … #define HSR0_VC18 … #define HSR0_VC19 … #define HSR0_VC20 … #define HSR0_VC21 … #define HSR0_VC22 … #define HSR0_VC23 … #define HSR0_VC24 … #define HSR0_VC25 … #define HSR0_VC26 … #define HSR0_VC27 … #define HSR0_VC28 … #define HSR0_VC29 … #define HSR0_VC30 … #define HSR0_VC31 … #define HSR0_VC32 … #define HSR0_VC33 … #define HSR0_VC34 … #define HSR0_VC35 … #define HSR0_VC36 … #define HSR0_VC37 … #define HSR0_VC38 … #define HSR0_VC39 … #define HSR0_VC40 … #define HSR0_VC41 … #define HSR0_VC42 … #define HSR0_VC43 … #define HSR0_VC44 … #define HSR0_VC45 … #define HSR0_VC46 … #define HSR0_VC47 … /* * The following defines are for the flags in the host interrupt control * register. */ #define HICR_IEV … #define HICR_CHGM … /* * The following defines are for the flags in the DMA status register. */ #define DMSR_HP … #define DMSR_HR … #define DMSR_SP … #define DMSR_SR … /* * The following defines are for the flags in the host DMA source address * register. */ #define HSAR_HOST_ADDR_MASK … #define HSAR_DSP_ADDR_MASK … #define HSAR_MEMID_MASK … #define HSAR_MEMID_SP_DMEM0 … #define HSAR_MEMID_SP_DMEM1 … #define HSAR_MEMID_SP_PMEM … #define HSAR_MEMID_SP_DEBUG … #define HSAR_MEMID_OMNI_MEM … #define HSAR_END … #define HSAR_ERR … /* * The following defines are for the flags in the host DMA destination address * register. */ #define HDAR_HOST_ADDR_MASK … #define HDAR_DSP_ADDR_MASK … #define HDAR_MEMID_MASK … #define HDAR_MEMID_SP_DMEM0 … #define HDAR_MEMID_SP_DMEM1 … #define HDAR_MEMID_SP_PMEM … #define HDAR_MEMID_SP_DEBUG … #define HDAR_MEMID_OMNI_MEM … #define HDAR_END … #define HDAR_ERR … /* * The following defines are for the flags in the host DMA control register. */ #define HDMR_AC_MASK … #define HDMR_AC_8_16 … #define HDMR_AC_M_S … #define HDMR_AC_B_L … #define HDMR_AC_S_U … /* * The following defines are for the flags in the host DMA control register. */ #define HDCR_COUNT_MASK … #define HDCR_DONE … #define HDCR_OPT … #define HDCR_WBD … #define HDCR_WBS … #define HDCR_DMS_MASK … #define HDCR_DMS_LINEAR … #define HDCR_DMS_16_DWORDS … #define HDCR_DMS_32_DWORDS … #define HDCR_DMS_64_DWORDS … #define HDCR_DMS_128_DWORDS … #define HDCR_DMS_256_DWORDS … #define HDCR_DMS_512_DWORDS … #define HDCR_DMS_1024_DWORDS … #define HDCR_DH … #define HDCR_SMS_MASK … #define HDCR_SMS_LINEAR … #define HDCR_SMS_16_DWORDS … #define HDCR_SMS_32_DWORDS … #define HDCR_SMS_64_DWORDS … #define HDCR_SMS_128_DWORDS … #define HDCR_SMS_256_DWORDS … #define HDCR_SMS_512_DWORDS … #define HDCR_SMS_1024_DWORDS … #define HDCR_SH … #define HDCR_COUNT_SHIFT … /* * The following defines are for the flags in the performance monitor control * register. */ #define PFMC_C1SS_MASK … #define PFMC_C1EV … #define PFMC_C1RS … #define PFMC_C2SS_MASK … #define PFMC_C2EV … #define PFMC_C2RS … #define PFMC_C1SS_SHIFT … #define PFMC_C2SS_SHIFT … #define PFMC_BUS_GRANT … #define PFMC_GRANT_AFTER_REQ … #define PFMC_TRANSACTION … #define PFMC_DWORD_TRANSFER … #define PFMC_SLAVE_READ … #define PFMC_SLAVE_WRITE … #define PFMC_PREEMPTION … #define PFMC_DISCONNECT_RETRY … #define PFMC_INTERRUPT … #define PFMC_BUS_OWNERSHIP … #define PFMC_TRANSACTION_LAG … #define PFMC_PCI_CLOCK … #define PFMC_SERIAL_CLOCK … #define PFMC_SP_CLOCK … /* * The following defines are for the flags in the performance counter value 1 * register. */ #define PFCV1_PC1V_MASK … #define PFCV1_PC1V_SHIFT … /* * The following defines are for the flags in the performance counter value 2 * register. */ #define PFCV2_PC2V_MASK … #define PFCV2_PC2V_SHIFT … /* * The following defines are for the flags in the clock control register 1. */ #define CLKCR1_OSCS … #define CLKCR1_OSCP … #define CLKCR1_PLLSS_MASK … #define CLKCR1_PLLSS_SERIAL … #define CLKCR1_PLLSS_CRYSTAL … #define CLKCR1_PLLSS_PCI … #define CLKCR1_PLLSS_RESERVED … #define CLKCR1_PLLP … #define CLKCR1_SWCE … #define CLKCR1_PLLOS … /* * The following defines are for the flags in the clock control register 2. */ #define CLKCR2_PDIVS_MASK … #define CLKCR2_PDIVS_1 … #define CLKCR2_PDIVS_2 … #define CLKCR2_PDIVS_4 … #define CLKCR2_PDIVS_7 … #define CLKCR2_PDIVS_8 … #define CLKCR2_PDIVS_16 … /* * The following defines are for the flags in the PLL multiplier register. */ #define PLLM_MASK … #define PLLM_SHIFT … /* * The following defines are for the flags in the PLL capacitor coefficient * register. */ #define PLLCC_CDR_MASK … #ifndef NO_CS4610 #define PLLCC_CDR_240_350_MHZ … #define PLLCC_CDR_184_265_MHZ … #define PLLCC_CDR_144_205_MHZ … #define PLLCC_CDR_111_160_MHZ … #define PLLCC_CDR_87_123_MHZ … #define PLLCC_CDR_67_96_MHZ … #define PLLCC_CDR_52_74_MHZ … #define PLLCC_CDR_45_58_MHZ … #endif #ifndef NO_CS4612 #define PLLCC_CDR_271_398_MHZ … #define PLLCC_CDR_227_330_MHZ … #define PLLCC_CDR_167_239_MHZ … #define PLLCC_CDR_150_215_MHZ … #define PLLCC_CDR_107_154_MHZ … #define PLLCC_CDR_98_140_MHZ … #define PLLCC_CDR_73_104_MHZ … #define PLLCC_CDR_63_90_MHZ … #endif #define PLLCC_LPF_MASK … #ifndef NO_CS4610 #define PLLCC_LPF_23850_60000_KHZ … #define PLLCC_LPF_7960_26290_KHZ … #define PLLCC_LPF_4160_10980_KHZ … #define PLLCC_LPF_1740_4580_KHZ … #define PLLCC_LPF_724_1910_KHZ … #define PLLCC_LPF_317_798_KHZ … #endif #ifndef NO_CS4612 #define PLLCC_LPF_25580_64530_KHZ … #define PLLCC_LPF_14360_37270_KHZ … #define PLLCC_LPF_6100_16020_KHZ … #define PLLCC_LPF_2540_6690_KHZ … #define PLLCC_LPF_1050_2780_KHZ … #define PLLCC_LPF_450_1160_KHZ … #endif /* * The following defines are for the flags in the feature reporting register. */ #define FRR_FAB_MASK … #define FRR_MASK_MASK … #ifdef NO_CS4612 #define FRR_CFOP_MASK … #else #define FRR_CFOP_MASK … #endif #define FRR_CFOP_NOT_DVD … #define FRR_CFOP_A3D … #define FRR_CFOP_128_PIN … #ifndef NO_CS4612 #define FRR_CFOP_CS4280 … #endif #define FRR_FAB_SHIFT … #define FRR_MASK_SHIFT … #define FRR_CFOP_SHIFT … /* * The following defines are for the flags in the configuration load 1 * register. */ #define CFL1_CLOCK_SOURCE_MASK … #define CFL1_CLOCK_SOURCE_CS423X … #define CFL1_CLOCK_SOURCE_AC97 … #define CFL1_CLOCK_SOURCE_CRYSTAL … #define CFL1_CLOCK_SOURCE_DUAL_AC97 … #define CFL1_VALID_DATA_MASK … /* * The following defines are for the flags in the configuration load 2 * register. */ #define CFL2_VALID_DATA_MASK … /* * The following defines are for the flags in the serial port master control * register 1. */ #define SERMC1_MSPE … #define SERMC1_PTC_MASK … #define SERMC1_PTC_CS423X … #define SERMC1_PTC_AC97 … #define SERMC1_PTC_DAC … #define SERMC1_PLB … #define SERMC1_XLB … /* * The following defines are for the flags in the serial port master control * register 2. */ #define SERMC2_LROE … #define SERMC2_MCOE … #define SERMC2_MCDIV … /* * The following defines are for the flags in the serial port 1 configuration * register. */ #define SERC1_SO1EN … #define SERC1_SO1F_MASK … #define SERC1_SO1F_CS423X … #define SERC1_SO1F_AC97 … #define SERC1_SO1F_DAC … #define SERC1_SO1F_SPDIF … /* * The following defines are for the flags in the serial port 2 configuration * register. */ #define SERC2_SI1EN … #define SERC2_SI1F_MASK … #define SERC2_SI1F_CS423X … #define SERC2_SI1F_AC97 … #define SERC2_SI1F_ADC … #define SERC2_SI1F_SPDIF … /* * The following defines are for the flags in the serial port 3 configuration * register. */ #define SERC3_SO2EN … #define SERC3_SO2F_MASK … #define SERC3_SO2F_DAC … #define SERC3_SO2F_SPDIF … /* * The following defines are for the flags in the serial port 4 configuration * register. */ #define SERC4_SO3EN … #define SERC4_SO3F_MASK … #define SERC4_SO3F_DAC … #define SERC4_SO3F_SPDIF … /* * The following defines are for the flags in the serial port 5 configuration * register. */ #define SERC5_SI2EN … #define SERC5_SI2F_MASK … #define SERC5_SI2F_ADC … #define SERC5_SI2F_SPDIF … /* * The following defines are for the flags in the serial port backdoor sample * pointer register. */ #define SERBSP_FSP_MASK … #define SERBSP_FSP_SHIFT … /* * The following defines are for the flags in the serial port backdoor status * register. */ #define SERBST_RRDY … #define SERBST_WBSY … /* * The following defines are for the flags in the serial port backdoor command * register. */ #define SERBCM_RDC … #define SERBCM_WRC … /* * The following defines are for the flags in the serial port backdoor address * register. */ #ifdef NO_CS4612 #define SERBAD_FAD_MASK … #else #define SERBAD_FAD_MASK … #endif #define SERBAD_FAD_SHIFT … /* * The following defines are for the flags in the serial port backdoor * configuration register. */ #define SERBCF_HBP … /* * The following defines are for the flags in the serial port backdoor write * port register. */ #define SERBWP_FWD_MASK … #define SERBWP_FWD_SHIFT … /* * The following defines are for the flags in the serial port backdoor read * port register. */ #define SERBRP_FRD_MASK … #define SERBRP_FRD_SHIFT … /* * The following defines are for the flags in the async FIFO address register. */ #ifndef NO_CS4612 #define ASER_FADDR_A1_MASK … #define ASER_FADDR_EN1 … #define ASER_FADDR_A2_MASK … #define ASER_FADDR_EN2 … #define ASER_FADDR_A1_SHIFT … #define ASER_FADDR_A2_SHIFT … #endif /* * The following defines are for the flags in the AC97 control register. */ #define ACCTL_RSTN … #define ACCTL_ESYN … #define ACCTL_VFRM … #define ACCTL_DCV … #define ACCTL_CRW … #define ACCTL_ASYN … #ifndef NO_CS4612 #define ACCTL_TC … #endif /* * The following defines are for the flags in the AC97 status register. */ #define ACSTS_CRDY … #define ACSTS_VSTS … #ifndef NO_CS4612 #define ACSTS_WKUP … #endif /* * The following defines are for the flags in the AC97 output slot valid * register. */ #define ACOSV_SLV3 … #define ACOSV_SLV4 … #define ACOSV_SLV5 … #define ACOSV_SLV6 … #define ACOSV_SLV7 … #define ACOSV_SLV8 … #define ACOSV_SLV9 … #define ACOSV_SLV10 … #define ACOSV_SLV11 … #define ACOSV_SLV12 … /* * The following defines are for the flags in the AC97 command address * register. */ #define ACCAD_CI_MASK … #define ACCAD_CI_SHIFT … /* * The following defines are for the flags in the AC97 command data register. */ #define ACCDA_CD_MASK … #define ACCDA_CD_SHIFT … /* * The following defines are for the flags in the AC97 input slot valid * register. */ #define ACISV_ISV3 … #define ACISV_ISV4 … #define ACISV_ISV5 … #define ACISV_ISV6 … #define ACISV_ISV7 … #define ACISV_ISV8 … #define ACISV_ISV9 … #define ACISV_ISV10 … #define ACISV_ISV11 … #define ACISV_ISV12 … /* * The following defines are for the flags in the AC97 status address * register. */ #define ACSAD_SI_MASK … #define ACSAD_SI_SHIFT … /* * The following defines are for the flags in the AC97 status data register. */ #define ACSDA_SD_MASK … #define ACSDA_SD_SHIFT … /* * The following defines are for the flags in the joystick poll/trigger * register. */ #define JSPT_CAX … #define JSPT_CAY … #define JSPT_CBX … #define JSPT_CBY … #define JSPT_BA1 … #define JSPT_BA2 … #define JSPT_BB1 … #define JSPT_BB2 … /* * The following defines are for the flags in the joystick control register. */ #define JSCTL_SP_MASK … #define JSCTL_SP_SLOW … #define JSCTL_SP_MEDIUM_SLOW … #define JSCTL_SP_MEDIUM_FAST … #define JSCTL_SP_FAST … #define JSCTL_ARE … /* * The following defines are for the flags in the joystick coordinate pair 1 * readback register. */ #define JSC1_Y1V_MASK … #define JSC1_X1V_MASK … #define JSC1_Y1V_SHIFT … #define JSC1_X1V_SHIFT … /* * The following defines are for the flags in the joystick coordinate pair 2 * readback register. */ #define JSC2_Y2V_MASK … #define JSC2_X2V_MASK … #define JSC2_Y2V_SHIFT … #define JSC2_X2V_SHIFT … /* * The following defines are for the flags in the MIDI control register. */ #define MIDCR_TXE … #define MIDCR_RXE … #define MIDCR_RIE … #define MIDCR_TIE … #define MIDCR_MLB … #define MIDCR_MRST … /* * The following defines are for the flags in the MIDI status register. */ #define MIDSR_TBF … #define MIDSR_RBE … /* * The following defines are for the flags in the MIDI write port register. */ #define MIDWP_MWD_MASK … #define MIDWP_MWD_SHIFT … /* * The following defines are for the flags in the MIDI read port register. */ #define MIDRP_MRD_MASK … #define MIDRP_MRD_SHIFT … /* * The following defines are for the flags in the joystick GPIO register. */ #define JSIO_DAX … #define JSIO_DAY … #define JSIO_DBX … #define JSIO_DBY … #define JSIO_AXOE … #define JSIO_AYOE … #define JSIO_BXOE … #define JSIO_BYOE … /* * The following defines are for the flags in the master async/sync serial * port enable register. */ #ifndef NO_CS4612 #define ASER_MASTER_ME … #endif /* * The following defines are for the flags in the configuration interface * register. */ #define CFGI_CLK … #define CFGI_DOUT … #define CFGI_DIN_EEN … #define CFGI_EELD … /* * The following defines are for the flags in the subsystem ID and vendor ID * register. */ #define SSVID_VID_MASK … #define SSVID_SID_MASK … #define SSVID_VID_SHIFT … #define SSVID_SID_SHIFT … /* * The following defines are for the flags in the GPIO pin interface register. */ #define GPIOR_VOLDN … #define GPIOR_VOLUP … #define GPIOR_SI2D … #define GPIOR_SI2OE … /* * The following defines are for the flags in the extended GPIO pin direction * register. */ #ifndef NO_CS4612 #define EGPIODR_GPOE0 … #define EGPIODR_GPOE1 … #define EGPIODR_GPOE2 … #define EGPIODR_GPOE3 … #define EGPIODR_GPOE4 … #define EGPIODR_GPOE5 … #define EGPIODR_GPOE6 … #define EGPIODR_GPOE7 … #define EGPIODR_GPOE8 … #endif /* * The following defines are for the flags in the extended GPIO pin polarity/ * type register. */ #ifndef NO_CS4612 #define EGPIOPTR_GPPT0 … #define EGPIOPTR_GPPT1 … #define EGPIOPTR_GPPT2 … #define EGPIOPTR_GPPT3 … #define EGPIOPTR_GPPT4 … #define EGPIOPTR_GPPT5 … #define EGPIOPTR_GPPT6 … #define EGPIOPTR_GPPT7 … #define EGPIOPTR_GPPT8 … #endif /* * The following defines are for the flags in the extended GPIO pin sticky * register. */ #ifndef NO_CS4612 #define EGPIOTR_GPS0 … #define EGPIOTR_GPS1 … #define EGPIOTR_GPS2 … #define EGPIOTR_GPS3 … #define EGPIOTR_GPS4 … #define EGPIOTR_GPS5 … #define EGPIOTR_GPS6 … #define EGPIOTR_GPS7 … #define EGPIOTR_GPS8 … #endif /* * The following defines are for the flags in the extended GPIO ping wakeup * register. */ #ifndef NO_CS4612 #define EGPIOWR_GPW0 … #define EGPIOWR_GPW1 … #define EGPIOWR_GPW2 … #define EGPIOWR_GPW3 … #define EGPIOWR_GPW4 … #define EGPIOWR_GPW5 … #define EGPIOWR_GPW6 … #define EGPIOWR_GPW7 … #define EGPIOWR_GPW8 … #endif /* * The following defines are for the flags in the extended GPIO pin status * register. */ #ifndef NO_CS4612 #define EGPIOSR_GPS0 … #define EGPIOSR_GPS1 … #define EGPIOSR_GPS2 … #define EGPIOSR_GPS3 … #define EGPIOSR_GPS4 … #define EGPIOSR_GPS5 … #define EGPIOSR_GPS6 … #define EGPIOSR_GPS7 … #define EGPIOSR_GPS8 … #endif /* * The following defines are for the flags in the serial port 6 configuration * register. */ #ifndef NO_CS4612 #define SERC6_ASDO2EN … #endif /* * The following defines are for the flags in the serial port 7 configuration * register. */ #ifndef NO_CS4612 #define SERC7_ASDI2EN … #define SERC7_POSILB … #define SERC7_SIPOLB … #define SERC7_SOSILB … #define SERC7_SISOLB … #endif /* * The following defines are for the flags in the serial port AC link * configuration register. */ #ifndef NO_CS4612 #define SERACC_CHIP_TYPE_MASK … #define SERACC_CHIP_TYPE_1_03 … #define SERACC_CHIP_TYPE_2_0 … #define SERACC_TWO_CODECS … #define SERACC_MDM … #define SERACC_HSP … #define SERACC_ODT … #endif /* * The following defines are for the flags in the AC97 control register 2. */ #ifndef NO_CS4612 #define ACCTL2_RSTN … #define ACCTL2_ESYN … #define ACCTL2_VFRM … #define ACCTL2_DCV … #define ACCTL2_CRW … #define ACCTL2_ASYN … #endif /* * The following defines are for the flags in the AC97 status register 2. */ #ifndef NO_CS4612 #define ACSTS2_CRDY … #define ACSTS2_VSTS … #endif /* * The following defines are for the flags in the AC97 output slot valid * register 2. */ #ifndef NO_CS4612 #define ACOSV2_SLV3 … #define ACOSV2_SLV4 … #define ACOSV2_SLV5 … #define ACOSV2_SLV6 … #define ACOSV2_SLV7 … #define ACOSV2_SLV8 … #define ACOSV2_SLV9 … #define ACOSV2_SLV10 … #define ACOSV2_SLV11 … #define ACOSV2_SLV12 … #endif /* * The following defines are for the flags in the AC97 command address * register 2. */ #ifndef NO_CS4612 #define ACCAD2_CI_MASK … #define ACCAD2_CI_SHIFT … #endif /* * The following defines are for the flags in the AC97 command data register * 2. */ #ifndef NO_CS4612 #define ACCDA2_CD_MASK … #define ACCDA2_CD_SHIFT … #endif /* * The following defines are for the flags in the AC97 input slot valid * register 2. */ #ifndef NO_CS4612 #define ACISV2_ISV3 … #define ACISV2_ISV4 … #define ACISV2_ISV5 … #define ACISV2_ISV6 … #define ACISV2_ISV7 … #define ACISV2_ISV8 … #define ACISV2_ISV9 … #define ACISV2_ISV10 … #define ACISV2_ISV11 … #define ACISV2_ISV12 … #endif /* * The following defines are for the flags in the AC97 status address * register 2. */ #ifndef NO_CS4612 #define ACSAD2_SI_MASK … #define ACSAD2_SI_SHIFT … #endif /* * The following defines are for the flags in the AC97 status data register 2. */ #ifndef NO_CS4612 #define ACSDA2_SD_MASK … #define ACSDA2_SD_SHIFT … #endif /* * The following defines are for the flags in the I/O trap address and control * registers (all 12). */ #ifndef NO_CS4612 #define IOTAC_SA_MASK … #define IOTAC_MSK_MASK … #define IOTAC_IODC_MASK … #define IOTAC_IODC_16_BIT … #define IOTAC_IODC_10_BIT … #define IOTAC_IODC_12_BIT … #define IOTAC_WSPI … #define IOTAC_RSPI … #define IOTAC_WSE … #define IOTAC_WE … #define IOTAC_RE … #define IOTAC_SA_SHIFT … #define IOTAC_MSK_SHIFT … #endif /* * The following defines are for the flags in the I/O trap fast read registers * (all 8). */ #ifndef NO_CS4612 #define IOTFR_D_MASK … #define IOTFR_A_MASK … #define IOTFR_R_MASK … #define IOTFR_ALL … #define IOTFR_VL … #define IOTFR_D_SHIFT … #define IOTFR_A_SHIFT … #define IOTFR_R_SHIFT … #endif /* * The following defines are for the flags in the I/O trap FIFO register. */ #ifndef NO_CS4612 #define IOTFIFO_BA_MASK … #define IOTFIFO_S_MASK … #define IOTFIFO_OF … #define IOTFIFO_SPIOF … #define IOTFIFO_BA_SHIFT … #define IOTFIFO_S_SHIFT … #endif /* * The following defines are for the flags in the I/O trap retry read data * register. */ #ifndef NO_CS4612 #define IOTRRD_D_MASK … #define IOTRRD_RDV … #define IOTRRD_D_SHIFT … #endif /* * The following defines are for the flags in the I/O trap FIFO pointer * register. */ #ifndef NO_CS4612 #define IOTFP_CA_MASK … #define IOTFP_PA_MASK … #define IOTFP_CA_SHIFT … #define IOTFP_PA_SHIFT … #endif /* * The following defines are for the flags in the I/O trap control register. */ #ifndef NO_CS4612 #define IOTCR_ITD … #define IOTCR_HRV … #define IOTCR_SRV … #define IOTCR_DTI … #define IOTCR_DFI … #define IOTCR_DDP … #define IOTCR_JTE … #define IOTCR_PPE … #endif /* * The following defines are for the flags in the direct PCI data register. */ #ifndef NO_CS4612 #define DPCID_D_MASK … #define DPCID_D_SHIFT … #endif /* * The following defines are for the flags in the direct PCI address register. */ #ifndef NO_CS4612 #define DPCIA_A_MASK … #define DPCIA_A_SHIFT … #endif /* * The following defines are for the flags in the direct PCI command register. */ #ifndef NO_CS4612 #define DPCIC_C_MASK … #define DPCIC_C_IOREAD … #define DPCIC_C_IOWRITE … #define DPCIC_BE_MASK … #endif /* * The following defines are for the flags in the PC/PCI request register. */ #ifndef NO_CS4612 #define PCPCIR_RDC_MASK … #define PCPCIR_C_MASK … #define PCPCIR_REQ … #define PCPCIR_RDC_SHIFT … #define PCPCIR_C_SHIFT … #endif /* * The following defines are for the flags in the PC/PCI grant register. */ #ifndef NO_CS4612 #define PCPCIG_GDC_MASK … #define PCPCIG_VL … #define PCPCIG_GDC_SHIFT … #endif /* * The following defines are for the flags in the PC/PCI master enable * register. */ #ifndef NO_CS4612 #define PCPCIEN_EN … #endif /* * The following defines are for the flags in the extended PCI power * management control register. */ #ifndef NO_CS4612 #define EPCIPMC_GWU … #define EPCIPMC_FSPC … #endif /* * The following defines are for the flags in the SP control register. */ #define SPCR_RUN … #define SPCR_STPFR … #define SPCR_RUNFR … #define SPCR_TICK … #define SPCR_DRQEN … #define SPCR_RSTSP … #define SPCR_OREN … #ifndef NO_CS4612 #define SPCR_PCIINT … #define SPCR_OINTD … #define SPCR_CRE … #endif /* * The following defines are for the flags in the debug index register. */ #define DREG_REGID_MASK … #define DREG_DEBUG … #define DREG_RGBK_MASK … #define DREG_TRAP … #if !defined(NO_CS4612) #if !defined(NO_CS4615) #define DREG_TRAPX … #endif #endif #define DREG_REGID_SHIFT … #define DREG_RGBK_SHIFT … #define DREG_RGBK_REGID_MASK … #define DREG_REGID_R0 … #define DREG_REGID_R1 … #define DREG_REGID_R2 … #define DREG_REGID_R3 … #define DREG_REGID_R4 … #define DREG_REGID_R5 … #define DREG_REGID_R6 … #define DREG_REGID_R7 … #define DREG_REGID_R8 … #define DREG_REGID_R9 … #define DREG_REGID_RA … #define DREG_REGID_RB … #define DREG_REGID_RC … #define DREG_REGID_RD … #define DREG_REGID_RE … #define DREG_REGID_RF … #define DREG_REGID_RA_BUS_LOW … #define DREG_REGID_RA_BUS_HIGH … #define DREG_REGID_YBUS_LOW … #define DREG_REGID_YBUS_HIGH … #define DREG_REGID_TRAP_0 … #define DREG_REGID_TRAP_1 … #define DREG_REGID_TRAP_2 … #define DREG_REGID_TRAP_3 … #define DREG_REGID_TRAP_4 … #define DREG_REGID_TRAP_5 … #define DREG_REGID_TRAP_6 … #define DREG_REGID_TRAP_7 … #define DREG_REGID_INDIRECT_ADDRESS … #define DREG_REGID_TOP_OF_STACK … #if !defined(NO_CS4612) #if !defined(NO_CS4615) #define DREG_REGID_TRAP_8 … #define DREG_REGID_TRAP_9 … #define DREG_REGID_TRAP_10 … #define DREG_REGID_TRAP_11 … #define DREG_REGID_TRAP_12 … #define DREG_REGID_TRAP_13 … #define DREG_REGID_TRAP_14 … #define DREG_REGID_TRAP_15 … #define DREG_REGID_TRAP_16 … #define DREG_REGID_TRAP_17 … #define DREG_REGID_TRAP_18 … #define DREG_REGID_TRAP_19 … #define DREG_REGID_TRAP_20 … #define DREG_REGID_TRAP_21 … #define DREG_REGID_TRAP_22 … #define DREG_REGID_TRAP_23 … #endif #endif #define DREG_REGID_RSA0_LOW … #define DREG_REGID_RSA0_HIGH … #define DREG_REGID_RSA1_LOW … #define DREG_REGID_RSA1_HIGH … #define DREG_REGID_RSA2 … #define DREG_REGID_RSA3 … #define DREG_REGID_RSI0_LOW … #define DREG_REGID_RSI0_HIGH … #define DREG_REGID_RSI1 … #define DREG_REGID_RSI2 … #define DREG_REGID_SAGUSTATUS … #define DREG_REGID_RSCONFIG01_LOW … #define DREG_REGID_RSCONFIG01_HIGH … #define DREG_REGID_RSCONFIG23_LOW … #define DREG_REGID_RSCONFIG23_HIGH … #define DREG_REGID_RSDMA01E … #define DREG_REGID_RSDMA23E … #define DREG_REGID_RSD0_LOW … #define DREG_REGID_RSD0_HIGH … #define DREG_REGID_RSD1_LOW … #define DREG_REGID_RSD1_HIGH … #define DREG_REGID_RSD2_LOW … #define DREG_REGID_RSD2_HIGH … #define DREG_REGID_RSD3_LOW … #define DREG_REGID_RSD3_HIGH … #define DREG_REGID_SRAR_HIGH … #define DREG_REGID_SRAR_LOW … #define DREG_REGID_DMA_STATE … #define DREG_REGID_CURRENT_DMA_STREAM … #define DREG_REGID_NEXT_DMA_STREAM … #define DREG_REGID_CPU_STATUS … #define DREG_REGID_MAC_MODE … #define DREG_REGID_STACK_AND_REPEAT … #define DREG_REGID_INDEX0 … #define DREG_REGID_INDEX1 … #define DREG_REGID_DMA_STATE_0_3 … #define DREG_REGID_DMA_STATE_4_7 … #define DREG_REGID_DMA_STATE_8_11 … #define DREG_REGID_DMA_STATE_12_15 … #define DREG_REGID_DMA_STATE_16_19 … #define DREG_REGID_DMA_STATE_20_23 … #define DREG_REGID_DMA_STATE_24_27 … #define DREG_REGID_DMA_STATE_28_31 … #define DREG_REGID_DMA_STATE_32_35 … #define DREG_REGID_DMA_STATE_36_39 … #define DREG_REGID_DMA_STATE_40_43 … #define DREG_REGID_DMA_STATE_44_47 … #define DREG_REGID_DMA_STATE_48_51 … #define DREG_REGID_DMA_STATE_52_55 … #define DREG_REGID_DMA_STATE_56_59 … #define DREG_REGID_DMA_STATE_60_63 … #define DREG_REGID_DMA_STATE_64_67 … #define DREG_REGID_DMA_STATE_68_71 … #define DREG_REGID_DMA_STATE_72_75 … #define DREG_REGID_DMA_STATE_76_79 … #define DREG_REGID_DMA_STATE_80_83 … #define DREG_REGID_DMA_STATE_84_87 … #define DREG_REGID_DMA_STATE_88_91 … #define DREG_REGID_DMA_STATE_92_95 … #define DREG_REGID_TRAP_SELECT … #define DREG_REGID_TRAP_WRITE_0 … #define DREG_REGID_TRAP_WRITE_1 … #define DREG_REGID_TRAP_WRITE_2 … #define DREG_REGID_TRAP_WRITE_3 … #define DREG_REGID_TRAP_WRITE_4 … #define DREG_REGID_TRAP_WRITE_5 … #define DREG_REGID_TRAP_WRITE_6 … #define DREG_REGID_TRAP_WRITE_7 … #if !defined(NO_CS4612) #if !defined(NO_CS4615) #define DREG_REGID_TRAP_WRITE_8 … #define DREG_REGID_TRAP_WRITE_9 … #define DREG_REGID_TRAP_WRITE_10 … #define DREG_REGID_TRAP_WRITE_11 … #define DREG_REGID_TRAP_WRITE_12 … #define DREG_REGID_TRAP_WRITE_13 … #define DREG_REGID_TRAP_WRITE_14 … #define DREG_REGID_TRAP_WRITE_15 … #define DREG_REGID_TRAP_WRITE_16 … #define DREG_REGID_TRAP_WRITE_17 … #define DREG_REGID_TRAP_WRITE_18 … #define DREG_REGID_TRAP_WRITE_19 … #define DREG_REGID_TRAP_WRITE_20 … #define DREG_REGID_TRAP_WRITE_21 … #define DREG_REGID_TRAP_WRITE_22 … #define DREG_REGID_TRAP_WRITE_23 … #endif #endif #define DREG_REGID_MAC0_ACC0_LOW … #define DREG_REGID_MAC0_ACC1_LOW … #define DREG_REGID_MAC0_ACC2_LOW … #define DREG_REGID_MAC0_ACC3_LOW … #define DREG_REGID_MAC1_ACC0_LOW … #define DREG_REGID_MAC1_ACC1_LOW … #define DREG_REGID_MAC1_ACC2_LOW … #define DREG_REGID_MAC1_ACC3_LOW … #define DREG_REGID_MAC0_ACC0_MID … #define DREG_REGID_MAC0_ACC1_MID … #define DREG_REGID_MAC0_ACC2_MID … #define DREG_REGID_MAC0_ACC3_MID … #define DREG_REGID_MAC1_ACC0_MID … #define DREG_REGID_MAC1_ACC1_MID … #define DREG_REGID_MAC1_ACC2_MID … #define DREG_REGID_MAC1_ACC3_MID … #define DREG_REGID_MAC0_ACC0_HIGH … #define DREG_REGID_MAC0_ACC1_HIGH … #define DREG_REGID_MAC0_ACC2_HIGH … #define DREG_REGID_MAC0_ACC3_HIGH … #define DREG_REGID_MAC1_ACC0_HIGH … #define DREG_REGID_MAC1_ACC1_HIGH … #define DREG_REGID_MAC1_ACC2_HIGH … #define DREG_REGID_MAC1_ACC3_HIGH … #define DREG_REGID_RSHOUT_LOW … #define DREG_REGID_RSHOUT_MID … #define DREG_REGID_RSHOUT_HIGH … /* * The following defines are for the flags in the DMA stream requestor write */ #define DSRWP_DSR_MASK … #define DSRWP_DSR_BG_RQ … #define DSRWP_DSR_PRIORITY_MASK … #define DSRWP_DSR_PRIORITY_0 … #define DSRWP_DSR_PRIORITY_1 … #define DSRWP_DSR_PRIORITY_2 … #define DSRWP_DSR_PRIORITY_3 … #define DSRWP_DSR_RQ_PENDING … /* * The following defines are for the flags in the trap write port register. */ #define TWPR_TW_MASK … #define TWPR_TW_SHIFT … /* * The following defines are for the flags in the stack pointer write * register. */ #define SPWR_STKP_MASK … #define SPWR_STKP_SHIFT … /* * The following defines are for the flags in the SP interrupt register. */ #define SPIR_FRI … #define SPIR_DOI … #define SPIR_GPI2 … #define SPIR_GPI3 … #define SPIR_IP0 … #define SPIR_IP1 … #define SPIR_IP2 … #define SPIR_IP3 … /* * The following defines are for the flags in the functional group 1 register. */ #define FGR1_F1S_MASK … #define FGR1_F1S_SHIFT … /* * The following defines are for the flags in the SP clock status register. */ #define SPCS_FRI … #define SPCS_DOI … #define SPCS_GPI2 … #define SPCS_GPI3 … #define SPCS_IP0 … #define SPCS_IP1 … #define SPCS_IP2 … #define SPCS_IP3 … #define SPCS_SPRUN … #define SPCS_SLEEP … #define SPCS_FG … #define SPCS_ORUN … #define SPCS_IRQ … #define SPCS_FGN_MASK … #define SPCS_FGN_SHIFT … /* * The following defines are for the flags in the SP DMA requestor status * register. */ #define SDSR_DCS_MASK … #define SDSR_DCS_SHIFT … #define SDSR_DCS_NONE … /* * The following defines are for the flags in the frame timer register. */ #define FRMT_FTV_MASK … #define FRMT_FTV_SHIFT … /* * The following defines are for the flags in the frame timer current count * register. */ #define FRCC_FCC_MASK … #define FRCC_FCC_SHIFT … /* * The following defines are for the flags in the frame timer save count * register. */ #define FRSC_FCS_MASK … #define FRSC_FCS_SHIFT … /* * The following define the various flags stored in the scatter/gather * descriptors. */ #define DMA_SG_NEXT_ENTRY_MASK … #define DMA_SG_SAMPLE_END_MASK … #define DMA_SG_SAMPLE_END_FLAG … #define DMA_SG_LOOP_END_FLAG … #define DMA_SG_SIGNAL_END_FLAG … #define DMA_SG_SIGNAL_PAGE_FLAG … #define DMA_SG_NEXT_ENTRY_SHIFT … #define DMA_SG_SAMPLE_END_SHIFT … /* * The following define the offsets of the fields within the on-chip generic * DMA requestor. */ #define DMA_RQ_CONTROL1 … #define DMA_RQ_CONTROL2 … #define DMA_RQ_SOURCE_ADDR … #define DMA_RQ_DESTINATION_ADDR … #define DMA_RQ_NEXT_PAGE_ADDR … #define DMA_RQ_NEXT_PAGE_SGDESC … #define DMA_RQ_LOOP_START_ADDR … #define DMA_RQ_POST_LOOP_ADDR … #define DMA_RQ_PAGE_MAP_ADDR … /* * The following defines are for the flags in the first control word of the * on-chip generic DMA requestor. */ #define DMA_RQ_C1_COUNT_MASK … #define DMA_RQ_C1_DESTINATION_SCATTER … #define DMA_RQ_C1_SOURCE_GATHER … #define DMA_RQ_C1_DONE_FLAG … #define DMA_RQ_C1_OPTIMIZE_STATE … #define DMA_RQ_C1_SAMPLE_END_STATE_MASK … #define DMA_RQ_C1_FULL_PAGE … #define DMA_RQ_C1_BEFORE_SAMPLE_END … #define DMA_RQ_C1_PAGE_MAP_ERROR … #define DMA_RQ_C1_AT_SAMPLE_END … #define DMA_RQ_C1_LOOP_END_STATE_MASK … #define DMA_RQ_C1_NOT_LOOP_END … #define DMA_RQ_C1_BEFORE_LOOP_END … #define DMA_RQ_C1_2PAGE_LOOP_BEGIN … #define DMA_RQ_C1_LOOP_BEGIN … #define DMA_RQ_C1_PAGE_MAP_MASK … #define DMA_RQ_C1_PM_NONE_PENDING … #define DMA_RQ_C1_PM_NEXT_PENDING … #define DMA_RQ_C1_PM_RESERVED … #define DMA_RQ_C1_PM_LOOP_NEXT_PENDING … #define DMA_RQ_C1_WRITEBACK_DEST_FLAG … #define DMA_RQ_C1_WRITEBACK_SRC_FLAG … #define DMA_RQ_C1_DEST_SIZE_MASK … #define DMA_RQ_C1_DEST_LINEAR … #define DMA_RQ_C1_DEST_MOD16 … #define DMA_RQ_C1_DEST_MOD32 … #define DMA_RQ_C1_DEST_MOD64 … #define DMA_RQ_C1_DEST_MOD128 … #define DMA_RQ_C1_DEST_MOD256 … #define DMA_RQ_C1_DEST_MOD512 … #define DMA_RQ_C1_DEST_MOD1024 … #define DMA_RQ_C1_DEST_ON_HOST … #define DMA_RQ_C1_SOURCE_SIZE_MASK … #define DMA_RQ_C1_SOURCE_LINEAR … #define DMA_RQ_C1_SOURCE_MOD16 … #define DMA_RQ_C1_SOURCE_MOD32 … #define DMA_RQ_C1_SOURCE_MOD64 … #define DMA_RQ_C1_SOURCE_MOD128 … #define DMA_RQ_C1_SOURCE_MOD256 … #define DMA_RQ_C1_SOURCE_MOD512 … #define DMA_RQ_C1_SOURCE_MOD1024 … #define DMA_RQ_C1_SOURCE_ON_HOST … #define DMA_RQ_C1_COUNT_SHIFT … /* * The following defines are for the flags in the second control word of the * on-chip generic DMA requestor. */ #define DMA_RQ_C2_VIRTUAL_CHANNEL_MASK … #define DMA_RQ_C2_VIRTUAL_SIGNAL_MASK … #define DMA_RQ_C2_NO_VIRTUAL_SIGNAL … #define DMA_RQ_C2_SIGNAL_EVERY_DMA … #define DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG … #define DMA_RQ_C2_SIGNAL_DEST_PINGPONG … #define DMA_RQ_C2_AUDIO_CONVERT_MASK … #define DMA_RQ_C2_AC_NONE … #define DMA_RQ_C2_AC_8_TO_16_BIT … #define DMA_RQ_C2_AC_MONO_TO_STEREO … #define DMA_RQ_C2_AC_ENDIAN_CONVERT … #define DMA_RQ_C2_AC_SIGNED_CONVERT … #define DMA_RQ_C2_LOOP_END_MASK … #define DMA_RQ_C2_LOOP_MASK … #define DMA_RQ_C2_NO_LOOP … #define DMA_RQ_C2_ONE_PAGE_LOOP … #define DMA_RQ_C2_TWO_PAGE_LOOP … #define DMA_RQ_C2_MULTI_PAGE_LOOP … #define DMA_RQ_C2_SIGNAL_LOOP_BACK … #define DMA_RQ_C2_SIGNAL_POST_BEGIN_PAGE … #define DMA_RQ_C2_VIRTUAL_CHANNEL_SHIFT … #define DMA_RQ_C2_LOOP_END_SHIFT … /* * The following defines are for the flags in the source and destination words * of the on-chip generic DMA requestor. */ #define DMA_RQ_SD_ADDRESS_MASK … #define DMA_RQ_SD_MEMORY_ID_MASK … #define DMA_RQ_SD_SP_PARAM_ADDR … #define DMA_RQ_SD_SP_SAMPLE_ADDR … #define DMA_RQ_SD_SP_PROGRAM_ADDR … #define DMA_RQ_SD_SP_DEBUG_ADDR … #define DMA_RQ_SD_OMNIMEM_ADDR … #define DMA_RQ_SD_END_FLAG … #define DMA_RQ_SD_ERROR_FLAG … #define DMA_RQ_SD_ADDRESS_SHIFT … /* * The following defines are for the flags in the page map address word of the * on-chip generic DMA requestor. */ #define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_MASK … #define DMA_RQ_PMA_PAGE_TABLE_MASK … #define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_SHIFT … #define DMA_RQ_PMA_PAGE_TABLE_SHIFT … #define BA1_VARIDEC_BUF_1 … #define BA1_PDTC … #define BA1_PFIE … #define BA1_PBA … #define BA1_PVOL … #define BA1_PSRC … #define BA1_PCTL … #define BA1_PPI … #define BA1_CCTL … #define BA1_CIE … #define BA1_CBA … #define BA1_CSRC … #define BA1_CCI … #define BA1_CD … #define BA1_CPI … #define BA1_CVOL … #define BA1_CFG1 … #define BA1_CFG2 … #define BA1_CCST … #define BA1_CSPB … /* * */ #define CS46XX_MODE_OUTPUT … #define CS46XX_MODE_INPUT … /* * */ #define SAVE_REG_MAX … #define POWER_DOWN_ALL … /* maxinum number of AC97 codecs connected, AC97 2.0 defined 4 */ #define MAX_NR_AC97 … #define CS46XX_PRIMARY_CODEC_INDEX … #define CS46XX_SECONDARY_CODEC_INDEX … #define CS46XX_SECONDARY_CODEC_OFFSET … #define CS46XX_DSP_CAPTURE_CHANNEL … /* capture */ #define CS46XX_DSP_CAPTURE_CHANNEL … /* mixer */ #define CS46XX_MIXER_SPDIF_INPUT_ELEMENT … #define CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT … struct snd_cs46xx_pcm { … }; struct snd_cs46xx_region { … }; struct snd_cs46xx { … }; int snd_cs46xx_create(struct snd_card *card, struct pci_dev *pci, int external_amp, int thinkpad); extern const struct dev_pm_ops snd_cs46xx_pm; int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device); int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device); int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device); int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device); int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device); int snd_cs46xx_midi(struct snd_cs46xx *chip, int device); int snd_cs46xx_start_dsp(struct snd_cs46xx *chip); int snd_cs46xx_gameport(struct snd_cs46xx *chip); #endif /* __SOUND_CS46XX_H */
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