/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * The driver for the Cirrus Logic's Sound Fusion CS46XX based soundcards * Copyright (c) by Jaroslav Kysela <[email protected]> */ /* * 2002-07 Benny Sjostrand [email protected] */ #ifdef CONFIG_SND_CS46XX_NEW_DSP /* hack ... */ #ifndef __DSP_SPOS_H__ #define __DSP_SPOS_H__ #define DSP_MAX_SYMBOLS … #define DSP_MAX_MODULES … #define DSP_CODE_BYTE_SIZE … #define DSP_PARAMETER_BYTE_SIZE … #define DSP_SAMPLE_BYTE_SIZE … #define DSP_PARAMETER_BYTE_OFFSET … #define DSP_SAMPLE_BYTE_OFFSET … #define DSP_CODE_BYTE_OFFSET … #define WIDE_INSTR_MASK … #define WIDE_LADD_INSTR_MASK … /* this instruction types needs to be reallocated when load code into DSP */ enum wide_opcode { … }; /* SAMPLE segment */ #define VARI_DECIMATE_BUF1 … #define WRITE_BACK_BUF1 … #define CODEC_INPUT_BUF1 … #define PCM_READER_BUF1 … #define SRC_DELAY_BUF1 … #define VARI_DECIMATE_BUF0 … #define SRC_OUTPUT_BUF1 … #define ASYNC_IP_OUTPUT_BUFFER1 … #define OUTPUT_SNOOP_BUFFER … #define SPDIFI_IP_OUTPUT_BUFFER1 … #define SPDIFO_IP_OUTPUT_BUFFER1 … #define MIX_SAMPLE_BUF1 … #define MIX_SAMPLE_BUF2 … #define MIX_SAMPLE_BUF3 … #define MIX_SAMPLE_BUF4 … #define MIX_SAMPLE_BUF5 … /* Task stack address */ #define HFG_STACK … #define FG_STACK … #define BG_STACK … /* SCB's addresses */ #define SPOSCB_ADDR … #define BG_TREE_SCB_ADDR … #define NULL_SCB_ADDR … #define TIMINGMASTER_SCB_ADDR … #define CODECOUT_SCB_ADDR … #define PCMREADER_SCB_ADDR … #define WRITEBACK_SCB_ADDR … #define CODECIN_SCB_ADDR … #define MASTERMIX_SCB_ADDR … #define SRCTASK_SCB_ADDR … #define VARIDECIMATE_SCB_ADDR … #define PCMSERIALIN_SCB_ADDR … #define FG_TASK_HEADER_ADDR … #define ASYNCTX_SCB_ADDR … #define ASYNCRX_SCB_ADDR … #define SRCTASKII_SCB_ADDR … #define OUTPUTSNOOP_SCB_ADDR … #define PCMSERIALINII_SCB_ADDR … #define SPIOWRITE_SCB_ADDR … #define REAR_CODECOUT_SCB_ADDR … #define OUTPUTSNOOPII_SCB_ADDR … #define PCMSERIALIN_PCM_SCB_ADDR … #define RECORD_MIXER_SCB_ADDR … #define REAR_MIXER_SCB_ADDR … #define CLFE_MIXER_SCB_ADDR … #define CLFE_CODEC_SCB_ADDR … /* hyperforground SCB's*/ #define HFG_TREE_SCB … #define SPDIFI_SCB_INST … #define SPDIFO_SCB_INST … #define WRITE_BACK_SPB … /* offsets */ #define AsyncCIOFIFOPointer … #define SPDIFOFIFOPointer … #define SPDIFIFIFOPointer … #define TCBData … #define HFGFlags … #define TCBContextBlk … #define AFGTxAccumPhi … #define SCBsubListPtr … #define SCBfuncEntryPtr … #define SRCCorPerGof … #define SRCPhiIncr6Int26Frac … #define SCBVolumeCtrl … /* conf */ #define UseASER1Input … /* * The following defines are for the flags in the rsConfig01/23 registers of * the SP. */ #define RSCONFIG_MODULO_SIZE_MASK … #define RSCONFIG_MODULO_16 … #define RSCONFIG_MODULO_32 … #define RSCONFIG_MODULO_64 … #define RSCONFIG_MODULO_128 … #define RSCONFIG_MODULO_256 … #define RSCONFIG_MODULO_512 … #define RSCONFIG_MODULO_1024 … #define RSCONFIG_MODULO_4 … #define RSCONFIG_MODULO_8 … #define RSCONFIG_SAMPLE_SIZE_MASK … #define RSCONFIG_SAMPLE_8MONO … #define RSCONFIG_SAMPLE_8STEREO … #define RSCONFIG_SAMPLE_16MONO … #define RSCONFIG_SAMPLE_16STEREO … #define RSCONFIG_UNDERRUN_ZERO … #define RSCONFIG_DMA_TO_HOST … #define RSCONFIG_STREAM_NUM_MASK … #define RSCONFIG_MAX_DMA_SIZE_MASK … #define RSCONFIG_DMA_ENABLE … #define RSCONFIG_PRIORITY_MASK … #define RSCONFIG_PRIORITY_HIGH … #define RSCONFIG_PRIORITY_MEDIUM_HIGH … #define RSCONFIG_PRIORITY_MEDIUM_LOW … #define RSCONFIG_PRIORITY_LOW … #define RSCONFIG_STREAM_NUM_SHIFT … #define RSCONFIG_MAX_DMA_SIZE_SHIFT … /* SP constants */ #define FG_INTERVAL_TIMER_PERIOD … #define BG_INTERVAL_TIMER_PERIOD … /* Only SP accessible registers */ #define SP_ASER_COUNTDOWN … #define SP_SPDOUT_FIFO … #define SP_SPDIN_MI_FIFO … #define SP_SPDIN_D_FIFO … #define SP_SPDIN_STATUS … #define SP_SPDIN_CONTROL … #define SP_SPDIN_FIFOPTR … #define SP_SPDOUT_STATUS … #define SP_SPDOUT_CONTROL … #define SP_SPDOUT_CSUV … static inline u8 _wrap_all_bits (u8 val) { … } static inline void cs46xx_dsp_spos_update_scb (struct snd_cs46xx * chip, struct dsp_scb_descriptor * scb) { … } static inline void cs46xx_dsp_scb_set_volume (struct snd_cs46xx * chip, struct dsp_scb_descriptor * scb, u16 left, u16 right) { … } #endif /* __DSP_SPOS_H__ */ #endif /* CONFIG_SND_CS46XX_NEW_DSP */
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