/**************************************************************************** Copyright Echo Digital Audio Corporation (c) 1998 - 2004 All rights reserved www.echoaudio.com This file is part of Echo Digital Audio's generic driver library. Echo Digital Audio's generic driver library is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ************************************************************************* Translation from C++ and adaptation for use in ALSA-Driver were made by Giuliano Pochini <[email protected]> ****************************************************************************/ #ifndef _ECHO_DSP_ #define _ECHO_DSP_ /**** Echogals: Darla20, Gina20, Layla20, and Darla24 ****/ #if defined(ECHOGALS_FAMILY) #define NUM_ASIC_TESTS … #define READ_DSP_TIMEOUT … /**** Echo24: Gina24, Layla24, Mona, Mia, Mia-midi ****/ #elif defined(ECHO24_FAMILY) #define DSP_56361 … #define READ_DSP_TIMEOUT … /**** 3G: Gina3G, Layla3G ****/ #elif defined(ECHO3G_FAMILY) #define DSP_56361 #define READ_DSP_TIMEOUT … #define MIN_MTC_1X_RATE … /**** Indigo: Indigo, Indigo IO, Indigo DJ ****/ #elif defined(INDIGO_FAMILY) #define DSP_56361 #define READ_DSP_TIMEOUT … #else #error No family is defined #endif /* * * Max inputs and outputs * */ #define DSP_MAXAUDIOINPUTS … #define DSP_MAXAUDIOOUTPUTS … #define DSP_MAXPIPES … /* * * These are the offsets for the memory-mapped DSP registers; the DSP base * address is treated as the start of a u32 array. */ #define CHI32_CONTROL_REG … #define CHI32_STATUS_REG … #define CHI32_VECTOR_REG … #define CHI32_DATA_REG … /* * * Interesting bits within the DSP registers * */ #define CHI32_VECTOR_BUSY … #define CHI32_STATUS_REG_HF3 … #define CHI32_STATUS_REG_HF4 … #define CHI32_STATUS_REG_HF5 … #define CHI32_STATUS_HOST_READ_FULL … #define CHI32_STATUS_HOST_WRITE_EMPTY … #define CHI32_STATUS_IRQ … /* * * DSP commands sent via slave mode; these are sent to the DSP by write_dsp() * */ #define DSP_FNC_SET_COMMPAGE_ADDR … #define DSP_FNC_LOAD_LAYLA_ASIC … #define DSP_FNC_LOAD_GINA24_ASIC … #define DSP_FNC_LOAD_MONA_PCI_CARD_ASIC … #define DSP_FNC_LOAD_LAYLA24_PCI_CARD_ASIC … #define DSP_FNC_LOAD_MONA_EXTERNAL_ASIC … #define DSP_FNC_LOAD_LAYLA24_EXTERNAL_ASIC … #define DSP_FNC_LOAD_3G_ASIC … /* * * Defines to handle the MIDI input state engine; these are used to properly * extract MIDI time code bytes and their timestamps from the MIDI input stream. * */ #define MIDI_IN_STATE_NORMAL … #define MIDI_IN_STATE_TS_HIGH … #define MIDI_IN_STATE_TS_LOW … #define MIDI_IN_STATE_F1_DATA … #define MIDI_IN_SKIP_DATA … /*---------------------------------------------------------------------------- Setting the sample rates on Layla24 is somewhat schizophrenic. For standard rates, it works exactly like Mona and Gina24. That is, for 8, 11.025, 16, 22.05, 32, 44.1, 48, 88.2, and 96 kHz, you just set the appropriate bits in the control register and write the control register. In order to support MIDI time code sync (and possibly SMPTE LTC sync in the future), Layla24 also has "continuous sample rate mode". In this mode, Layla24 can generate any sample rate between 25 and 50 kHz inclusive, or 50 to 100 kHz inclusive for double speed mode. To use continuous mode: -Set the clock select bits in the control register to 0xe (see the #define below) -Set double-speed mode if you want to use sample rates above 50 kHz -Write the control register as you would normally -Now, you need to set the frequency register. First, you need to determine the value for the frequency register. This is given by the following formula: frequency_reg = (LAYLA24_MAGIC_NUMBER / sample_rate) - 2 Note the #define below for the magic number -Wait for the DSP handshake -Write the frequency_reg value to the .SampleRate field of the comm page -Send the vector command SET_LAYLA24_FREQUENCY_REG (see vmonkey.h) Once you have set the control register up for continuous mode, you can just write the frequency register to change the sample rate. This could be used for MIDI time code sync. For MTC sync, the control register is set for continuous mode. The driver then just keeps writing the SET_LAYLA24_FREQUENCY_REG command. -----------------------------------------------------------------------------*/ #define LAYLA24_MAGIC_NUMBER … #define LAYLA24_CONTINUOUS_CLOCK … /* * * DSP vector commands * */ #define DSP_VC_RESET … #ifndef DSP_56361 #define DSP_VC_ACK_INT … #define DSP_VC_SET_VMIXER_GAIN … #define DSP_VC_START_TRANSFER … #define DSP_VC_METERS_ON … #define DSP_VC_METERS_OFF … #define DSP_VC_UPDATE_OUTVOL … #define DSP_VC_UPDATE_INGAIN … #define DSP_VC_ADD_AUDIO_BUFFER … #define DSP_VC_TEST_ASIC … #define DSP_VC_UPDATE_CLOCKS … #define DSP_VC_SET_LAYLA_SAMPLE_RATE … #define DSP_VC_SET_GD_AUDIO_STATE … #define DSP_VC_WRITE_CONTROL_REG … #define DSP_VC_MIDI_WRITE … #define DSP_VC_STOP_TRANSFER … #define DSP_VC_UPDATE_FLAGS … #define DSP_VC_GO_COMATOSE … #else /* !DSP_56361 */ /* Vector commands for families that use either the 56301 or 56361 */ #define DSP_VC_ACK_INT … #define DSP_VC_SET_VMIXER_GAIN … #define DSP_VC_START_TRANSFER … #define DSP_VC_METERS_ON … #define DSP_VC_METERS_OFF … #define DSP_VC_UPDATE_OUTVOL … #define DSP_VC_UPDATE_INGAIN … #define DSP_VC_ADD_AUDIO_BUFFER … #define DSP_VC_TEST_ASIC … #define DSP_VC_UPDATE_CLOCKS … #define DSP_VC_SET_LAYLA24_FREQUENCY_REG … #define DSP_VC_SET_LAYLA_SAMPLE_RATE … #define DSP_VC_SET_GD_AUDIO_STATE … #define DSP_VC_WRITE_CONTROL_REG … #define DSP_VC_MIDI_WRITE … #define DSP_VC_STOP_TRANSFER … #define DSP_VC_UPDATE_FLAGS … #define DSP_VC_GO_COMATOSE … #endif /* !DSP_56361 */ /* * * Timeouts * */ #define HANDSHAKE_TIMEOUT … #define VECTOR_BUSY_TIMEOUT … #define MIDI_OUT_DELAY_USEC … /* * * Flags for .Flags field in the comm page * */ #define DSP_FLAG_MIDI_INPUT … #define DSP_FLAG_SPDIF_NONAUDIO … #define DSP_FLAG_PROFESSIONAL_SPDIF … /* * * Clock detect bits reported by the DSP for Gina20, Layla20, Darla24, and Mia * */ #define GLDM_CLOCK_DETECT_BIT_WORD … #define GLDM_CLOCK_DETECT_BIT_SUPER … #define GLDM_CLOCK_DETECT_BIT_SPDIF … #define GLDM_CLOCK_DETECT_BIT_ESYNC … /* * * Clock detect bits reported by the DSP for Gina24, Mona, and Layla24 * */ #define GML_CLOCK_DETECT_BIT_WORD96 … #define GML_CLOCK_DETECT_BIT_WORD48 … #define GML_CLOCK_DETECT_BIT_SPDIF48 … #define GML_CLOCK_DETECT_BIT_SPDIF96 … #define GML_CLOCK_DETECT_BIT_WORD … #define GML_CLOCK_DETECT_BIT_SPDIF … #define GML_CLOCK_DETECT_BIT_ESYNC … #define GML_CLOCK_DETECT_BIT_ADAT … /* * * Layla clock numbers to send to DSP * */ #define LAYLA20_CLOCK_INTERNAL … #define LAYLA20_CLOCK_SPDIF … #define LAYLA20_CLOCK_WORD … #define LAYLA20_CLOCK_SUPER … /* * * Gina/Darla clock states * */ #define GD_CLOCK_NOCHANGE … #define GD_CLOCK_44 … #define GD_CLOCK_48 … #define GD_CLOCK_SPDIFIN … #define GD_CLOCK_UNDEF … /* * * Gina/Darla S/PDIF status bits * */ #define GD_SPDIF_STATUS_NOCHANGE … #define GD_SPDIF_STATUS_44 … #define GD_SPDIF_STATUS_48 … #define GD_SPDIF_STATUS_UNDEF … /* * * Layla20 output clocks * */ #define LAYLA20_OUTPUT_CLOCK_SUPER … #define LAYLA20_OUTPUT_CLOCK_WORD … /**************************************************************************** Magic constants for the Darla24 hardware ****************************************************************************/ #define GD24_96000 … #define GD24_48000 … #define GD24_44100 … #define GD24_32000 … #define GD24_22050 … #define GD24_16000 … #define GD24_11025 … #define GD24_8000 … #define GD24_88200 … #define GD24_EXT_SYNC … /* * * Return values from the DSP when ASIC is loaded * */ #define ASIC_ALREADY_LOADED … #define ASIC_NOT_LOADED … /* * * DSP Audio formats * * These are the audio formats that the DSP can transfer * via input and output pipes. LE means little-endian, * BE means big-endian. * * DSP_AUDIOFORM_MS_8 * * 8-bit mono unsigned samples. For playback, * mono data is duplicated out the left and right channels * of the output bus. The "MS" part of the name * means mono->stereo. * * DSP_AUDIOFORM_MS_16LE * * 16-bit signed little-endian mono samples. Playback works * like the previous code. * * DSP_AUDIOFORM_MS_24LE * * 24-bit signed little-endian mono samples. Data is packed * three bytes per sample; if you had two samples 0x112233 and 0x445566 * they would be stored in memory like this: 33 22 11 66 55 44. * * DSP_AUDIOFORM_MS_32LE * * 24-bit signed little-endian mono samples in a 32-bit * container. In other words, each sample is a 32-bit signed * integer, where the actual audio data is left-justified * in the 32 bits and only the 24 most significant bits are valid. * * DSP_AUDIOFORM_SS_8 * DSP_AUDIOFORM_SS_16LE * DSP_AUDIOFORM_SS_24LE * DSP_AUDIOFORM_SS_32LE * * Like the previous ones, except now with stereo interleaved * data. "SS" means stereo->stereo. * * DSP_AUDIOFORM_MM_32LE * * Similar to DSP_AUDIOFORM_MS_32LE, except that the mono * data is not duplicated out both the left and right outputs. * This mode is used by the ASIO driver. Here, "MM" means * mono->mono. * * DSP_AUDIOFORM_MM_32BE * * Just like DSP_AUDIOFORM_MM_32LE, but now the data is * in big-endian format. * */ #define DSP_AUDIOFORM_MS_8 … #define DSP_AUDIOFORM_MS_16LE … #define DSP_AUDIOFORM_MS_24LE … #define DSP_AUDIOFORM_MS_32LE … #define DSP_AUDIOFORM_SS_8 … #define DSP_AUDIOFORM_SS_16LE … #define DSP_AUDIOFORM_SS_24LE … #define DSP_AUDIOFORM_SS_32LE … #define DSP_AUDIOFORM_MM_32LE … #define DSP_AUDIOFORM_MM_32BE … #define DSP_AUDIOFORM_SS_32BE … #define DSP_AUDIOFORM_INVALID … /* * * Super-interleave is defined as interleaving by 4 or more. Darla20 and Gina20 * do not support super interleave. * * 16 bit, 24 bit, and 32 bit little endian samples are supported for super * interleave. The interleave factor must be even. 16 - way interleave is the * current maximum, so you can interleave by 4, 6, 8, 10, 12, 14, and 16. * * The actual format code is derived by taking the define below and or-ing with * the interleave factor. So, 32 bit interleave by 6 is 0x86 and * 16 bit interleave by 16 is (0x40 | 0x10) = 0x50. * */ #define DSP_AUDIOFORM_SUPER_INTERLEAVE_16LE … #define DSP_AUDIOFORM_SUPER_INTERLEAVE_24LE … #define DSP_AUDIOFORM_SUPER_INTERLEAVE_32LE … /* * * Gina24, Mona, and Layla24 control register defines * */ #define GML_CONVERTER_ENABLE … #define GML_SPDIF_PRO_MODE … #define GML_SPDIF_SAMPLE_RATE0 … #define GML_SPDIF_SAMPLE_RATE1 … #define GML_SPDIF_TWO_CHANNEL … #define GML_SPDIF_NOT_AUDIO … #define GML_SPDIF_COPY_PERMIT … #define GML_SPDIF_24_BIT … #define GML_ADAT_MODE … #define GML_SPDIF_OPTICAL_MODE … #define GML_SPDIF_CDROM_MODE … #define GML_DOUBLE_SPEED_MODE … #define GML_DIGITAL_IN_AUTO_MUTE … #define GML_96KHZ … #define GML_88KHZ … #define GML_48KHZ … #define GML_44KHZ … #define GML_32KHZ … #define GML_22KHZ … #define GML_16KHZ … #define GML_11KHZ … #define GML_8KHZ … #define GML_SPDIF_CLOCK … #define GML_ADAT_CLOCK … #define GML_WORD_CLOCK … #define GML_ESYNC_CLOCK … #define GML_ESYNCx2_CLOCK … #define GML_CLOCK_CLEAR_MASK … #define GML_SPDIF_RATE_CLEAR_MASK … #define GML_DIGITAL_MODE_CLEAR_MASK … #define GML_SPDIF_FORMAT_CLEAR_MASK … /* * * Mia sample rate and clock setting constants * */ #define MIA_32000 … #define MIA_44100 … #define MIA_48000 … #define MIA_88200 … #define MIA_96000 … #define MIA_SPDIF … #define MIA_SPDIF96 … #define MIA_MIDI_REV … /* * * 3G register bits * */ #define E3G_CONVERTER_ENABLE … #define E3G_SPDIF_PRO_MODE … #define E3G_SPDIF_SAMPLE_RATE0 … #define E3G_SPDIF_SAMPLE_RATE1 … #define E3G_SPDIF_TWO_CHANNEL … #define E3G_SPDIF_NOT_AUDIO … #define E3G_SPDIF_COPY_PERMIT … #define E3G_SPDIF_24_BIT … #define E3G_DOUBLE_SPEED_MODE … #define E3G_PHANTOM_POWER … #define E3G_96KHZ … #define E3G_88KHZ … #define E3G_48KHZ … #define E3G_44KHZ … #define E3G_32KHZ … #define E3G_22KHZ … #define E3G_16KHZ … #define E3G_11KHZ … #define E3G_8KHZ … #define E3G_SPDIF_CLOCK … #define E3G_ADAT_CLOCK … #define E3G_WORD_CLOCK … #define E3G_CONTINUOUS_CLOCK … #define E3G_ADAT_MODE … #define E3G_SPDIF_OPTICAL_MODE … #define E3G_CLOCK_CLEAR_MASK … #define E3G_DIGITAL_MODE_CLEAR_MASK … #define E3G_SPDIF_FORMAT_CLEAR_MASK … /* Clock detect bits reported by the DSP */ #define E3G_CLOCK_DETECT_BIT_WORD96 … #define E3G_CLOCK_DETECT_BIT_WORD48 … #define E3G_CLOCK_DETECT_BIT_SPDIF48 … #define E3G_CLOCK_DETECT_BIT_ADAT … #define E3G_CLOCK_DETECT_BIT_SPDIF96 … #define E3G_CLOCK_DETECT_BIT_WORD … #define E3G_CLOCK_DETECT_BIT_SPDIF … /* Frequency control register */ #define E3G_MAGIC_NUMBER … #define E3G_FREQ_REG_DEFAULT … #define E3G_FREQ_REG_MAX … /* 3G external box types */ #define E3G_GINA3G_BOX_TYPE … #define E3G_LAYLA3G_BOX_TYPE … #define E3G_ASIC_NOT_LOADED … #define E3G_BOX_TYPE_MASK … /* Indigo express control register values */ #define INDIGO_EXPRESS_32000 … #define INDIGO_EXPRESS_44100 … #define INDIGO_EXPRESS_48000 … #define INDIGO_EXPRESS_DOUBLE_SPEED … #define INDIGO_EXPRESS_QUAD_SPEED … #define INDIGO_EXPRESS_CLOCK_MASK … /* * * Gina20 & Layla20 have input gain controls for the analog inputs; * this is the magic number for the hardware that gives you 0 dB at -10. * */ #define GL20_INPUT_GAIN_MAGIC_NUMBER … /* * * Defines how much time must pass between DSP load attempts * */ #define DSP_LOAD_ATTEMPT_PERIOD … /* * * Size of arrays for the comm page. MAX_PLAY_TAPS and MAX_REC_TAPS are * no longer used, but the sizes must still be right for the DSP to see * the comm page correctly. * */ #define MONITOR_ARRAY_SIZE … #define VMIXER_ARRAY_SIZE … #define MIDI_OUT_BUFFER_SIZE … #define MIDI_IN_BUFFER_SIZE … #define MAX_PLAY_TAPS … #define MAX_REC_TAPS … #define DSP_MIDI_OUT_FIFO_SIZE … /* sg_entry is a single entry for the scatter-gather list. The array of struct sg_entry struct is read by the DSP, so all values must be little-endian. */ #define MAX_SGLIST_ENTRIES … struct sg_entry { … }; /**************************************************************************** The comm page. This structure is read and written by the DSP; the DSP code is a firm believer in the byte offsets written in the comments at the end of each line. This structure should not be changed. Any reads from or writes to this structure should be in little-endian format. ****************************************************************************/ struct comm_page { … }; #endif /* _ECHO_DSP_ */
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