// SPDX-License-Identifier: GPL-2.0 /* * Copyright 2020-2022 HabanaLabs, Ltd. * All Rights Reserved. */ #include "gaudi2P.h" #include "../include/gaudi2/asic_reg/gaudi2_regs.h" #define UNSET_GLBL_SEC_BIT(array, b) … #define SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD … #define SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD … #define SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR … #define SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR … #define SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR … #define SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD … #define SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR … #define SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR … /* LBW RR */ #define SFT_NUM_OF_LBW_RTR … #define SFT_LBW_RTR_OFFSET … #define RR_LBW_LONG_MASK … #define RR_LBW_SHORT_MASK … /* HBW RR */ #define SFT_NUM_OF_HBW_RTR … #define RR_HBW_SHORT_LO_MASK … #define RR_HBW_SHORT_HI_MASK … #define RR_HBW_LONG_LO_MASK … #define RR_HBW_LONG_HI_MASK … struct rr_config { … }; struct gaudi2_atypical_bp_blocks { … }; static const struct gaudi2_atypical_bp_blocks gaudi2_pb_dcr0_sm_objs = …; static const u32 gaudi2_pb_sft0[] = …; static const u32 gaudi2_pb_dcr0_hif[] = …; static const u32 gaudi2_pb_dcr0_rtr0[] = …; static const u32 gaudi2_pb_dcr0_hmmu0[] = …; static const u32 gaudi2_pb_cpu_if[] = …; static const u32 gaudi2_pb_cpu[] = …; static const u32 gaudi2_pb_kdma[] = …; static const u32 gaudi2_pb_pdma0[] = …; static const u32 gaudi2_pb_pdma0_arc[] = …; static const struct range gaudi2_pb_pdma0_arc_unsecured_regs[] = …; static const u32 gaudi2_pb_pdma0_unsecured_regs[] = …; static const u32 gaudi2_pb_dcr0_edma0[] = …; static const u32 gaudi2_pb_dcr0_edma0_arc[] = …; static const struct range gaudi2_pb_dcr0_edma0_arc_unsecured_regs[] = …; static const u32 gaudi2_pb_dcr0_edma0_unsecured_regs[] = …; static const u32 gaudi2_pb_dcr0_mme_sbte[] = …; static const u32 gaudi2_pb_dcr0_mme_qm[] = …; static const u32 gaudi2_pb_dcr0_mme_eng[] = …; static const u32 gaudi2_pb_dcr0_mme_arc[] = …; static const struct range gaudi2_pb_dcr0_mme_arc_unsecured_regs[] = …; static const u32 gaudi2_pb_dcr0_mme_qm_unsecured_regs[] = …; static const u32 gaudi2_pb_dcr0_mme_eng_unsecured_regs[] = …; static const u32 gaudi2_pb_dcr0_tpc0[] = …; static const u32 gaudi2_pb_dcr0_tpc0_arc[] = …; static const struct range gaudi2_pb_dcr0_tpc0_arc_unsecured_regs[] = …; static const u32 gaudi2_pb_dcr0_tpc0_unsecured_regs[] = …; static const u32 gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs[] = …; static const u32 gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs[] = …; static const u32 gaudi2_pb_dcr0_sram0[] = …; static const u32 gaudi2_pb_dcr0_sm_mstr_if[] = …; static const u32 gaudi2_pb_dcr0_sm_glbl[] = …; static const u32 gaudi2_pb_dcr1_sm_glbl[] = …; static const struct range gaudi2_pb_dcr0_sm_glbl_unsecured_regs[] = …; static const struct range gaudi2_pb_dcr_x_sm_glbl_unsecured_regs[] = …; static const u32 gaudi2_pb_arc_sched[] = …; static const struct range gaudi2_pb_arc_sched_unsecured_regs[] = …; static const u32 gaudi2_pb_xbar_mid[] = …; static const u32 gaudi2_pb_xbar_mid_unsecured_regs[] = …; static const u32 gaudi2_pb_xbar_edge[] = …; static const u32 gaudi2_pb_xbar_edge_unsecured_regs[] = …; static const u32 gaudi2_pb_nic0[] = …; static const u32 gaudi2_pb_nic0_qm_qpc[] = …; static const u32 gaudi2_pb_nic0_qm_arc_aux0[] = …; static const struct range gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs[] = …; static const u32 gaudi2_pb_nic0_umr[] = …; static const struct range gaudi2_pb_nic0_umr_unsecured_regs[] = …; /* * mmNIC0_QPC0_LINEAR_WQE_QPN and mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN are 32-bit * registers and since the user writes in bulks of 64 bits we need to un-secure * also the following 32 bits (that's why we added also the next 4 bytes to the * table). In the RTL, as part of ECO (2874), writing to the next 4 bytes * triggers a write to the SPECIAL_GLBL_SPARE register, hence it's must be * unsecured as well. */ #define mmNIC0_QPC0_LINEAR_WQE_RSV … #define mmNIC0_QPC0_MULTI_STRIDE_WQE_RSV … #define mmNIC0_QPC0_SPECIAL_GLBL_SPARE … static const u32 gaudi2_pb_nic0_qm_qpc_unsecured_regs[] = …; static const u32 gaudi2_pb_rot0[] = …; static const u32 gaudi2_pb_rot0_arc[] = …; static const struct range gaudi2_pb_rot0_arc_unsecured_regs[] = …; static const u32 gaudi2_pb_rot0_unsecured_regs[] = …; static const u32 gaudi2_pb_psoc_global_conf[] = …; static const u32 gaudi2_pb_psoc[] = …; static const u32 gaudi2_pb_pmmu[] = …; static const u32 gaudi2_pb_psoc_pll[] = …; static const u32 gaudi2_pb_pmmu_pll[] = …; static const u32 gaudi2_pb_xbar_pll[] = …; static const u32 gaudi2_pb_xft_pll[] = …; static const u32 gaudi2_pb_pcie[] = …; static const u32 gaudi2_pb_pcie_unsecured_regs[] = …; static const u32 gaudi2_pb_thermal_sensor0[] = …; static const u32 gaudi2_pb_hbm[] = …; static const u32 gaudi2_pb_mme_qm_arc_acp_eng[] = …; static const struct range gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs[] = …; struct gaudi2_tpc_pb_data { … }; static void gaudi2_config_tpcs_glbl_sec(struct hl_device *hdev, int dcore, int inst, u32 offset, struct iterate_module_ctx *ctx) { … } static int gaudi2_init_pb_tpc(struct hl_device *hdev) { … } struct gaudi2_tpc_arc_pb_data { … }; static void gaudi2_config_tpcs_pb_ranges(struct hl_device *hdev, int dcore, int inst, u32 offset, struct iterate_module_ctx *ctx) { … } static int gaudi2_init_pb_tpc_arc(struct hl_device *hdev) { … } static int gaudi2_init_pb_sm_objs(struct hl_device *hdev) { … } static void gaudi2_write_lbw_range_register(struct hl_device *hdev, u64 base, void *data) { … } void gaudi2_write_rr_to_all_lbw_rtrs(struct hl_device *hdev, u8 rr_type, u32 rr_index, u64 min_val, u64 max_val) { … } static void gaudi2_init_lbw_range_registers_secure(struct hl_device *hdev) { … } static void gaudi2_init_lbw_range_registers(struct hl_device *hdev) { … } static void gaudi2_write_hbw_range_register(struct hl_device *hdev, u64 base, void *data) { … } static void gaudi2_write_hbw_rr_to_all_mstr_if(struct hl_device *hdev, u8 rr_type, u32 rr_index, u64 min_val, u64 max_val) { … } static void gaudi2_init_hbw_range_registers(struct hl_device *hdev) { … } static void gaudi2_write_mmu_range_register(struct hl_device *hdev, u64 base, struct rr_config *rr_cfg) { … } static void gaudi2_init_mmu_range_registers(struct hl_device *hdev) { … } /** * gaudi2_init_range_registers - * Initialize range registers of all initiators * * @hdev: pointer to hl_device structure */ static void gaudi2_init_range_registers(struct hl_device *hdev) { … } /** * gaudi2_init_protection_bits - * Initialize protection bits of specific registers * * @hdev: pointer to hl_device structure * * All protection bits are 1 by default, means not protected. Need to set to 0 * each bit that belongs to a protected register. * */ static int gaudi2_init_protection_bits(struct hl_device *hdev) { … } /** * gaudi2_init_security - Initialize security model * * @hdev: pointer to hl_device structure * * Initialize the security model of the device * That includes range registers and protection bit per register. */ int gaudi2_init_security(struct hl_device *hdev) { … } struct gaudi2_ack_pb_tpc_data { … }; static void gaudi2_ack_pb_tpc_config(struct hl_device *hdev, int dcore, int inst, u32 offset, struct iterate_module_ctx *ctx) { … } static void gaudi2_ack_pb_tpc(struct hl_device *hdev) { … } /** * gaudi2_ack_protection_bits_errors - scan all blocks having protection bits * and for every protection error found, display the appropriate error message * and clear the error. * * @hdev: pointer to hl_device structure * * All protection bits are 1 by default, means not protected. Need to set to 0 * each bit that belongs to a protected register. * */ void gaudi2_ack_protection_bits_errors(struct hl_device *hdev) { … } /* * Print PB security errors */ void gaudi2_pb_print_security_errors(struct hl_device *hdev, u32 block_addr, u32 cause, u32 offended_addr) { … }
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