/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2020 HabanaLabs, Ltd. * All Rights Reserved. * */ #ifndef GAUDI2_CORESIGHT_REGS_DRV_H_ #define GAUDI2_CORESIGHT_REGS_DRV_H_ #include "gaudi2_masks.h" #include "../include/gaudi2/gaudi2_coresight.h" #include "gaudi2P.h" /* FUNNEL Offsets - same offsets for all funnels*/ #define mmFUNNEL_CTRL_REG_OFFSET … #define mmFUNNEL_PRIORITY_CTRL_REG_OFFSET … #define mmFUNNEL_ITATBDATA0_OFFSET … #define mmFUNNEL_ITATBCTR2_OFFSET … #define mmFUNNEL_ITATBCTR1_OFFSET … #define mmFUNNEL_ITATBCTR0_OFFSET … #define mmFUNNEL_ITCTRL_OFFSET … #define mmFUNNEL_CLAIMSET_OFFSET … #define mmFUNNEL_CLAIMCLR_OFFSET … #define mmFUNNEL_LOCKACCESS_OFFSET … #define mmFUNNEL_LOCKSTATUS_OFFSET … #define mmFUNNEL_AUTHSTATUS_OFFSET … #define mmFUNNEL_DEVID_OFFSET … #define mmFUNNEL_DEVTYPE_OFFSET … #define mmFUNNEL_PIDR4_OFFSET … #define mmFUNNEL_PERIPHID5_OFFSET … #define mmFUNNEL_PERIPHID6_OFFSET … #define mmFUNNEL_PERIPHID7_OFFSET … #define mmFUNNEL_PIDR0_OFFSET … #define mmFUNNEL_PIDR1_OFFSET … #define mmFUNNEL_PIDR2_OFFSET … #define mmFUNNEL_PIDR3_OFFSET … #define mmFUNNEL_CID0_OFFSET … #define mmFUNNEL_CID1_OFFSET … #define mmFUNNEL_CID2_OFFSET … #define mmFUNNEL_CID3_OFFSET … /* ETF Offsets - same offsets for all etfs */ #define mmETF_RSZ_OFFSET … #define mmETF_STS_OFFSET … #define mmETF_RRD_OFFSET … #define mmETF_RRP_OFFSET … #define mmETF_RWP_OFFSET … #define mmETF_TRG_OFFSET … #define mmETF_CTL_OFFSET … #define mmETF_RWD_OFFSET … #define mmETF_MODE_OFFSET … #define mmETF_LBUFLEVEL_OFFSET … #define mmETF_CBUFLEVEL_OFFSET … #define mmETF_BUFWM_OFFSET … #define mmETF_FFSR_OFFSET … #define mmETF_FFCR_OFFSET … #define mmETF_PSCR_OFFSET … #define mmETF_ITATBMDATA0_OFFSET … #define mmETF_ITATBMCTR2_OFFSET … #define mmETF_ITATBMCTR1_OFFSET … #define mmETF_ITATBMCTR0_OFFSET … #define mmETF_ITMISCOP0_OFFSET … #define mmETF_ITTRFLIN_OFFSET … #define mmETF_ITATBDATA0_OFFSET … #define mmETF_ITATBCTR2_OFFSET … #define mmETF_ITATBCTR1_OFFSET … #define mmETF_ITATBCTR0_OFFSET … #define mmETF_ITCTRL_OFFSET … #define mmETF_CLAIMSET_OFFSET … #define mmETF_CLAIMCLR_OFFSET … #define mmETF_LAR_OFFSET … #define mmETF_LSR_OFFSET … #define mmETF_AUTHSTATUS_OFFSET … #define mmETF_DEVID_OFFSET … #define mmETF_DEVTYPE_OFFSET … #define mmETF_PERIPHID4_OFFSET … #define mmETF_PERIPHID5_OFFSET … #define mmETF_PERIPHID6_OFFSET … #define mmETF_PERIPHID7_OFFSET … #define mmETF_PERIPHID0_OFFSET … #define mmETF_PERIPHID1_OFFSET … #define mmETF_PERIPHID2_OFFSET … #define mmETF_PERIPHID3_OFFSET … #define mmETF_COMPID0_OFFSET … #define mmETF_COMPID1_OFFSET … #define mmETF_COMPID2_OFFSET … #define mmETF_COMPID3_OFFSET … /* STM OFFSETS - same offsets for all stms */ #define mmSTM_STMDMASTARTR_OFFSET … #define mmSTM_STMDMASTOPR_OFFSET … #define mmSTM_STMDMASTATR_OFFSET … #define mmSTM_STMDMACTLR_OFFSET … #define mmSTM_STMDMAIDR_OFFSET … #define mmSTM_STMHEER_OFFSET … #define mmSTM_STMHETER_OFFSET … #define mmSTM_STMHEBSR_OFFSET … #define mmSTM_STMHEMCR_OFFSET … #define mmSTM_STMHEEXTMUXR_OFFSET … #define mmSTM_STMHEMASTR_OFFSET … #define mmSTM_STMHEFEAT1R_OFFSET … #define mmSTM_STMHEIDR_OFFSET … #define mmSTM_STMSPER_OFFSET … #define mmSTM_STMSPTER_OFFSET … #define mmSTM_STMSPSCR_OFFSET … #define mmSTM_STMSPMSCR_OFFSET … #define mmSTM_STMSPOVERRIDER_OFFSET … #define mmSTM_STMSPMOVERRIDER_OFFSET … #define mmSTM_STMSPTRIGCSR_OFFSET … #define mmSTM_STMTCSR_OFFSET … #define mmSTM_STMTSSTIMR_OFFSET … #define mmSTM_STMTSFREQR_OFFSET … #define mmSTM_STMSYNCR_OFFSET … #define mmSTM_STMAUXCR_OFFSET … #define mmSTM_STMFEAT1R_OFFSET … #define mmSTM_STMFEAT2R_OFFSET … #define mmSTM_STMFEAT3R_OFFSET … #define mmSTM_STMITTRIGGER_OFFSET … #define mmSTM_STMITATBDATA0_OFFSET … #define mmSTM_STMITATBCTR2_OFFSET … #define mmSTM_STMITATBID_OFFSET … #define mmSTM_STMITATBCTR0_OFFSET … #define mmSTM_STMITCTRL_OFFSET … #define mmSTM_STMCLAIMSET_OFFSET … #define mmSTM_STMCLAIMCLR_OFFSET … #define mmSTM_STMLAR_OFFSET … #define mmSTM_STMLSR_OFFSET … #define mmSTM_STMAUTHSTATUS_OFFSET … #define mmSTM_STMDEVARCH_OFFSET … #define mmSTM_STMDEVID_OFFSET … #define mmSTM_STMDEVTYPE_OFFSET … #define mmSTM_STMPIDR4_OFFSET … #define mmSTM_STMPIDR5_OFFSET … #define mmSTM_STMPIDR6_OFFSET … #define mmSTM_STMPIDR7_OFFSET … #define mmSTM_STMPIDR0_OFFSET … #define mmSTM_STMPIDR1_OFFSET … #define mmSTM_STMPIDR2_OFFSET … #define mmSTM_STMPIDR3_OFFSET … #define mmSTM_STMCIDR0_OFFSET … #define mmSTM_STMCIDR1_OFFSET … #define mmSTM_STMCIDR2_OFFSET … #define mmSTM_STMCIDR3_OFFSET … /* SPMU OFFSETS - same offsets for all SPMUs */ #define mmSPMU_PMEVCNTR0_EL0_OFFSET … #define mmSPMU_PMEVCNTR1_EL0_OFFSET … #define mmSPMU_PMEVCNTR2_EL0_OFFSET … #define mmSPMU_PMEVCNTR3_EL0_OFFSET … #define mmSPMU_PMEVCNTR4_EL0_OFFSET … #define mmSPMU_PMEVCNTR5_EL0_OFFSET … #define mmSPMU_PMCCNTR_L_EL0_OFFSET … #define mmSPMU_PMCCNTR_H_EL0_OFFSET … #define mmSPMU_PMTRC_OFFSET … #define mmSPMU_TRC_CTRL_HOST_OFFSET … #define mmSPMU_TRC_STAT_HOST_OFFSET … #define mmSPMU_TRC_EN_HOST_OFFSET … #define mmSPMU_PMEVTYPER0_EL0_OFFSET … #define mmSPMU_PMEVTYPER1_EL0_OFFSET … #define mmSPMU_PMEVTYPER2_EL0_OFFSET … #define mmSPMU_PMEVTYPER3_EL0_OFFSET … #define mmSPMU_PMEVTYPER4_EL0_OFFSET … #define mmSPMU_PMEVTYPER5_EL0_OFFSET … #define mmSPMU_PMSSR_OFFSET … #define mmSPMU_PMOVSSR_OFFSET … #define mmSPMU_PMCCNTSR_L_OFFSET … #define mmSPMU_PMCCNTSR_H_OFFSET … #define mmSPMU_PMEVCNTSR0_OFFSET … #define mmSPMU_PMEVCNTSR1_OFFSET … #define mmSPMU_PMEVCNTSR2_OFFSET … #define mmSPMU_PMEVCNTSR3_OFFSET … #define mmSPMU_PMEVCNTSR4_OFFSET … #define mmSPMU_PMEVCNTSR5_OFFSET … #define mmSPMU_PMSCR_OFFSET … #define mmSPMU_PMSRR_OFFSET … #define mmSPMU_PMCNTENSET_EL0_OFFSET … #define mmSPMU_PMCNTENCLR_EL0_OFFSET … #define mmSPMU_PMINTENSET_EL1_OFFSET … #define mmSPMU_PMINTENCLR_EL1_OFFSET … #define mmSPMU_PMOVSCLR_EL0_OFFSET … #define mmSPMU_PMSWINC_EL0_OFFSET … #define mmSPMU_PMOVSSET_EL0_OFFSET … #define mmSPMU_PMCFGR_OFFSET … #define mmSPMU_PMCR_EL0_OFFSET … #define mmSPMU_PMITCTRL_OFFSET … #define mmSPMU_PMCLAIMSET_OFFSET … #define mmSPMU_PMCLAIMCLR_OFFSET … #define mmSPMU_PMDEVAFF0_OFFSET … #define mmSPMU_PMDEVAFF1_OFFSET … #define mmSPMU_PMLAR_OFFSET … #define mmSPMU_PMLSR_OFFSET … #define mmSPMU_PMAUTHSTATUS_OFFSET … #define mmSPMU_PMDEVARCH_OFFSET … #define mmSPMU_PMDEVID2_OFFSET … #define mmSPMU_PMDEVID1_OFFSET … #define mmSPMU_PMDEVID_OFFSET … #define mmSPMU_PMDEVTYPE_OFFSET … #define mmSPMU_PMPIDR4_OFFSET … #define mmSPMU_PMPIDR5_OFFSET … #define mmSPMU_PMPIDR6_OFFSET … #define mmSPMU_PMPIDR7_OFFSET … #define mmSPMU_PMPIDR0_OFFSET … #define mmSPMU_PMPIDR1_OFFSET … #define mmSPMU_PMPIDR2_OFFSET … #define mmSPMU_PMPIDR3_OFFSET … #define mmSPMU_PMCIDR0_OFFSET … #define mmSPMU_PMCIDR1_OFFSET … #define mmSPMU_PMCIDR2_OFFSET … #define mmSPMU_PMCIDR3_OFFSET … /* BMON OFFSETS - same offsets for all BMONs*/ #define mmBMON_CR_OFFSET … #define mmBMON_RESET_OFFSET … #define mmBMON_INT_CLR_OFFSET … #define mmBMON_TRIG_TH_OFFSET … #define mmBMON_ADDRL_S0_OFFSET … #define mmBMON_ADDRH_S0_OFFSET … #define mmBMON_ADDRL_E0_OFFSET … #define mmBMON_ADDRH_E0_OFFSET … #define mmBMON_ADDRL_S1_OFFSET … #define mmBMON_ADDRH_S1_OFFSET … #define mmBMON_ADDRL_E1_OFFSET … #define mmBMON_ADDRH_E1_OFFSET … #define mmBMON_ADDRL_S2_OFFSET … #define mmBMON_ADDRH_S2_OFFSET … #define mmBMON_ADDRL_E2_OFFSET … #define mmBMON_ADDRH_E2_OFFSET … #define mmBMON_ADDRL_S3_OFFSET … #define mmBMON_ADDRH_S3_OFFSET … #define mmBMON_ADDRL_E3_OFFSET … #define mmBMON_ADDRH_E3_OFFSET … #define mmBMON_REDUCTION_OFFSET … #define mmBMON_IDL_OFFSET … #define mmBMON_IDH_OFFSET … #define mmBMON_IDENL_OFFSET … #define mmBMON_IDENH_OFFSET … #define mmBMON_LATENCY_SMP_OFFSET … #define mmBMON_ATTR_OFFSET … #define mmBMON_ATTREN_OFFSET … #define mmBMON_USRENL_OFFSET … #define mmBMON_USRL_OFFSET … #define mmBMON_USRENH_OFFSET … #define mmBMON_USRH_OFFSET … #define mmBMON_CAPTURE_OFFSET … #define mmBMON_RELEASE_OFFSET … #define mmBMON_WIN_CAPTURE_OFFSET … #define mmBMON_BW_WIN_OFFSET … #define mmBMON_MATCH_CNT_SOD_OFFSET … #define mmBMON_MATCH_CNT_WIN_OFFSET … #define mmBMON_CYCCNT_L_OFFSET … #define mmBMON_CYCCNT_H_OFFSET … #define mmBMON_MAXLAT_SOD_OFFSET … #define mmBMON_MINLAT_SOD_OFFSET … #define mmBMON_MAXBW_SOD_OFFSET … #define mmBMON_MINBW_SOD_OFFSET … #define mmBMON_MAXOS_SOD_OFFSET … #define mmBMON_MINOS_SOD_OFFSET … #define mmBMON_ADDRL_SNAPSHOT_OFFSET … #define mmBMON_ADDRH_SNAPSHOT_OFFSET … #define mmBMON_IDL_SNAPSHOT_OFFSET … #define mmBMON_IDH_SNAPSHOT_OFFSET … #define mmBMON_ATTR_SNAPSHOT_OFFSET … #define mmBMON_STM_TRC_OFFSET … #define mmBMON_STM_TRC_DROP_OFFSET … #define mmBMON_DEVARCH_OFFSET … #define mmBMON_PMDEVID2_OFFSET … #define mmBMON_PMDEVID1_OFFSET … #define mmBMON_PMDEVID_OFFSET … #define mmBMON_DEVTYPE_OFFSET … #define mmBMON_PIDR4_OFFSET … #define mmBMON_PIDR5_OFFSET … #define mmBMON_PIDR6_OFFSET … #define mmBMON_PIDR7_OFFSET … #define mmBMON_PIDR0_OFFSET … #define mmBMON_PIDR1_OFFSET … #define mmBMON_PIDR2_OFFSET … #define mmBMON_PIDR3_OFFSET … #define mmBMON_CIDR0_OFFSET … #define mmBMON_CIDR1_OFFSET … #define mmBMON_CIDR2_OFFSET … #define mmBMON_CIDR3_OFFSET … /* Coresight unlock offset */ #define mmCORESIGHT_UNLOCK_REGISTER_OFFSET … #define mmCORESIGHT_UNLOCK_STATUS_REGISTER_OFFSET … #endif /* GAUDI2_CORESIGHT_REGS_DRV_H_ */
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