#ifndef GAUDI2_REG_MAP_H_
#define GAUDI2_REG_MAP_H_
#define mmHW_STATE …
#define mmPID_STATUS_REG …
#define mmARM_STATUS_REG …
#define mmGIC_TPC_QM_IRQ_CTRL_POLL_REG …
#define mmGIC_MME_QM_IRQ_CTRL_POLL_REG …
#define mmGIC_DMA_QM_IRQ_CTRL_POLL_REG …
#define mmGIC_ROT_QM_IRQ_CTRL_POLL_REG …
#define mmGIC_NIC_QM_IRQ_CTRL_POLL_REG …
#define mmGIC_DMA_CR_IRQ_CTRL_POLL_REG …
#define mmGIC_HOST_PI_UPD_IRQ_POLL_REG …
#define mmGIC_HOST_HALT_IRQ_POLL_REG …
#define mmGIC_HOST_INTS_IRQ_POLL_REG …
#define mmGIC_HOST_SOFT_RST_IRQ_POLL_REG …
#define mmCPU_RST_STATUS_TO_HOST …
#define mmENGINE_ARC_IRQ_CTRL_POLL_REG …
#define mmPID_CFG_REG …
#define mmGIC_RAZWI_STATUS_REG …
#define mmCPU_BOOT_DEV_STS0 …
#define mmCPU_BOOT_DEV_STS1 …
#define mmCPU_CMD_STATUS_TO_HOST …
#define mmCPU_BOOT_ERR0 …
#define mmCPU_BOOT_ERR1 …
#define mmUPD_STS …
#define mmUPD_CMD …
#define mmPPBOOT_VER_OFFSET …
#define mmRDWR_TEST …
#define mmBTL_ID …
#define mmRST_SRC …
#define mmCOLD_RST_DATA …
#define mmUPD_PENDING_STS …
#define mmPID_CMD_REQ_REG …
#define mmPID_CMD_REQ_REG_HI …
#define mmPID_CMD_RSP_REG …
#define mmPID_CMD_RSP_REG_HI …
#define mmPID_CMD_TELEMETRY_REG_0 …
#define mmPID_CMD_TELEMETRY_REG_0_HI …
#define mmPID_CMD_TELEMETRY_REG_1 …
#define mmPID_CMD_TELEMETRY_REG_1_HI …
#define mmWD_GPIO_OUTSET_REG …
#define mmWD_GPIO_DATAOUT_REG …
#define mmSTM_PROFILER_SPE_REG …
#define mmARM_MSG_BOOT_ERR_SET …
#define mmARM_MSG_BOOT_ERR_CLR …
#define mmARM_MSG_BOOT_DEV_STS_SET …
#define mmARM_MSG_BOOT_DEV_STS_CLR …
#define mmMGMT_MSG_BOOT_ERR …
#define mmMGMT_MSG_BOOT_DEV_STS …
#endif