/* SPDX-License-Identifier: GPL-2.0-only */ /* * linux/sound/cs42l42.h -- Platform data for CS42L42 ALSA SoC audio driver header * * Copyright 2016-2022 Cirrus Logic, Inc. * * Author: James Schulman <[email protected]> * Author: Brian Austin <[email protected]> * Author: Michael White <[email protected]> */ #ifndef __CS42L42_H #define __CS42L42_H #define CS42L42_PAGE_REGISTER … #define CS42L42_WIN_START … #define CS42L42_WIN_LEN … #define CS42L42_RANGE_MIN … #define CS42L42_RANGE_MAX … #define CS42L42_PAGE_10 … #define CS42L42_PAGE_11 … #define CS42L42_PAGE_12 … #define CS42L42_PAGE_13 … #define CS42L42_PAGE_15 … #define CS42L42_PAGE_19 … #define CS42L42_PAGE_1B … #define CS42L42_PAGE_1C … #define CS42L42_PAGE_1D … #define CS42L42_PAGE_1F … #define CS42L42_PAGE_20 … #define CS42L42_PAGE_21 … #define CS42L42_PAGE_23 … #define CS42L42_PAGE_24 … #define CS42L42_PAGE_25 … #define CS42L42_PAGE_26 … #define CS42L42_PAGE_27 … #define CS42L42_PAGE_28 … #define CS42L42_PAGE_29 … #define CS42L42_PAGE_2A … #define CS42L42_PAGE_30 … #define CS42L42_CHIP_ID … #define CS42L83_CHIP_ID … /* Page 0x10 Global Registers */ #define CS42L42_DEVID_AB … #define CS42L42_DEVID_CD … #define CS42L42_DEVID_E … #define CS42L42_FABID … #define CS42L42_REVID … #define CS42L42_FRZ_CTL … #define CS42L42_SRC_CTL … #define CS42L42_SRC_BYPASS_DAC_SHIFT … #define CS42L42_SRC_BYPASS_DAC_MASK … #define CS42L42_MCLK_STATUS … #define CS42L42_MCLK_CTL … #define CS42L42_INTERNAL_FS_SHIFT … #define CS42L42_INTERNAL_FS_MASK … #define CS42L42_SFTRAMP_RATE … #define CS42L42_SLOW_START_ENABLE … #define CS42L42_SLOW_START_EN_MASK … #define CS42L42_SLOW_START_EN_SHIFT … #define CS42L42_I2C_DEBOUNCE … #define CS42L42_I2C_STRETCH … #define CS42L42_I2C_TIMEOUT … /* Page 0x11 Power and Headset Detect Registers */ #define CS42L42_PWR_CTL1 … #define CS42L42_ASP_DAO_PDN_SHIFT … #define CS42L42_ASP_DAO_PDN_MASK … #define CS42L42_ASP_DAI_PDN_SHIFT … #define CS42L42_ASP_DAI_PDN_MASK … #define CS42L42_MIXER_PDN_SHIFT … #define CS42L42_MIXER_PDN_MASK … #define CS42L42_EQ_PDN_SHIFT … #define CS42L42_EQ_PDN_MASK … #define CS42L42_HP_PDN_SHIFT … #define CS42L42_HP_PDN_MASK … #define CS42L42_ADC_PDN_SHIFT … #define CS42L42_ADC_PDN_MASK … #define CS42L42_PDN_ALL_SHIFT … #define CS42L42_PDN_ALL_MASK … #define CS42L42_PWR_CTL2 … #define CS42L42_ADC_SRC_PDNB_SHIFT … #define CS42L42_ADC_SRC_PDNB_MASK … #define CS42L42_DAC_SRC_PDNB_SHIFT … #define CS42L42_DAC_SRC_PDNB_MASK … #define CS42L42_ASP_DAI1_PDN_SHIFT … #define CS42L42_ASP_DAI1_PDN_MASK … #define CS42L42_SRC_PDN_OVERRIDE_SHIFT … #define CS42L42_SRC_PDN_OVERRIDE_MASK … #define CS42L42_DISCHARGE_FILT_SHIFT … #define CS42L42_DISCHARGE_FILT_MASK … #define CS42L42_PWR_CTL3 … #define CS42L42_RING_SENSE_PDNB_SHIFT … #define CS42L42_RING_SENSE_PDNB_MASK … #define CS42L42_VPMON_PDNB_SHIFT … #define CS42L42_VPMON_PDNB_MASK … #define CS42L42_SW_CLK_STP_STAT_SEL_SHIFT … #define CS42L42_SW_CLK_STP_STAT_SEL_MASK … #define CS42L42_RSENSE_CTL1 … #define CS42L42_RS_TRIM_R_SHIFT … #define CS42L42_RS_TRIM_R_MASK … #define CS42L42_RS_TRIM_T_SHIFT … #define CS42L42_RS_TRIM_T_MASK … #define CS42L42_HPREF_RS_SHIFT … #define CS42L42_HPREF_RS_MASK … #define CS42L42_HSBIAS_FILT_REF_RS_SHIFT … #define CS42L42_HSBIAS_FILT_REF_RS_MASK … #define CS42L42_RING_SENSE_PU_HIZ_SHIFT … #define CS42L42_RING_SENSE_PU_HIZ_MASK … #define CS42L42_RSENSE_CTL2 … #define CS42L42_TS_RS_GATE_SHIFT … #define CS42L42_TS_RS_GATE_MAS … #define CS42L42_OSC_SWITCH … #define CS42L42_SCLK_PRESENT_SHIFT … #define CS42L42_SCLK_PRESENT_MASK … #define CS42L42_OSC_SWITCH_STATUS … #define CS42L42_OSC_SW_SEL_STAT_SHIFT … #define CS42L42_OSC_SW_SEL_STAT_MASK … #define CS42L42_OSC_PDNB_STAT_SHIFT … #define CS42L42_OSC_PDNB_STAT_MASK … #define CS42L42_RSENSE_CTL3 … #define CS42L42_RS_RISE_DBNCE_TIME_SHIFT … #define CS42L42_RS_RISE_DBNCE_TIME_MASK … #define CS42L42_RS_FALL_DBNCE_TIME_SHIFT … #define CS42L42_RS_FALL_DBNCE_TIME_MASK … #define CS42L42_RS_PU_EN_SHIFT … #define CS42L42_RS_PU_EN_MASK … #define CS42L42_RS_INV_SHIFT … #define CS42L42_RS_INV_MASK … #define CS42L42_TSENSE_CTL … #define CS42L42_TS_RISE_DBNCE_TIME_SHIFT … #define CS42L42_TS_RISE_DBNCE_TIME_MASK … #define CS42L42_TS_FALL_DBNCE_TIME_SHIFT … #define CS42L42_TS_FALL_DBNCE_TIME_MASK … #define CS42L42_TS_INV_SHIFT … #define CS42L42_TS_INV_MASK … #define CS42L42_TSRS_INT_DISABLE … #define CS42L42_D_RS_PLUG_DBNC_SHIFT … #define CS42L42_D_RS_PLUG_DBNC_MASK … #define CS42L42_D_RS_UNPLUG_DBNC_SHIFT … #define CS42L42_D_RS_UNPLUG_DBNC_MASK … #define CS42L42_D_TS_PLUG_DBNC_SHIFT … #define CS42L42_D_TS_PLUG_DBNC_MASK … #define CS42L42_D_TS_UNPLUG_DBNC_SHIFT … #define CS42L42_D_TS_UNPLUG_DBNC_MASK … #define CS42L42_TRSENSE_STATUS … #define CS42L42_RS_PLUG_DBNC_SHIFT … #define CS42L42_RS_PLUG_DBNC_MASK … #define CS42L42_RS_UNPLUG_DBNC_SHIFT … #define CS42L42_RS_UNPLUG_DBNC_MASK … #define CS42L42_TS_PLUG_DBNC_SHIFT … #define CS42L42_TS_PLUG_DBNC_MASK … #define CS42L42_TS_UNPLUG_DBNC_SHIFT … #define CS42L42_TS_UNPLUG_DBNC_MASK … #define CS42L42_HSDET_CTL1 … #define CS42L42_HSDET_COMP1_LVL_SHIFT … #define CS42L42_HSDET_COMP1_LVL_MASK … #define CS42L42_HSDET_COMP2_LVL_SHIFT … #define CS42L42_HSDET_COMP2_LVL_MASK … #define CS42L42_HSDET_COMP1_LVL_VAL … #define CS42L42_HSDET_COMP2_LVL_VAL … #define CS42L42_HSDET_COMP1_LVL_DEFAULT … #define CS42L42_HSDET_COMP2_LVL_DEFAULT … #define CS42L42_HSDET_CTL2 … #define CS42L42_HSDET_AUTO_TIME_SHIFT … #define CS42L42_HSDET_AUTO_TIME_MASK … #define CS42L42_HSBIAS_REF_SHIFT … #define CS42L42_HSBIAS_REF_MASK … #define CS42L42_HSDET_SET_SHIFT … #define CS42L42_HSDET_SET_MASK … #define CS42L42_HSDET_CTRL_SHIFT … #define CS42L42_HSDET_CTRL_MASK … #define CS42L42_HS_SWITCH_CTL … #define CS42L42_SW_GNDHS_HS4_SHIFT … #define CS42L42_SW_GNDHS_HS4_MASK … #define CS42L42_SW_GNDHS_HS3_SHIFT … #define CS42L42_SW_GNDHS_HS3_MASK … #define CS42L42_SW_HSB_HS4_SHIFT … #define CS42L42_SW_HSB_HS4_MASK … #define CS42L42_SW_HSB_HS3_SHIFT … #define CS42L42_SW_HSB_HS3_MASK … #define CS42L42_SW_HSB_FILT_HS4_SHIFT … #define CS42L42_SW_HSB_FILT_HS4_MASK … #define CS42L42_SW_HSB_FILT_HS3_SHIFT … #define CS42L42_SW_HSB_FILT_HS3_MASK … #define CS42L42_SW_REF_HS4_SHIFT … #define CS42L42_SW_REF_HS4_MASK … #define CS42L42_SW_REF_HS3_SHIFT … #define CS42L42_SW_REF_HS3_MASK … #define CS42L42_HS_DET_STATUS … #define CS42L42_HSDET_TYPE_SHIFT … #define CS42L42_HSDET_TYPE_MASK … #define CS42L42_HSDET_COMP1_OUT_SHIFT … #define CS42L42_HSDET_COMP1_OUT_MASK … #define CS42L42_HSDET_COMP2_OUT_SHIFT … #define CS42L42_HSDET_COMP2_OUT_MASK … #define CS42L42_PLUG_CTIA … #define CS42L42_PLUG_OMTP … #define CS42L42_PLUG_HEADPHONE … #define CS42L42_PLUG_INVALID … #define CS42L42_HSDET_SW_COMP1 … #define CS42L42_HSDET_SW_COMP2 … #define CS42L42_HSDET_SW_TYPE1 … #define CS42L42_HSDET_SW_TYPE2 … #define CS42L42_HSDET_SW_TYPE3 … #define CS42L42_HSDET_SW_TYPE4 … #define CS42L42_HSDET_COMP_TYPE1 … #define CS42L42_HSDET_COMP_TYPE2 … #define CS42L42_HSDET_COMP_TYPE3 … #define CS42L42_HSDET_COMP_TYPE4 … #define CS42L42_HS_CLAMP_DISABLE … #define CS42L42_HS_CLAMP_DISABLE_SHIFT … #define CS42L42_HS_CLAMP_DISABLE_MASK … /* Page 0x12 Clocking Registers */ #define CS42L42_MCLK_SRC_SEL … #define CS42L42_MCLKDIV_SHIFT … #define CS42L42_MCLKDIV_MASK … #define CS42L42_MCLK_SRC_SEL_SHIFT … #define CS42L42_MCLK_SRC_SEL_MASK … #define CS42L42_SPDIF_CLK_CFG … #define CS42L42_FSYNC_PW_LOWER … #define CS42L42_FSYNC_PW_UPPER … #define CS42L42_FSYNC_PULSE_WIDTH_SHIFT … #define CS42L42_FSYNC_PULSE_WIDTH_MASK … #define CS42L42_FSYNC_P_LOWER … #define CS42L42_FSYNC_P_UPPER … #define CS42L42_FSYNC_PERIOD_SHIFT … #define CS42L42_FSYNC_PERIOD_MASK … #define CS42L42_ASP_CLK_CFG … #define CS42L42_ASP_SCLK_EN_SHIFT … #define CS42L42_ASP_SCLK_EN_MASK … #define CS42L42_ASP_MASTER_MODE … #define CS42L42_ASP_SLAVE_MODE … #define CS42L42_ASP_MODE_SHIFT … #define CS42L42_ASP_MODE_MASK … #define CS42L42_ASP_SCPOL_SHIFT … #define CS42L42_ASP_SCPOL_MASK … #define CS42L42_ASP_SCPOL_NOR … #define CS42L42_ASP_LCPOL_SHIFT … #define CS42L42_ASP_LCPOL_MASK … #define CS42L42_ASP_LCPOL_INV … #define CS42L42_ASP_FRM_CFG … #define CS42L42_ASP_STP_SHIFT … #define CS42L42_ASP_STP_MASK … #define CS42L42_ASP_5050_SHIFT … #define CS42L42_ASP_5050_MASK … #define CS42L42_ASP_FSD_SHIFT … #define CS42L42_ASP_FSD_MASK … #define CS42L42_ASP_FSD_0_5 … #define CS42L42_ASP_FSD_1_0 … #define CS42L42_ASP_FSD_1_5 … #define CS42L42_ASP_FSD_2_0 … #define CS42L42_FS_RATE_EN … #define CS42L42_FS_EN_SHIFT … #define CS42L42_FS_EN_MASK … #define CS42L42_FS_EN_IASRC_96K … #define CS42L42_FS_EN_OASRC_96K … #define CS42L42_IN_ASRC_CLK … #define CS42L42_CLK_IASRC_SEL_SHIFT … #define CS42L42_CLK_IASRC_SEL_MASK … #define CS42L42_CLK_IASRC_SEL_6 … #define CS42L42_CLK_IASRC_SEL_12 … #define CS42L42_OUT_ASRC_CLK … #define CS42L42_CLK_OASRC_SEL_SHIFT … #define CS42L42_CLK_OASRC_SEL_MASK … #define CS42L42_CLK_OASRC_SEL_12 … #define CS42L42_PLL_DIV_CFG1 … #define CS42L42_SCLK_PREDIV_SHIFT … #define CS42L42_SCLK_PREDIV_MASK … /* Page 0x13 Interrupt Registers */ /* Interrupts */ #define CS42L42_ADC_OVFL_STATUS … #define CS42L42_MIXER_STATUS … #define CS42L42_SRC_STATUS … #define CS42L42_ASP_RX_STATUS … #define CS42L42_ASP_TX_STATUS … #define CS42L42_CODEC_STATUS … #define CS42L42_DET_INT_STATUS1 … #define CS42L42_DET_INT_STATUS2 … #define CS42L42_SRCPL_INT_STATUS … #define CS42L42_VPMON_STATUS … #define CS42L42_PLL_LOCK_STATUS … #define CS42L42_TSRS_PLUG_STATUS … /* Masks */ #define CS42L42_ADC_OVFL_INT_MASK … #define CS42L42_ADC_OVFL_SHIFT … #define CS42L42_ADC_OVFL_MASK … #define CS42L42_ADC_OVFL_VAL_MASK … #define CS42L42_MIXER_INT_MASK … #define CS42L42_MIX_CHB_OVFL_SHIFT … #define CS42L42_MIX_CHB_OVFL_MASK … #define CS42L42_MIX_CHA_OVFL_SHIFT … #define CS42L42_MIX_CHA_OVFL_MASK … #define CS42L42_EQ_OVFL_SHIFT … #define CS42L42_EQ_OVFL_MASK … #define CS42L42_EQ_BIQUAD_OVFL_SHIFT … #define CS42L42_EQ_BIQUAD_OVFL_MASK … #define CS42L42_MIXER_VAL_MASK … #define CS42L42_SRC_INT_MASK … #define CS42L42_SRC_ILK_SHIFT … #define CS42L42_SRC_ILK_MASK … #define CS42L42_SRC_OLK_SHIFT … #define CS42L42_SRC_OLK_MASK … #define CS42L42_SRC_IUNLK_SHIFT … #define CS42L42_SRC_IUNLK_MASK … #define CS42L42_SRC_OUNLK_SHIFT … #define CS42L42_SRC_OUNLK_MASK … #define CS42L42_SRC_VAL_MASK … #define CS42L42_ASP_RX_INT_MASK … #define CS42L42_ASPRX_NOLRCK_SHIFT … #define CS42L42_ASPRX_NOLRCK_MASK … #define CS42L42_ASPRX_EARLY_SHIFT … #define CS42L42_ASPRX_EARLY_MASK … #define CS42L42_ASPRX_LATE_SHIFT … #define CS42L42_ASPRX_LATE_MASK … #define CS42L42_ASPRX_ERROR_SHIFT … #define CS42L42_ASPRX_ERROR_MASK … #define CS42L42_ASPRX_OVLD_SHIFT … #define CS42L42_ASPRX_OVLD_MASK … #define CS42L42_ASP_RX_VAL_MASK … #define CS42L42_ASP_TX_INT_MASK … #define CS42L42_ASPTX_NOLRCK_SHIFT … #define CS42L42_ASPTX_NOLRCK_MASK … #define CS42L42_ASPTX_EARLY_SHIFT … #define CS42L42_ASPTX_EARLY_MASK … #define CS42L42_ASPTX_LATE_SHIFT … #define CS42L42_ASPTX_LATE_MASK … #define CS42L42_ASPTX_SMERROR_SHIFT … #define CS42L42_ASPTX_SMERROR_MASK … #define CS42L42_ASP_TX_VAL_MASK … #define CS42L42_CODEC_INT_MASK … #define CS42L42_PDN_DONE_SHIFT … #define CS42L42_PDN_DONE_MASK … #define CS42L42_HSDET_AUTO_DONE_SHIFT … #define CS42L42_HSDET_AUTO_DONE_MASK … #define CS42L42_CODEC_VAL_MASK … #define CS42L42_SRCPL_INT_MASK … #define CS42L42_SRCPL_ADC_LK_SHIFT … #define CS42L42_SRCPL_ADC_LK_MASK … #define CS42L42_SRCPL_DAC_LK_SHIFT … #define CS42L42_SRCPL_DAC_LK_MASK … #define CS42L42_SRCPL_ADC_UNLK_SHIFT … #define CS42L42_SRCPL_ADC_UNLK_MASK … #define CS42L42_SRCPL_DAC_UNLK_SHIFT … #define CS42L42_SRCPL_DAC_UNLK_MASK … #define CS42L42_SRCPL_VAL_MASK … #define CS42L42_VPMON_INT_MASK … #define CS42L42_VPMON_SHIFT … #define CS42L42_VPMON_MASK … #define CS42L42_VPMON_VAL_MASK … #define CS42L42_PLL_LOCK_INT_MASK … #define CS42L42_PLL_LOCK_SHIFT … #define CS42L42_PLL_LOCK_MASK … #define CS42L42_PLL_LOCK_VAL_MASK … #define CS42L42_TSRS_PLUG_INT_MASK … #define CS42L42_RS_PLUG_SHIFT … #define CS42L42_RS_PLUG_MASK … #define CS42L42_RS_UNPLUG_SHIFT … #define CS42L42_RS_UNPLUG_MASK … #define CS42L42_TS_PLUG_SHIFT … #define CS42L42_TS_PLUG_MASK … #define CS42L42_TS_UNPLUG_SHIFT … #define CS42L42_TS_UNPLUG_MASK … #define CS42L42_TSRS_PLUG_VAL_MASK … #define CS42L42_TS_PLUG … #define CS42L42_TS_UNPLUG … #define CS42L42_TS_TRANS … /* * NOTE: PLL_START must be 0 while both ADC_PDN=1 and HP_PDN=1. * Otherwise it will prevent FILT+ from charging properly. */ #define CS42L42_PLL_CTL1 … #define CS42L42_PLL_START_SHIFT … #define CS42L42_PLL_START_MASK … #define CS42L42_PLL_DIV_FRAC0 … #define CS42L42_PLL_DIV_FRAC_SHIFT … #define CS42L42_PLL_DIV_FRAC_MASK … #define CS42L42_PLL_DIV_FRAC1 … #define CS42L42_PLL_DIV_FRAC2 … #define CS42L42_PLL_DIV_INT … #define CS42L42_PLL_DIV_INT_SHIFT … #define CS42L42_PLL_DIV_INT_MASK … #define CS42L42_PLL_CTL3 … #define CS42L42_PLL_DIVOUT_SHIFT … #define CS42L42_PLL_DIVOUT_MASK … #define CS42L42_PLL_CAL_RATIO … #define CS42L42_PLL_CAL_RATIO_SHIFT … #define CS42L42_PLL_CAL_RATIO_MASK … #define CS42L42_PLL_CTL4 … #define CS42L42_PLL_MODE_SHIFT … #define CS42L42_PLL_MODE_MASK … /* Page 0x19 HP Load Detect Registers */ #define CS42L42_LOAD_DET_RCSTAT … #define CS42L42_RLA_STAT_SHIFT … #define CS42L42_RLA_STAT_MASK … #define CS42L42_RLA_STAT_15_OHM … #define CS42L42_LOAD_DET_DONE … #define CS42L42_HPLOAD_DET_DONE_SHIFT … #define CS42L42_HPLOAD_DET_DONE_MASK … #define CS42L42_LOAD_DET_EN … #define CS42L42_HP_LD_EN_SHIFT … #define CS42L42_HP_LD_EN_MASK … /* Page 0x1B Headset Interface Registers */ #define CS42L42_HSBIAS_SC_AUTOCTL … #define CS42L42_HSBIAS_SENSE_TRIP_SHIFT … #define CS42L42_HSBIAS_SENSE_TRIP_MASK … #define CS42L42_TIP_SENSE_EN_SHIFT … #define CS42L42_TIP_SENSE_EN_MASK … #define CS42L42_AUTO_HSBIAS_HIZ_SHIFT … #define CS42L42_AUTO_HSBIAS_HIZ_MASK … #define CS42L42_HSBIAS_SENSE_EN_SHIFT … #define CS42L42_HSBIAS_SENSE_EN_MASK … #define CS42L42_WAKE_CTL … #define CS42L42_WAKEB_CLEAR_SHIFT … #define CS42L42_WAKEB_CLEAR_MASK … #define CS42L42_WAKEB_MODE_SHIFT … #define CS42L42_WAKEB_MODE_MASK … #define CS42L42_M_HP_WAKE_SHIFT … #define CS42L42_M_HP_WAKE_MASK … #define CS42L42_M_MIC_WAKE_SHIFT … #define CS42L42_M_MIC_WAKE_MASK … #define CS42L42_ADC_DISABLE_MUTE … #define CS42L42_ADC_DISABLE_S0_MUTE_SHIFT … #define CS42L42_ADC_DISABLE_S0_MUTE_MASK … #define CS42L42_TIPSENSE_CTL … #define CS42L42_TIP_SENSE_DEBOUNCE_SHIFT … #define CS42L42_TIP_SENSE_DEBOUNCE_MASK … #define CS42L42_TIP_SENSE_INV_SHIFT … #define CS42L42_TIP_SENSE_INV_MASK … #define CS42L42_TIP_SENSE_CTRL_SHIFT … #define CS42L42_TIP_SENSE_CTRL_MASK … /* * NOTE: DETECT_MODE must be 0 while both ADC_PDN=1 and HP_PDN=1. * Otherwise it will prevent FILT+ from charging properly. */ #define CS42L42_MISC_DET_CTL … #define CS42L42_PDN_MIC_LVL_DET_SHIFT … #define CS42L42_PDN_MIC_LVL_DET_MASK … #define CS42L42_HSBIAS_CTL_SHIFT … #define CS42L42_HSBIAS_CTL_MASK … #define CS42L42_DETECT_MODE_SHIFT … #define CS42L42_DETECT_MODE_MASK … #define CS42L42_MIC_DET_CTL1 … #define CS42L42_HS_DET_LEVEL_SHIFT … #define CS42L42_HS_DET_LEVEL_MASK … #define CS42L42_EVENT_STAT_SEL_SHIFT … #define CS42L42_EVENT_STAT_SEL_MASK … #define CS42L42_LATCH_TO_VP_SHIFT … #define CS42L42_LATCH_TO_VP_MASK … #define CS42L42_MIC_DET_CTL2 … #define CS42L42_DEBOUNCE_TIME_SHIFT … #define CS42L42_DEBOUNCE_TIME_MASK … #define CS42L42_DET_STATUS1 … #define CS42L42_HSBIAS_HIZ_MODE_SHIFT … #define CS42L42_HSBIAS_HIZ_MODE_MASK … #define CS42L42_TIP_SENSE_SHIFT … #define CS42L42_TIP_SENSE_MASK … #define CS42L42_DET_STATUS2 … #define CS42L42_SHORT_TRUE_SHIFT … #define CS42L42_SHORT_TRUE_MASK … #define CS42L42_HS_TRUE_SHIFT … #define CS42L42_HS_TRUE_MASK … #define CS42L42_DET_INT1_MASK … #define CS42L42_TIP_SENSE_UNPLUG_SHIFT … #define CS42L42_TIP_SENSE_UNPLUG_MASK … #define CS42L42_TIP_SENSE_PLUG_SHIFT … #define CS42L42_TIP_SENSE_PLUG_MASK … #define CS42L42_HSBIAS_SENSE_SHIFT … #define CS42L42_HSBIAS_SENSE_MASK … #define CS42L42_DET_INT_VAL1_MASK … #define CS42L42_DET_INT2_MASK … #define CS42L42_M_SHORT_DET_SHIFT … #define CS42L42_M_SHORT_DET_MASK … #define CS42L42_M_SHORT_RLS_SHIFT … #define CS42L42_M_SHORT_RLS_MASK … #define CS42L42_M_HSBIAS_HIZ_SHIFT … #define CS42L42_M_HSBIAS_HIZ_MASK … #define CS42L42_M_DETECT_FT_SHIFT … #define CS42L42_M_DETECT_FT_MASK … #define CS42L42_M_DETECT_TF_SHIFT … #define CS42L42_M_DETECT_TF_MASK … #define CS42L42_DET_INT_VAL2_MASK … /* Page 0x1C Headset Bias Registers */ #define CS42L42_HS_BIAS_CTL … #define CS42L42_HSBIAS_RAMP_SHIFT … #define CS42L42_HSBIAS_RAMP_MASK … #define CS42L42_HSBIAS_PD_SHIFT … #define CS42L42_HSBIAS_PD_MASK … #define CS42L42_HSBIAS_CAPLESS_SHIFT … #define CS42L42_HSBIAS_CAPLESS_MASK … /* Page 0x1D ADC Registers */ #define CS42L42_ADC_CTL … #define CS42L42_ADC_NOTCH_DIS_SHIFT … #define CS42L42_ADC_FORCE_WEAK_VCM_SHIFT … #define CS42L42_ADC_INV_SHIFT … #define CS42L42_ADC_DIG_BOOST_SHIFT … #define CS42L42_ADC_VOLUME … #define CS42L42_ADC_VOL_SHIFT … #define CS42L42_ADC_WNF_HPF_CTL … #define CS42L42_ADC_WNF_CF_SHIFT … #define CS42L42_ADC_WNF_EN_SHIFT … #define CS42L42_ADC_HPF_CF_SHIFT … #define CS42L42_ADC_HPF_EN_SHIFT … /* Page 0x1F DAC Registers */ #define CS42L42_DAC_CTL1 … #define CS42L42_DACB_INV_SHIFT … #define CS42L42_DACA_INV_SHIFT … #define CS42L42_DAC_CTL2 … #define CS42L42_HPOUT_PULLDOWN_SHIFT … #define CS42L42_HPOUT_PULLDOWN_MASK … #define CS42L42_HPOUT_LOAD_SHIFT … #define CS42L42_HPOUT_LOAD_MASK … #define CS42L42_HPOUT_CLAMP_SHIFT … #define CS42L42_HPOUT_CLAMP_MASK … #define CS42L42_DAC_HPF_EN_SHIFT … #define CS42L42_DAC_HPF_EN_MASK … #define CS42L42_DAC_MON_EN_SHIFT … #define CS42L42_DAC_MON_EN_MASK … /* Page 0x20 HP CTL Registers */ #define CS42L42_HP_CTL … #define CS42L42_HP_ANA_BMUTE_SHIFT … #define CS42L42_HP_ANA_BMUTE_MASK … #define CS42L42_HP_ANA_AMUTE_SHIFT … #define CS42L42_HP_ANA_AMUTE_MASK … #define CS42L42_HP_FULL_SCALE_VOL_SHIFT … #define CS42L42_HP_FULL_SCALE_VOL_MASK … /* Page 0x21 Class H Registers */ #define CS42L42_CLASSH_CTL … /* Page 0x23 Mixer Volume Registers */ #define CS42L42_MIXER_CHA_VOL … #define CS42L42_MIXER_ADC_VOL … #define CS42L42_MIXER_CHB_VOL … #define CS42L42_MIXER_CH_VOL_SHIFT … #define CS42L42_MIXER_CH_VOL_MASK … /* Page 0x24 EQ Registers */ #define CS42L42_EQ_COEF_IN0 … #define CS42L42_EQ_COEF_IN1 … #define CS42L42_EQ_COEF_IN2 … #define CS42L42_EQ_COEF_IN3 … #define CS42L42_EQ_COEF_RW … #define CS42L42_EQ_COEF_OUT0 … #define CS42L42_EQ_COEF_OUT1 … #define CS42L42_EQ_COEF_OUT2 … #define CS42L42_EQ_COEF_OUT3 … #define CS42L42_EQ_INIT_STAT … #define CS42L42_EQ_START_FILT … #define CS42L42_EQ_MUTE_CTL … /* Page 0x25 Audio Port Registers */ #define CS42L42_SP_RX_CH_SEL … #define CS42L42_SP_RX_CHB_SEL_SHIFT … #define CS42L42_SP_RX_CHB_SEL_MASK … #define CS42L42_SP_RX_ISOC_CTL … #define CS42L42_SP_RX_RSYNC_SHIFT … #define CS42L42_SP_RX_RSYNC_MASK … #define CS42L42_SP_RX_NSB_POS_SHIFT … #define CS42L42_SP_RX_NSB_POS_MASK … #define CS42L42_SP_RX_NFS_NSBB_SHIFT … #define CS42L42_SP_RX_NFS_NSBB_MASK … #define CS42L42_SP_RX_ISOC_MODE_SHIFT … #define CS42L42_SP_RX_ISOC_MODE_MASK … #define CS42L42_SP_RX_FS … #define CS42l42_SPDIF_CH_SEL … #define CS42L42_SP_TX_ISOC_CTL … #define CS42L42_SP_TX_FS … #define CS42L42_SPDIF_SW_CTL1 … /* Page 0x26 SRC Registers */ #define CS42L42_SRC_SDIN_FS … #define CS42L42_SRC_SDIN_FS_SHIFT … #define CS42L42_SRC_SDIN_FS_MASK … #define CS42L42_SRC_SDOUT_FS … /* Page 0x27 DMA */ #define CS42L42_SOFT_RESET_REBOOT … #define CS42L42_SFT_RST_REBOOT_MASK … /* Page 0x28 S/PDIF Registers */ #define CS42L42_SPDIF_CTL1 … #define CS42L42_SPDIF_CTL2 … #define CS42L42_SPDIF_CTL3 … #define CS42L42_SPDIF_CTL4 … /* Page 0x29 Serial Port TX Registers */ #define CS42L42_ASP_TX_SZ_EN … #define CS42L42_ASP_TX_EN_SHIFT … #define CS42L42_ASP_TX_CH_EN … #define CS42L42_ASP_TX0_CH2_SHIFT … #define CS42L42_ASP_TX0_CH1_SHIFT … #define CS42L42_ASP_TX_CH_AP_RES … #define CS42L42_ASP_TX_CH1_AP_SHIFT … #define CS42L42_ASP_TX_CH1_AP_MASK … #define CS42L42_ASP_TX_CH2_AP_SHIFT … #define CS42L42_ASP_TX_CH2_AP_MASK … #define CS42L42_ASP_TX_CH2_RES_SHIFT … #define CS42L42_ASP_TX_CH2_RES_MASK … #define CS42L42_ASP_TX_CH1_RES_SHIFT … #define CS42L42_ASP_TX_CH1_RES_MASK … #define CS42L42_ASP_TX_CH1_BIT_MSB … #define CS42L42_ASP_TX_CH1_BIT_LSB … #define CS42L42_ASP_TX_HIZ_DLY_CFG … #define CS42L42_ASP_TX_CH2_BIT_MSB … #define CS42L42_ASP_TX_CH2_BIT_LSB … /* Page 0x2A Serial Port RX Registers */ #define CS42L42_ASP_RX_DAI0_EN … #define CS42L42_ASP_RX0_CH_EN_SHIFT … #define CS42L42_ASP_RX0_CH_EN_MASK … #define CS42L42_ASP_RX0_CH1_SHIFT … #define CS42L42_ASP_RX0_CH2_SHIFT … #define CS42L42_ASP_RX0_CH3_SHIFT … #define CS42L42_ASP_RX0_CH4_SHIFT … #define CS42L42_ASP_RX_DAI0_CH1_AP_RES … #define CS42L42_ASP_RX_DAI0_CH1_BIT_MSB … #define CS42L42_ASP_RX_DAI0_CH1_BIT_LSB … #define CS42L42_ASP_RX_DAI0_CH2_AP_RES … #define CS42L42_ASP_RX_DAI0_CH2_BIT_MSB … #define CS42L42_ASP_RX_DAI0_CH2_BIT_LSB … #define CS42L42_ASP_RX_DAI0_CH3_AP_RES … #define CS42L42_ASP_RX_DAI0_CH3_BIT_MSB … #define CS42L42_ASP_RX_DAI0_CH3_BIT_LSB … #define CS42L42_ASP_RX_DAI0_CH4_AP_RES … #define CS42L42_ASP_RX_DAI0_CH4_BIT_MSB … #define CS42L42_ASP_RX_DAI0_CH4_BIT_LSB … #define CS42L42_ASP_RX_DAI1_CH1_AP_RES … #define CS42L42_ASP_RX_DAI1_CH1_BIT_MSB … #define CS42L42_ASP_RX_DAI1_CH1_BIT_LSB … #define CS42L42_ASP_RX_DAI1_CH2_AP_RES … #define CS42L42_ASP_RX_DAI1_CH2_BIT_MSB … #define CS42L42_ASP_RX_DAI1_CH2_BIT_LSB … #define CS42L42_ASP_RX_CH_AP_SHIFT … #define CS42L42_ASP_RX_CH_AP_MASK … #define CS42L42_ASP_RX_CH_AP_LOW … #define CS42L42_ASP_RX_CH_AP_HI … #define CS42L42_ASP_RX_CH_RES_SHIFT … #define CS42L42_ASP_RX_CH_RES_MASK … #define CS42L42_ASP_RX_CH_RES_32 … #define CS42L42_ASP_RX_CH_RES_16 … #define CS42L42_ASP_RX_CH_BIT_ST_SHIFT … #define CS42L42_ASP_RX_CH_BIT_ST_MASK … /* Page 0x30 ID Registers */ #define CS42L42_SUB_REVID … #define CS42L42_MAX_REGISTER … /* Defines for fracturing values spread across multiple registers */ #define CS42L42_FRAC0_VAL(val) … #define CS42L42_FRAC1_VAL(val) … #define CS42L42_FRAC2_VAL(val) … #define CS42L42_NUM_SUPPLIES … #define CS42L42_BOOT_TIME_US … #define CS42L42_PLL_DIVOUT_TIME_US … #define CS42L42_CLOCK_SWITCH_DELAY_US … #define CS42L42_PLL_LOCK_POLL_US … #define CS42L42_PLL_LOCK_TIMEOUT_US … #define CS42L42_HP_ADC_EN_TIME_US … #define CS42L42_PDN_DONE_POLL_US … #define CS42L42_PDN_DONE_TIMEOUT_US … #define CS42L42_PDN_DONE_TIME_MS … #endif /* __CS42L42_H */
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