// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2018, The Linux Foundation. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H #define _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H /* CAM_CC clock registers */ #define CAM_CC_BPS_AHB_CLK … #define CAM_CC_BPS_AREG_CLK … #define CAM_CC_BPS_AXI_CLK … #define CAM_CC_BPS_CLK … #define CAM_CC_BPS_CLK_SRC … #define CAM_CC_CAMNOC_ATB_CLK … #define CAM_CC_CAMNOC_AXI_CLK … #define CAM_CC_CCI_CLK … #define CAM_CC_CCI_CLK_SRC … #define CAM_CC_CPAS_AHB_CLK … #define CAM_CC_CPHY_RX_CLK_SRC … #define CAM_CC_CSI0PHYTIMER_CLK … #define CAM_CC_CSI0PHYTIMER_CLK_SRC … #define CAM_CC_CSI1PHYTIMER_CLK … #define CAM_CC_CSI1PHYTIMER_CLK_SRC … #define CAM_CC_CSI2PHYTIMER_CLK … #define CAM_CC_CSI2PHYTIMER_CLK_SRC … #define CAM_CC_CSI3PHYTIMER_CLK … #define CAM_CC_CSI3PHYTIMER_CLK_SRC … #define CAM_CC_CSIPHY0_CLK … #define CAM_CC_CSIPHY1_CLK … #define CAM_CC_CSIPHY2_CLK … #define CAM_CC_CSIPHY3_CLK … #define CAM_CC_FAST_AHB_CLK_SRC … #define CAM_CC_FD_CORE_CLK … #define CAM_CC_FD_CORE_CLK_SRC … #define CAM_CC_FD_CORE_UAR_CLK … #define CAM_CC_ICP_APB_CLK … #define CAM_CC_ICP_ATB_CLK … #define CAM_CC_ICP_CLK … #define CAM_CC_ICP_CLK_SRC … #define CAM_CC_ICP_CTI_CLK … #define CAM_CC_ICP_TS_CLK … #define CAM_CC_IFE_0_AXI_CLK … #define CAM_CC_IFE_0_CLK … #define CAM_CC_IFE_0_CLK_SRC … #define CAM_CC_IFE_0_CPHY_RX_CLK … #define CAM_CC_IFE_0_CSID_CLK … #define CAM_CC_IFE_0_CSID_CLK_SRC … #define CAM_CC_IFE_0_DSP_CLK … #define CAM_CC_IFE_1_AXI_CLK … #define CAM_CC_IFE_1_CLK … #define CAM_CC_IFE_1_CLK_SRC … #define CAM_CC_IFE_1_CPHY_RX_CLK … #define CAM_CC_IFE_1_CSID_CLK … #define CAM_CC_IFE_1_CSID_CLK_SRC … #define CAM_CC_IFE_1_DSP_CLK … #define CAM_CC_IFE_LITE_CLK … #define CAM_CC_IFE_LITE_CLK_SRC … #define CAM_CC_IFE_LITE_CPHY_RX_CLK … #define CAM_CC_IFE_LITE_CSID_CLK … #define CAM_CC_IFE_LITE_CSID_CLK_SRC … #define CAM_CC_IPE_0_AHB_CLK … #define CAM_CC_IPE_0_AREG_CLK … #define CAM_CC_IPE_0_AXI_CLK … #define CAM_CC_IPE_0_CLK … #define CAM_CC_IPE_0_CLK_SRC … #define CAM_CC_IPE_1_AHB_CLK … #define CAM_CC_IPE_1_AREG_CLK … #define CAM_CC_IPE_1_AXI_CLK … #define CAM_CC_IPE_1_CLK … #define CAM_CC_IPE_1_CLK_SRC … #define CAM_CC_JPEG_CLK … #define CAM_CC_JPEG_CLK_SRC … #define CAM_CC_LRME_CLK … #define CAM_CC_LRME_CLK_SRC … #define CAM_CC_MCLK0_CLK … #define CAM_CC_MCLK0_CLK_SRC … #define CAM_CC_MCLK1_CLK … #define CAM_CC_MCLK1_CLK_SRC … #define CAM_CC_MCLK2_CLK … #define CAM_CC_MCLK2_CLK_SRC … #define CAM_CC_MCLK3_CLK … #define CAM_CC_MCLK3_CLK_SRC … #define CAM_CC_PLL0 … #define CAM_CC_PLL0_OUT_EVEN … #define CAM_CC_PLL1 … #define CAM_CC_PLL1_OUT_EVEN … #define CAM_CC_PLL2 … #define CAM_CC_PLL2_OUT_EVEN … #define CAM_CC_PLL3 … #define CAM_CC_PLL3_OUT_EVEN … #define CAM_CC_SLOW_AHB_CLK_SRC … #define CAM_CC_SOC_AHB_CLK … #define CAM_CC_SYS_TMR_CLK … /* CAM_CC Resets */ #define TITAN_CAM_CC_CCI_BCR … #define TITAN_CAM_CC_CPAS_BCR … #define TITAN_CAM_CC_CSI0PHY_BCR … #define TITAN_CAM_CC_CSI1PHY_BCR … #define TITAN_CAM_CC_CSI2PHY_BCR … #define TITAN_CAM_CC_MCLK0_BCR … #define TITAN_CAM_CC_MCLK1_BCR … #define TITAN_CAM_CC_MCLK2_BCR … #define TITAN_CAM_CC_MCLK3_BCR … #define TITAN_CAM_CC_TITAN_TOP_BCR … /* CAM_CC GDSCRs */ #define BPS_GDSC … #define IPE_0_GDSC … #define IPE_1_GDSC … #define IFE_0_GDSC … #define IFE_1_GDSC … #define TITAN_TOP_GDSC … #endif
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