// SPDX-License-Identifier: GPL-2.0-or-later /* * ALSA driver for ICEnsemble VT1724 (Envy24HT) * * Lowlevel functions for Infrasonic Quartet * * Copyright (c) 2009 Pavel Hofman <[email protected]> */ #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/init.h> #include <linux/slab.h> #include <linux/string.h> #include <sound/core.h> #include <sound/tlv.h> #include <sound/info.h> #include "ice1712.h" #include "envy24ht.h" #include <sound/ak4113.h> #include "quartet.h" struct qtet_spec { … }; struct qtet_kcontrol_private { … }; enum { … }; static const char * const ext_clock_names[3] = …; /* chip address on I2C bus */ #define AK4113_ADDR … /* chip address on SPI bus */ #define AK4620_ADDR … /* * GPIO pins */ /* GPIO0 - O - DATA0, def. 0 */ #define GPIO_D0 … /* GPIO1 - I/O - DATA1, Jack Detect Input0 (0:present, 1:missing), def. 1 */ #define GPIO_D1_JACKDTC0 … /* GPIO2 - I/O - DATA2, Jack Detect Input1 (0:present, 1:missing), def. 1 */ #define GPIO_D2_JACKDTC1 … /* GPIO3 - I/O - DATA3, def. 1 */ #define GPIO_D3 … /* GPIO4 - I/O - DATA4, SPI CDTO, def. 1 */ #define GPIO_D4_SPI_CDTO … /* GPIO5 - I/O - DATA5, SPI CCLK, def. 1 */ #define GPIO_D5_SPI_CCLK … /* GPIO6 - I/O - DATA6, Cable Detect Input (0:detected, 1:not detected */ #define GPIO_D6_CD … /* GPIO7 - I/O - DATA7, Device Detect Input (0:detected, 1:not detected */ #define GPIO_D7_DD … /* GPIO8 - O - CPLD Chip Select, def. 1 */ #define GPIO_CPLD_CSN … /* GPIO9 - O - CPLD register read/write (0:write, 1:read), def. 0 */ #define GPIO_CPLD_RW … /* GPIO10 - O - SPI Chip Select for CODEC#0, def. 1 */ #define GPIO_SPI_CSN0 … /* GPIO11 - O - SPI Chip Select for CODEC#1, def. 1 */ #define GPIO_SPI_CSN1 … /* GPIO12 - O - Ex. Register Output Enable (0:enable, 1:disable), def. 1, * init 0 */ #define GPIO_EX_GPIOE … /* GPIO13 - O - Ex. Register0 Chip Select for System Control Register, * def. 1 */ #define GPIO_SCR … /* GPIO14 - O - Ex. Register1 Chip Select for Monitor Control Register, * def. 1 */ #define GPIO_MCR … #define GPIO_SPI_ALL … #define GPIO_DATA_MASK … /* System Control Register GPIO_SCR data bits */ /* Mic/Line select relay (0:line, 1:mic) */ #define SCR_RELAY … /* Phantom power drive control (0:5V, 1:48V) */ #define SCR_PHP_V … /* H/W mute control (0:Normal, 1:Mute) */ #define SCR_MUTE … /* Phantom power control (0:Phantom on, 1:off) */ #define SCR_PHP … /* Analog input 1/2 Source Select */ #define SCR_AIN12_SEL0 … #define SCR_AIN12_SEL1 … /* Analog input 3/4 Source Select (0:line, 1:hi-z) */ #define SCR_AIN34_SEL … /* Codec Power Down (0:power down, 1:normal) */ #define SCR_CODEC_PDN … #define SCR_AIN12_LINE … #define SCR_AIN12_MIC … #define SCR_AIN12_LOWCUT … /* Monitor Control Register GPIO_MCR data bits */ /* Input 1/2 to Monitor 1/2 (0:off, 1:on) */ #define MCR_IN12_MON12 … /* Input 1/2 to Monitor 3/4 (0:off, 1:on) */ #define MCR_IN12_MON34 … /* Input 3/4 to Monitor 1/2 (0:off, 1:on) */ #define MCR_IN34_MON12 … /* Input 3/4 to Monitor 3/4 (0:off, 1:on) */ #define MCR_IN34_MON34 … /* Output to Monitor 1/2 (0:off, 1:on) */ #define MCR_OUT34_MON12 … /* Output to Monitor 3/4 (0:off, 1:on) */ #define MCR_OUT12_MON34 … /* CPLD Register DATA bits */ /* Clock Rate Select */ #define CPLD_CKS0 … #define CPLD_CKS1 … #define CPLD_CKS2 … /* Sync Source Select (0:Internal, 1:External) */ #define CPLD_SYNC_SEL … /* Word Clock FS Select (0:FS, 1:256FS) */ #define CPLD_WORD_SEL … /* Coaxial Output Source (IS-Link) (0:SPDIF, 1:I2S) */ #define CPLD_COAX_OUT … /* Input 1/2 Source Select (0:Analog12, 1:An34) */ #define CPLD_IN12_SEL … /* Input 3/4 Source Select (0:Analog34, 1:Digital In) */ #define CPLD_IN34_SEL … /* internal clock (CPLD_SYNC_SEL = 0) options */ #define CPLD_CKS_44100HZ … #define CPLD_CKS_48000HZ … #define CPLD_CKS_88200HZ … #define CPLD_CKS_96000HZ … #define CPLD_CKS_176400HZ … #define CPLD_CKS_192000HZ … #define CPLD_CKS_MASK … /* external clock (CPLD_SYNC_SEL = 1) options */ /* external clock - SPDIF */ #define CPLD_EXT_SPDIF … /* external clock - WordClock 1xfs */ #define CPLD_EXT_WORDCLOCK_1FS … /* external clock - WordClock 256xfs */ #define CPLD_EXT_WORDCLOCK_256FS … #define EXT_SPDIF_TYPE … #define EXT_WORDCLOCK_1FS_TYPE … #define EXT_WORDCLOCK_256FS_TYPE … #define AK4620_DFS0 … #define AK4620_DFS1 … #define AK4620_CKS0 … #define AK4620_CKS1 … /* Clock and Format Control register */ #define AK4620_DFS_REG … /* Deem and Volume Control register */ #define AK4620_DEEMVOL_REG … #define AK4620_SMUTE … /* * Conversion from int value to its binary form. Used for debugging. * The output buffer must be allocated prior to calling the function. */ static char *get_binary(char *buffer, int value) { … } /* * Initial setup of the conversion array GPIO <-> rate */ static const unsigned int qtet_rates[] = …; static const unsigned int cks_vals[] = …; static const struct snd_pcm_hw_constraint_list qtet_rates_info = …; static void qtet_ak4113_write(void *private_data, unsigned char reg, unsigned char val) { … } static unsigned char qtet_ak4113_read(void *private_data, unsigned char reg) { … } /* * AK4620 section */ /* * Write data to addr register of ak4620 */ static void qtet_akm_write(struct snd_akm4xxx *ak, int chip, unsigned char addr, unsigned char data) { … } static void qtet_akm_set_regs(struct snd_akm4xxx *ak, unsigned char addr, unsigned char mask, unsigned char value) { … } /* * change the rate of AK4620 */ static void qtet_akm_set_rate_val(struct snd_akm4xxx *ak, unsigned int rate) { … } #define AK_CONTROL(xname, xch) … #define PCM_12_PLAYBACK_VOLUME … #define PCM_34_PLAYBACK_VOLUME … #define PCM_12_CAPTURE_VOLUME … #define PCM_34_CAPTURE_VOLUME … static const struct snd_akm4xxx_dac_channel qtet_dac[] = …; static const struct snd_akm4xxx_adc_channel qtet_adc[] = …; static const struct snd_akm4xxx akm_qtet_dac = …; /* Communication routines with the CPLD */ /* Writes data to external register reg, both reg and data are * GPIO representations */ static void reg_write(struct snd_ice1712 *ice, unsigned int reg, unsigned int data) { … } static unsigned int get_scr(struct snd_ice1712 *ice) { … } static unsigned int get_mcr(struct snd_ice1712 *ice) { … } static unsigned int get_cpld(struct snd_ice1712 *ice) { … } static void set_scr(struct snd_ice1712 *ice, unsigned int val) { … } static void set_mcr(struct snd_ice1712 *ice, unsigned int val) { … } static void set_cpld(struct snd_ice1712 *ice, unsigned int val) { … } static void proc_regs_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) { … } static void proc_init(struct snd_ice1712 *ice) { … } static int qtet_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int qtet_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int qtet_ain12_enum_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { … } static int qtet_ain12_sw_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int qtet_ain12_sw_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int qtet_php_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int qtet_php_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } #define PRIV_SW(xid, xbit, xreg) … #define PRIV_ENUM2(xid, xbit, xreg, xtext1, xtext2) … static const struct qtet_kcontrol_private qtet_privates[] = …; static int qtet_enum_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { … } static int qtet_sw_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int qtet_sw_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } #define qtet_sw_info … #define QTET_CONTROL(xname, xtype, xpriv) … static const struct snd_kcontrol_new qtet_controls[] = …; static const char * const follower_vols[] = …; static DECLARE_TLV_DB_SCALE(qtet_master_db_scale, -6350, 50, 1); static int qtet_add_controls(struct snd_ice1712 *ice) { … } static inline int qtet_is_spdif_master(struct snd_ice1712 *ice) { … } static unsigned int qtet_get_rate(struct snd_ice1712 *ice) { … } static int get_cks_val(int rate) { … } /* setting new rate */ static void qtet_set_rate(struct snd_ice1712 *ice, unsigned int rate) { … } static inline unsigned char qtet_set_mclk(struct snd_ice1712 *ice, unsigned int rate) { … } /* setting clock to external - SPDIF */ static int qtet_set_spdif_clock(struct snd_ice1712 *ice, int type) { … } static int qtet_get_spdif_master_type(struct snd_ice1712 *ice) { … } /* Called when ak4113 detects change in the input SPDIF stream */ static void qtet_ak4113_change(struct ak4113 *ak4113, unsigned char c0, unsigned char c1) { … } /* * If clock slaved to SPDIF-IN, setting runtime rate * to the detected external rate */ static void qtet_spdif_in_open(struct snd_ice1712 *ice, struct snd_pcm_substream *substream) { … } /* * initialize the chip */ static int qtet_init(struct snd_ice1712 *ice) { … } static const unsigned char qtet_eeprom[] = …; /* entry point */ struct snd_ice1712_card_info snd_vt1724_qtet_cards[] = …;
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