/* SPDX-License-Identifier: GPL-2.0 */ #ifndef OXYGEN_REGS_H_INCLUDED #define OXYGEN_REGS_H_INCLUDED /* recording channel A */ #define OXYGEN_DMA_A_ADDRESS … #define OXYGEN_DMA_A_COUNT … #define OXYGEN_DMA_A_TCOUNT … /* recording channel B */ #define OXYGEN_DMA_B_ADDRESS … #define OXYGEN_DMA_B_COUNT … #define OXYGEN_DMA_B_TCOUNT … /* recording channel C */ #define OXYGEN_DMA_C_ADDRESS … #define OXYGEN_DMA_C_COUNT … #define OXYGEN_DMA_C_TCOUNT … /* SPDIF playback channel */ #define OXYGEN_DMA_SPDIF_ADDRESS … #define OXYGEN_DMA_SPDIF_COUNT … #define OXYGEN_DMA_SPDIF_TCOUNT … /* multichannel playback channel */ #define OXYGEN_DMA_MULTICH_ADDRESS … #define OXYGEN_DMA_MULTICH_COUNT … #define OXYGEN_DMA_MULTICH_TCOUNT … /* AC'97 (front panel) playback channel */ #define OXYGEN_DMA_AC97_ADDRESS … #define OXYGEN_DMA_AC97_COUNT … #define OXYGEN_DMA_AC97_TCOUNT … /* all registers 0x00..0x36 return current position on read */ #define OXYGEN_DMA_STATUS … #define OXYGEN_CHANNEL_A … #define OXYGEN_CHANNEL_B … #define OXYGEN_CHANNEL_C … #define OXYGEN_CHANNEL_SPDIF … #define OXYGEN_CHANNEL_MULTICH … #define OXYGEN_CHANNEL_AC97 … #define OXYGEN_DMA_PAUSE … /* OXYGEN_CHANNEL_* */ #define OXYGEN_DMA_RESET … /* OXYGEN_CHANNEL_* */ #define OXYGEN_PLAY_CHANNELS … #define OXYGEN_PLAY_CHANNELS_MASK … #define OXYGEN_PLAY_CHANNELS_2 … #define OXYGEN_PLAY_CHANNELS_4 … #define OXYGEN_PLAY_CHANNELS_6 … #define OXYGEN_PLAY_CHANNELS_8 … #define OXYGEN_DMA_A_BURST_MASK … #define OXYGEN_DMA_A_BURST_8 … #define OXYGEN_DMA_A_BURST_16 … #define OXYGEN_DMA_MULTICH_BURST_MASK … #define OXYGEN_DMA_MULTICH_BURST_8 … #define OXYGEN_DMA_MULTICH_BURST_16 … #define OXYGEN_INTERRUPT_MASK … /* OXYGEN_CHANNEL_* */ #define OXYGEN_INT_SPDIF_IN_DETECT … #define OXYGEN_INT_MCU … #define OXYGEN_INT_2WIRE … #define OXYGEN_INT_GPIO … #define OXYGEN_INT_MCB … #define OXYGEN_INT_AC97 … #define OXYGEN_INTERRUPT_STATUS … /* OXYGEN_CHANNEL_* amd OXYGEN_INT_* */ #define OXYGEN_INT_MIDI … #define OXYGEN_MISC … #define OXYGEN_MISC_WRITE_PCI_SUBID … #define OXYGEN_MISC_LATENCY_3F … #define OXYGEN_MISC_REC_C_FROM_SPDIF … #define OXYGEN_MISC_REC_B_FROM_AC97 … #define OXYGEN_MISC_REC_A_FROM_MULTICH … #define OXYGEN_MISC_PCI_MEM_W_1_CLOCK … #define OXYGEN_MISC_MIDI … #define OXYGEN_MISC_CRYSTAL_MASK … #define OXYGEN_MISC_CRYSTAL_24576 … #define OXYGEN_MISC_CRYSTAL_27 … #define OXYGEN_REC_FORMAT … #define OXYGEN_REC_FORMAT_A_MASK … #define OXYGEN_REC_FORMAT_A_SHIFT … #define OXYGEN_REC_FORMAT_B_MASK … #define OXYGEN_REC_FORMAT_B_SHIFT … #define OXYGEN_REC_FORMAT_C_MASK … #define OXYGEN_REC_FORMAT_C_SHIFT … #define OXYGEN_FORMAT_16 … #define OXYGEN_FORMAT_24 … #define OXYGEN_FORMAT_32 … #define OXYGEN_PLAY_FORMAT … #define OXYGEN_SPDIF_FORMAT_MASK … #define OXYGEN_SPDIF_FORMAT_SHIFT … #define OXYGEN_MULTICH_FORMAT_MASK … #define OXYGEN_MULTICH_FORMAT_SHIFT … /* OXYGEN_FORMAT_* */ #define OXYGEN_REC_CHANNELS … #define OXYGEN_REC_CHANNELS_MASK … #define OXYGEN_REC_CHANNELS_2_2_2 … #define OXYGEN_REC_CHANNELS_4_2_2 … #define OXYGEN_REC_CHANNELS_6_0_2 … #define OXYGEN_REC_CHANNELS_6_2_0 … #define OXYGEN_REC_CHANNELS_8_0_0 … #define OXYGEN_FUNCTION … #define OXYGEN_FUNCTION_CLOCK_MASK … #define OXYGEN_FUNCTION_CLOCK_PLL … #define OXYGEN_FUNCTION_CLOCK_CRYSTAL … #define OXYGEN_FUNCTION_RESET_CODEC … #define OXYGEN_FUNCTION_RESET_POL … #define OXYGEN_FUNCTION_PWDN … #define OXYGEN_FUNCTION_PWDN_EN … #define OXYGEN_FUNCTION_PWDN_POL … #define OXYGEN_FUNCTION_2WIRE_SPI_MASK … #define OXYGEN_FUNCTION_SPI … #define OXYGEN_FUNCTION_2WIRE … #define OXYGEN_FUNCTION_ENABLE_SPI_4_5 … #define OXYGEN_I2S_MULTICH_FORMAT … #define OXYGEN_I2S_RATE_MASK … #define OXYGEN_RATE_32000 … #define OXYGEN_RATE_44100 … #define OXYGEN_RATE_48000 … #define OXYGEN_RATE_64000 … #define OXYGEN_RATE_88200 … #define OXYGEN_RATE_96000 … #define OXYGEN_RATE_176400 … #define OXYGEN_RATE_192000 … #define OXYGEN_I2S_FORMAT_MASK … #define OXYGEN_I2S_FORMAT_I2S … #define OXYGEN_I2S_FORMAT_LJUST … #define OXYGEN_I2S_MCLK_MASK … #define OXYGEN_I2S_MCLK_SHIFT … #define MCLK_128 … #define MCLK_256 … #define MCLK_512 … #define OXYGEN_I2S_MCLK(f) … #define OXYGEN_I2S_BITS_MASK … #define OXYGEN_I2S_BITS_16 … #define OXYGEN_I2S_BITS_20 … #define OXYGEN_I2S_BITS_24 … #define OXYGEN_I2S_BITS_32 … #define OXYGEN_I2S_MASTER … #define OXYGEN_I2S_BCLK_MASK … #define OXYGEN_I2S_BCLK_64 … #define OXYGEN_I2S_BCLK_128 … #define OXYGEN_I2S_BCLK_256 … #define OXYGEN_I2S_MUTE_MCLK … #define OXYGEN_I2S_A_FORMAT … #define OXYGEN_I2S_B_FORMAT … #define OXYGEN_I2S_C_FORMAT … /* like OXYGEN_I2S_MULTICH_FORMAT */ #define OXYGEN_SPDIF_CONTROL … #define OXYGEN_SPDIF_OUT_ENABLE … #define OXYGEN_SPDIF_LOOPBACK … #define OXYGEN_SPDIF_SENSE_MASK … #define OXYGEN_SPDIF_LOCK_MASK … #define OXYGEN_SPDIF_RATE_MASK … #define OXYGEN_SPDIF_SPDVALID … #define OXYGEN_SPDIF_SENSE_PAR … #define OXYGEN_SPDIF_LOCK_PAR … #define OXYGEN_SPDIF_SENSE_STATUS … #define OXYGEN_SPDIF_LOCK_STATUS … #define OXYGEN_SPDIF_SENSE_INT … #define OXYGEN_SPDIF_LOCK_INT … #define OXYGEN_SPDIF_RATE_INT … #define OXYGEN_SPDIF_IN_CLOCK_MASK … #define OXYGEN_SPDIF_IN_CLOCK_96 … #define OXYGEN_SPDIF_IN_CLOCK_192 … #define OXYGEN_SPDIF_OUT_RATE_MASK … #define OXYGEN_SPDIF_OUT_RATE_SHIFT … /* OXYGEN_RATE_* << OXYGEN_SPDIF_OUT_RATE_SHIFT */ #define OXYGEN_SPDIF_OUTPUT_BITS … #define OXYGEN_SPDIF_NONAUDIO … #define OXYGEN_SPDIF_C … #define OXYGEN_SPDIF_PREEMPHASIS … #define OXYGEN_SPDIF_CATEGORY_MASK … #define OXYGEN_SPDIF_CATEGORY_SHIFT … #define OXYGEN_SPDIF_ORIGINAL … #define OXYGEN_SPDIF_CS_RATE_MASK … #define OXYGEN_SPDIF_CS_RATE_SHIFT … #define OXYGEN_SPDIF_V … #define OXYGEN_SPDIF_INPUT_BITS … /* 32 bits, IEC958_AES_* */ #define OXYGEN_EEPROM_CONTROL … #define OXYGEN_EEPROM_ADDRESS_MASK … #define OXYGEN_EEPROM_DIR_MASK … #define OXYGEN_EEPROM_DIR_READ … #define OXYGEN_EEPROM_DIR_WRITE … #define OXYGEN_EEPROM_STATUS … #define OXYGEN_EEPROM_VALID … #define OXYGEN_EEPROM_BUSY … #define OXYGEN_EEPROM_DATA … #define OXYGEN_2WIRE_CONTROL … #define OXYGEN_2WIRE_DIR_MASK … #define OXYGEN_2WIRE_DIR_WRITE … #define OXYGEN_2WIRE_DIR_READ … #define OXYGEN_2WIRE_ADDRESS_MASK … #define OXYGEN_2WIRE_ADDRESS_SHIFT … #define OXYGEN_2WIRE_MAP … #define OXYGEN_2WIRE_DATA … #define OXYGEN_2WIRE_BUS_STATUS … #define OXYGEN_2WIRE_BUSY … #define OXYGEN_2WIRE_LENGTH_MASK … #define OXYGEN_2WIRE_LENGTH_8 … #define OXYGEN_2WIRE_LENGTH_16 … #define OXYGEN_2WIRE_MANUAL_READ … #define OXYGEN_2WIRE_WRITE_MAP_ONLY … #define OXYGEN_2WIRE_SLAVE_AD_MASK … #define OXYGEN_2WIRE_INTERRUPT_MASK … #define OXYGEN_2WIRE_SLAVE_NO_RESPONSE … #define OXYGEN_2WIRE_SPEED_MASK … #define OXYGEN_2WIRE_SPEED_STANDARD … #define OXYGEN_2WIRE_SPEED_FAST … #define OXYGEN_2WIRE_CLOCK_SYNC … #define OXYGEN_2WIRE_BUS_RESET … #define OXYGEN_SPI_CONTROL … #define OXYGEN_SPI_BUSY … #define OXYGEN_SPI_TRIGGER … #define OXYGEN_SPI_DATA_LENGTH_MASK … #define OXYGEN_SPI_DATA_LENGTH_2 … #define OXYGEN_SPI_DATA_LENGTH_3 … #define OXYGEN_SPI_CLOCK_MASK … #define OXYGEN_SPI_CLOCK_160 … #define OXYGEN_SPI_CLOCK_320 … #define OXYGEN_SPI_CLOCK_640 … #define OXYGEN_SPI_CLOCK_1280 … #define OXYGEN_SPI_CODEC_MASK … #define OXYGEN_SPI_CODEC_SHIFT … #define OXYGEN_SPI_CEN_MASK … #define OXYGEN_SPI_CEN_LATCH_CLOCK_LO … #define OXYGEN_SPI_CEN_LATCH_CLOCK_HI … #define OXYGEN_SPI_DATA1 … #define OXYGEN_SPI_DATA2 … #define OXYGEN_SPI_DATA3 … #define OXYGEN_MPU401 … #define OXYGEN_MPU401_CONTROL … #define OXYGEN_MPU401_LOOPBACK … #define OXYGEN_GPI_DATA … /* bits 0..5 = pin XGPI0..XGPI5 */ #define OXYGEN_GPI_INTERRUPT_MASK … /* bits 0..5, 1 = enable */ #define OXYGEN_GPIO_DATA … /* bits 0..9 */ #define OXYGEN_GPIO_CONTROL … /* bits 0..9, 0 = input, 1 = output */ #define OXYGEN_GPIO1_XSLAVE_RDY … #define OXYGEN_GPIO_INTERRUPT_MASK … /* bits 0..9, 1 = enable */ #define OXYGEN_DEVICE_SENSE … #define OXYGEN_HEAD_PHONE_DETECT … #define OXYGEN_HEAD_PHONE_MASK … #define OXYGEN_HEAD_PHONE_PASSIVE_SPK … #define OXYGEN_HEAD_PHONE_HP … #define OXYGEN_HEAD_PHONE_ACTIVE_SPK … #define OXYGEN_MCU_2WIRE_DATA … #define OXYGEN_MCU_2WIRE_MAP … #define OXYGEN_MCU_2WIRE_STATUS … #define OXYGEN_MCU_2WIRE_BUSY … #define OXYGEN_MCU_2WIRE_LENGTH_MASK … #define OXYGEN_MCU_2WIRE_LENGTH_1 … #define OXYGEN_MCU_2WIRE_LENGTH_2 … #define OXYGEN_MCU_2WIRE_LENGTH_3 … #define OXYGEN_MCU_2WIRE_WRITE … #define OXYGEN_MCU_2WIRE_READ … #define OXYGEN_MCU_2WIRE_DRV_XACT_FAIL … #define OXYGEN_MCU_2WIRE_RESET … #define OXYGEN_MCU_2WIRE_CONTROL … #define OXYGEN_MCU_2WIRE_DRV_ACK … #define OXYGEN_MCU_2WIRE_DRV_XACT … #define OXYGEN_MCU_2WIRE_INT_MASK … #define OXYGEN_MCU_2WIRE_SYNC_MASK … #define OXYGEN_MCU_2WIRE_SYNC_RDY_PIN … #define OXYGEN_MCU_2WIRE_SYNC_DATA … #define OXYGEN_MCU_2WIRE_ADDRESS_MASK … #define OXYGEN_MCU_2WIRE_ADDRESS_10 … #define OXYGEN_MCU_2WIRE_ADDRESS_12 … #define OXYGEN_MCU_2WIRE_ADDRESS_14 … #define OXYGEN_MCU_2WIRE_ADDRESS_16 … #define OXYGEN_MCU_2WIRE_INT_POL … #define OXYGEN_MCU_2WIRE_SYNC_ENABLE … #define OXYGEN_PLAY_ROUTING … #define OXYGEN_PLAY_MUTE01 … #define OXYGEN_PLAY_MUTE23 … #define OXYGEN_PLAY_MUTE45 … #define OXYGEN_PLAY_MUTE67 … #define OXYGEN_PLAY_MUTE_MASK … #define OXYGEN_PLAY_MULTICH_MASK … #define OXYGEN_PLAY_MULTICH_I2S_DAC … #define OXYGEN_PLAY_MULTICH_AC97 … #define OXYGEN_PLAY_SPDIF_MASK … #define OXYGEN_PLAY_SPDIF_SPDIF … #define OXYGEN_PLAY_SPDIF_MULTICH_01 … #define OXYGEN_PLAY_SPDIF_MULTICH_23 … #define OXYGEN_PLAY_SPDIF_MULTICH_45 … #define OXYGEN_PLAY_SPDIF_MULTICH_67 … #define OXYGEN_PLAY_SPDIF_REC_A … #define OXYGEN_PLAY_SPDIF_REC_B … #define OXYGEN_PLAY_SPDIF_I2S_ADC_3 … #define OXYGEN_PLAY_DAC0_SOURCE_MASK … #define OXYGEN_PLAY_DAC0_SOURCE_SHIFT … #define OXYGEN_PLAY_DAC1_SOURCE_MASK … #define OXYGEN_PLAY_DAC1_SOURCE_SHIFT … #define OXYGEN_PLAY_DAC2_SOURCE_MASK … #define OXYGEN_PLAY_DAC2_SOURCE_SHIFT … #define OXYGEN_PLAY_DAC3_SOURCE_MASK … #define OXYGEN_PLAY_DAC3_SOURCE_SHIFT … #define OXYGEN_REC_ROUTING … #define OXYGEN_MUTE_I2S_ADC_1 … #define OXYGEN_MUTE_I2S_ADC_2 … #define OXYGEN_MUTE_I2S_ADC_3 … #define OXYGEN_REC_A_ROUTE_MASK … #define OXYGEN_REC_A_ROUTE_I2S_ADC_1 … #define OXYGEN_REC_A_ROUTE_AC97_0 … #define OXYGEN_REC_B_ROUTE_MASK … #define OXYGEN_REC_B_ROUTE_I2S_ADC_2 … #define OXYGEN_REC_B_ROUTE_AC97_1 … #define OXYGEN_REC_C_ROUTE_MASK … #define OXYGEN_REC_C_ROUTE_SPDIF … #define OXYGEN_REC_C_ROUTE_I2S_ADC_3 … #define OXYGEN_ADC_MONITOR … #define OXYGEN_ADC_MONITOR_A … #define OXYGEN_ADC_MONITOR_A_HALF_VOL … #define OXYGEN_ADC_MONITOR_B … #define OXYGEN_ADC_MONITOR_B_HALF_VOL … #define OXYGEN_ADC_MONITOR_C … #define OXYGEN_ADC_MONITOR_C_HALF_VOL … #define OXYGEN_A_MONITOR_ROUTING … #define OXYGEN_A_MONITOR_ROUTE_0_MASK … #define OXYGEN_A_MONITOR_ROUTE_0_SHIFT … #define OXYGEN_A_MONITOR_ROUTE_1_MASK … #define OXYGEN_A_MONITOR_ROUTE_1_SHIFT … #define OXYGEN_A_MONITOR_ROUTE_2_MASK … #define OXYGEN_A_MONITOR_ROUTE_2_SHIFT … #define OXYGEN_A_MONITOR_ROUTE_3_MASK … #define OXYGEN_A_MONITOR_ROUTE_3_SHIFT … #define OXYGEN_AC97_CONTROL … #define OXYGEN_AC97_COLD_RESET … #define OXYGEN_AC97_SUSPENDED … #define OXYGEN_AC97_RESUME … #define OXYGEN_AC97_CLOCK_DISABLE … #define OXYGEN_AC97_NO_CODEC_0 … #define OXYGEN_AC97_CODEC_0 … #define OXYGEN_AC97_CODEC_1 … #define OXYGEN_AC97_INTERRUPT_MASK … #define OXYGEN_AC97_INT_READ_DONE … #define OXYGEN_AC97_INT_WRITE_DONE … #define OXYGEN_AC97_INT_CODEC_0 … #define OXYGEN_AC97_INT_CODEC_1 … #define OXYGEN_AC97_INTERRUPT_STATUS … /* OXYGEN_AC97_INT_* */ #define OXYGEN_AC97_OUT_CONFIG … #define OXYGEN_AC97_CODEC1_SLOT3 … #define OXYGEN_AC97_CODEC1_SLOT3_VSR … #define OXYGEN_AC97_CODEC1_SLOT4 … #define OXYGEN_AC97_CODEC1_SLOT4_VSR … #define OXYGEN_AC97_CODEC0_FRONTL … #define OXYGEN_AC97_CODEC0_FRONTR … #define OXYGEN_AC97_CODEC0_SIDEL … #define OXYGEN_AC97_CODEC0_SIDER … #define OXYGEN_AC97_CODEC0_CENTER … #define OXYGEN_AC97_CODEC0_BASE … #define OXYGEN_AC97_CODEC0_REARL … #define OXYGEN_AC97_CODEC0_REARR … #define OXYGEN_AC97_IN_CONFIG … #define OXYGEN_AC97_CODEC1_LINEL … #define OXYGEN_AC97_CODEC1_LINEL_VSR … #define OXYGEN_AC97_CODEC1_LINEL_16 … #define OXYGEN_AC97_CODEC1_LINEL_18 … #define OXYGEN_AC97_CODEC1_LINEL_20 … #define OXYGEN_AC97_CODEC1_LINER … #define OXYGEN_AC97_CODEC1_LINER_VSR … #define OXYGEN_AC97_CODEC1_LINER_16 … #define OXYGEN_AC97_CODEC1_LINER_18 … #define OXYGEN_AC97_CODEC1_LINER_20 … #define OXYGEN_AC97_CODEC0_LINEL … #define OXYGEN_AC97_CODEC0_LINER … #define OXYGEN_AC97_REGS … #define OXYGEN_AC97_REG_DATA_MASK … #define OXYGEN_AC97_REG_ADDR_MASK … #define OXYGEN_AC97_REG_ADDR_SHIFT … #define OXYGEN_AC97_REG_DIR_MASK … #define OXYGEN_AC97_REG_DIR_WRITE … #define OXYGEN_AC97_REG_DIR_READ … #define OXYGEN_AC97_REG_CODEC_MASK … #define OXYGEN_AC97_REG_CODEC_SHIFT … #define OXYGEN_TEST … #define OXYGEN_TEST_RAM_SUCCEEDED … #define OXYGEN_TEST_PLAYBACK_RAM … #define OXYGEN_TEST_RECORD_RAM … #define OXYGEN_TEST_PLL … #define OXYGEN_TEST_2WIRE_LOOPBACK … #define OXYGEN_DMA_FLUSH … /* OXYGEN_CHANNEL_* */ #define OXYGEN_CODEC_VERSION … #define OXYGEN_CODEC_ID_MASK … #define OXYGEN_REVISION … #define OXYGEN_PACKAGE_ID_MASK … #define OXYGEN_PACKAGE_ID_8786 … #define OXYGEN_PACKAGE_ID_8787 … #define OXYGEN_PACKAGE_ID_8788 … #define OXYGEN_REVISION_MASK … #define OXYGEN_REVISION_2 … #define OXYGEN_OFFSIN_48K … #define OXYGEN_OFFSBASE_48K … #define OXYGEN_OFFSBASE_MASK … #define OXYGEN_OFFSIN_44K … #define OXYGEN_OFFSBASE_44K … #endif
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