/* SPDX-License-Identifier: GPL-2.0 */ /* Analog Devices 1889 audio driver * Copyright (C) 2004, Kyle McMartin <[email protected]> */ #ifndef __AD1889_H__ #define __AD1889_H__ #define AD_DS_WSMC … #define AD_DS_WSMC_SYEN … #define AD_DS_WSMC_SYRQ … #define AD_DS_WSMC_WA16 … #define AD_DS_WSMC_WAST … #define AD_DS_WSMC_WAEN … #define AD_DS_WSMC_WARQ … #define AD_DS_RAMC … #define AD_DS_RAMC_AD16 … #define AD_DS_RAMC_ADST … #define AD_DS_RAMC_ADEN … #define AD_DS_RAMC_ACRQ … #define AD_DS_RAMC_REEN … #define AD_DS_RAMC_RERQ … #define AD_DS_WADA … #define AD_DS_WADA_RWAM … #define AD_DS_WADA_RWAA … #define AD_DS_WADA_LWAM … #define AD_DS_WADA_LWAA … #define AD_DS_SYDA … #define AD_DS_SYDA_RSYM … #define AD_DS_SYDA_RSYA … #define AD_DS_SYDA_LSYM … #define AD_DS_SYDA_LSYA … #define AD_DS_WAS … #define AD_DS_WAS_WAS … #define AD_DS_RES … #define AD_DS_RES_RES … #define AD_DS_CCS … #define AD_DS_CCS_ADO … #define AD_DS_CCS_REO … #define AD_DS_CCS_SYU … #define AD_DS_CCS_WAU … /* bits 4 -> 7, 9, 11 -> 14 reserved */ #define AD_DS_CCS_XTD … #define AD_DS_CCS_PDALL … #define AD_DS_CCS_CLKEN … #define AD_DMA_RESBA … #define AD_DMA_RESCA … #define AD_DMA_RESBC … #define AD_DMA_RESCC … #define AD_DMA_ADCBA … #define AD_DMA_ADCCA … #define AD_DMA_ADCBC … #define AD_DMA_ADCCC … #define AD_DMA_SYNBA … #define AD_DMA_SYNCA … #define AD_DMA_SYNBC … #define AD_DMA_SYNCC … #define AD_DMA_WAVBA … #define AD_DMA_WAVCA … #define AD_DMA_WAVBC … #define AD_DMA_WAVCC … #define AD_DMA_RESIC … #define AD_DMA_RESIB … #define AD_DMA_ADCIC … #define AD_DMA_ADCIB … #define AD_DMA_SYNIC … #define AD_DMA_SYNIB … #define AD_DMA_WAVIC … #define AD_DMA_WAVIB … #define AD_DMA_ICC … #define AD_DMA_IBC … /* bits 24 -> 31 reserved */ /* 4 bytes pad */ #define AD_DMA_ADC … #define AD_DMA_SYNTH … #define AD_DMA_WAV … #define AD_DMA_RES … #define AD_DMA_SGDE … #define AD_DMA_LOOP … #define AD_DMA_IM … #define AD_DMA_IM_DIS … #define AD_DMA_IM_CNT … #define AD_DMA_IM_SGD … #define AD_DMA_IM_EOL … #define AD_DMA_SGDS … #define AD_DMA_SFLG … #define AD_DMA_EOL … /* bits 8 -> 15 reserved */ #define AD_DMA_DISR … #define AD_DMA_DISR_RESI … #define AD_DMA_DISR_ADCI … #define AD_DMA_DISR_SYNI … #define AD_DMA_DISR_WAVI … /* bits 4, 5 reserved */ #define AD_DMA_DISR_SEPS … /* bits 7 -> 13 reserved */ #define AD_DMA_DISR_PMAI … #define AD_DMA_DISR_PTAI … #define AD_DMA_DISR_PTAE … #define AD_DMA_DISR_PMAE … /* bits 19 -> 31 reserved */ /* interrupt mask */ #define AD_INTR_MASK … #define AD_DMA_CHSS … #define AD_DMA_CHSS_RESS … #define AD_DMA_CHSS_ADCS … #define AD_DMA_CHSS_SYNS … #define AD_DMA_CHSS_WAVS … #define AD_GPIO_IPC … #define AD_GPIO_OP … #define AD_GPIO_IP … #define AD_AC97_BASE … #define AD_AC97_RESET … #define AD_AC97_PWR_CTL … #define AD_AC97_PWR_ADC … #define AD_AC97_PWR_DAC … #define AD_AC97_PWR_PR0 … #define AD_AC97_PWR_PR1 … #define AD_MISC_CTL … #define AD_MISC_CTL_DACZ … #define AD_MISC_CTL_ARSR … #define AD_MISC_CTL_ALSR … #define AD_MISC_CTL_DLSR … #define AD_MISC_CTL_DRSR … #define AD_AC97_SR0 … #define AD_AC97_SR0_48K … #define AD_AC97_SR1 … #define AD_AC97_ACIC … #define AD_AC97_ACIC_ACIE … #define AD_AC97_ACIC_ACRD … #define AD_AC97_ACIC_ASOE … #define AD_AC97_ACIC_VSRM … #define AD_AC97_ACIC_FSDH … #define AD_AC97_ACIC_FSYH … #define AD_AC97_ACIC_ACRDY … /* bits 10 -> 14 reserved */ #define AD_DS_MEMSIZE … #define AD_OPL_MEMSIZE … #define AD_MIDI_MEMSIZE … #define AD_WAV_STATE … #define AD_ADC_STATE … #define AD_MAX_STATES … #define AD_CHAN_WAV … #define AD_CHAN_ADC … #define AD_CHAN_RES … #define AD_CHAN_SYN … /* The chip would support 4 GB buffers and 16 MB periods, * but let's not overdo it ... */ #define BUFFER_BYTES_MAX … #define PERIOD_BYTES_MIN … #define PERIOD_BYTES_MAX … #define PERIODS_MIN … #define PERIODS_MAX … #endif /* __AD1889_H__ */
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