/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __SOUND_AZT3328_H #define __SOUND_AZT3328_H /* "PU" == "power-up value", as tested on PCI168 PCI rev. 10 * "WRITE_ONLY" == register does not indicate actual bit values */ /*** main I/O area port indices ***/ /* (only 0x70 of 0x80 bytes saved/restored by Windows driver) */ #define AZF_IO_SIZE_CTRL … #define AZF_IO_SIZE_CTRL_PM … /* the driver initialisation suggests a layout of 4 areas * within the main card control I/O: * from 0x00 (playback codec), from 0x20 (recording codec) * and from 0x40 (most certainly I2S out codec). * And another area from 0x60 to 0x6f (DirectX timer, IRQ management, * power management etc.???). */ #define AZF_IO_OFFS_CODEC_PLAYBACK … #define AZF_IO_OFFS_CODEC_CAPTURE … #define AZF_IO_OFFS_CODEC_I2S_OUT … #define IDX_IO_CODEC_DMA_FLAGS … /* able to reactivate output after output muting due to 8/16bit * output change, just like 0x0002. * 0x0001 is the only bit that's able to start the DMA counter */ #define DMA_RESUME … /* 0x0002 *temporarily* set during DMA stopping. hmm * both 0x0002 and 0x0004 set in playback setup. */ /* able to reactivate output after output muting due to 8/16bit * output change, just like 0x0001. */ #define DMA_RUN_SOMETHING1 … /* 0x0004: NOT able to reactivate output */ #define DMA_RUN_SOMETHING2 … #define SOMETHING_ALMOST_ALWAYS_SET … #define DMA_EPILOGUE_SOMETHING … #define DMA_SOMETHING_ELSE … #define SOMETHING_UNMODIFIABLE … #define IDX_IO_CODEC_IRQTYPE … /* write back to flags in case flags are set, in order to ACK IRQ in handler * (bit 1 of port 0x64 indicates interrupt for one of these three types) * sometimes in this case it just writes 0xffff to globally ACK all IRQs * settings written are not reflected when reading back, though. * seems to be IRQ, too (frequently used: port |= 0x07 !), but who knows? */ #define IRQ_SOMETHING … #define IRQ_FINISHED_DMABUF_1 … #define IRQ_FINISHED_DMABUF_2 … #define IRQMASK_SOME_STATUS_1 … #define IRQMASK_SOME_STATUS_2 … #define IRQMASK_UNMODIFIABLE … /* start address of 1st DMA transfer area, PU:0x00000000 */ #define IDX_IO_CODEC_DMA_START_1 … /* start address of 2nd DMA transfer area, PU:0x00000000 */ #define IDX_IO_CODEC_DMA_START_2 … /* both lengths of DMA transfer areas, PU:0x00000000 length1: offset 0x0c, length2: offset 0x0e */ #define IDX_IO_CODEC_DMA_LENGTHS … #define IDX_IO_CODEC_DMA_CURRPOS … /* offset within current DMA transfer area, PU:0x0000 */ #define IDX_IO_CODEC_DMA_CURROFS … #define IDX_IO_CODEC_SOUNDFORMAT … /* all unspecified bits can't be modified */ #define SOUNDFORMAT_FREQUENCY_MASK … #define SOUNDFORMAT_XTAL1 … #define SOUNDFORMAT_XTAL2 … /* all _SUSPECTED_ values are not used by Windows drivers, so we don't * have any hard facts, only rough measurements. * All we know is that the crystal used on the board has 24.576MHz, * like many soundcards (which results in the frequencies below when * using certain divider values selected by the values below) */ #define SOUNDFORMAT_FREQ_SUSPECTED_4000 … #define SOUNDFORMAT_FREQ_SUSPECTED_4800 … #define SOUNDFORMAT_FREQ_5510 … #define SOUNDFORMAT_FREQ_6620 … #define SOUNDFORMAT_FREQ_8000 … #define SOUNDFORMAT_FREQ_9600 … #define SOUNDFORMAT_FREQ_11025 … #define SOUNDFORMAT_FREQ_SUSPECTED_13240 … #define SOUNDFORMAT_FREQ_16000 … #define SOUNDFORMAT_FREQ_22050 … #define SOUNDFORMAT_FREQ_32000 … #define SOUNDFORMAT_FREQ_44100 … #define SOUNDFORMAT_FREQ_48000 … #define SOUNDFORMAT_FREQ_SUSPECTED_66200 … #define SOUNDFORMAT_FLAG_16BIT … #define SOUNDFORMAT_FLAG_2CHANNELS … /* define frequency helpers, for maximum value safety */ enum azf_freq_t { … }; /** DirectX timer, main interrupt area (FIXME: and something else?) **/ #define IDX_IO_TIMER_VALUE … /* timer countdown value; triggers IRQ when timer is finished */ #define TIMER_VALUE_MASK … /* activate timer countdown */ #define TIMER_COUNTDOWN_ENABLE … /* trigger timer IRQ on zero transition */ #define TIMER_IRQ_ENABLE … /* being set in IRQ handler in case port 0x00 (hmm, not port 0x64!?!?) * had 0x0020 set upon IRQ handler */ #define TIMER_IRQ_ACK … #define IDX_IO_IRQSTATUS … /* some IRQ bit in here might also be used to signal a power-management timer * timeout, to request shutdown of the chip (e.g. AD1815JS has such a thing). * OPL3 hardware contains several timers which confusingly in most cases * are NOT routed to an IRQ, but some designs (e.g. LM4560) DO support that, * so I wouldn't be surprised at all to discover that AZF3328 * supports that thing as well... */ #define IRQ_PLAYBACK … #define IRQ_RECORDING … #define IRQ_I2S_OUT … #define IRQ_GAMEPORT … #define IRQ_MPU401 … #define IRQ_TIMER … #define IRQ_UNKNOWN2 … #define IRQ_UNKNOWN3 … #define IDX_IO_66H … /* this is set to e.g. 0x3ff or 0x300, and writable; * maybe some buffer limit, but I couldn't find out more, PU:0x00ff: */ #define IDX_IO_SOME_VALUE … #define IO_68_RANDOM_TOGGLE1 … #define IO_68_RANDOM_TOGGLE2 … /* umm, nope, behaviour of these bits changes depending on what we wrote * to 0x6b!! * And they change upon playback/stop, too: * Writing a value to 0x68 will display this exact value during playback, * too but when stopped it can fall back to a rather different * seemingly random value). Hmm, possibly this is a register which * has a remote shadow which needs proper device supply which only exists * in case playback is active? Or is this driver-induced? */ /* this WORD can be set to have bits 0x0028 activated (FIXME: correct??); * actually inhibits PCM playback!!! maybe power management??: */ #define IDX_IO_6AH … /* bit 5: enabling this will activate permanent counting of bytes 2/3 * at gameport I/O (0xb402/3) (equal values each) and cause * gameport legacy I/O at 0x0200 to be _DISABLED_! * Is this Digital Enhanced Game Port Enable??? Or maybe it's Testmode * for Enhanced Digital Gameport (see 4D Wave DX card): */ #define IO_6A_SOMETHING1_GAMEPORT … /* bit 8; sure, this _pauses_ playback (later resumes at same spot!), * but what the heck is this really about??: */ #define IO_6A_PAUSE_PLAYBACK_BIT8 … /* bit 9; sure, this _pauses_ playback (later resumes at same spot!), * but what the heck is this really about??: */ #define IO_6A_PAUSE_PLAYBACK_BIT9 … /* BIT8 and BIT9 are _NOT_ able to affect OPL3 MIDI playback, * thus it suggests influence on PCM only!! * However OTOH there seems to be no bit anywhere around here * which is able to disable OPL3... */ /* bit 10: enabling this actually changes values at legacy gameport * I/O address (0x200); is this enabling of the Digital Enhanced Game Port??? * Or maybe this simply switches off the NE558 circuit, since enabling this * still lets us evaluate button states, but not axis states */ #define IO_6A_SOMETHING2_GAMEPORT … /* writing 0x0300: causes quite some crackling during * PC activity such as switching windows (PCI traffic?? * --> FIFO/timing settings???) */ /* writing 0x0100 plus/or 0x0200 inhibits playback */ /* since the Windows .INF file has Flag_Enable_JoyStick and * Flag_Enable_SB_DOS_Emulation directly together, it stands to reason * that some other bit in this same register might be responsible * for SB DOS Emulation activation (note that the file did NOT define * a switch for OPL3!) */ #define IDX_IO_6CH … #define IDX_IO_6EH … /* writing 0xffff returns 0x83fe (or 0x03fe only). * writing 0x83 (and only 0x83!!) to 0x6f will cause 0x6c to switch * from 0000 to ffff. */ /* further I/O indices not saved/restored and not readable after writing, * so probably not used */ /*** Gameport area port indices ***/ /* (only 0x06 of 0x08 bytes saved/restored by Windows driver) */ #define AZF_IO_SIZE_GAME … #define AZF_IO_SIZE_GAME_PM … enum { … }; #define IDX_GAME_LEGACY_COMPATIBLE … /* in some operation mode, writing anything to this port * triggers an interrupt: * yup, that's in case IDX_GAME_01H has one of the * axis measurement bits enabled * (and of course one needs to have GAME_HWCFG_IRQ_ENABLE, too) */ #define IDX_GAME_AXES_CONFIG … /* NOTE: layout of this register awfully similar (read: "identical??") * to AD1815JS.pdf (p.29) */ /* enables axis 1 (X axis) measurement: */ #define GAME_AXES_ENABLE_1 … /* enables axis 2 (Y axis) measurement: */ #define GAME_AXES_ENABLE_2 … /* enables axis 3 (X axis) measurement: */ #define GAME_AXES_ENABLE_3 … /* enables axis 4 (Y axis) measurement: */ #define GAME_AXES_ENABLE_4 … /* selects the current axis to read the measured value of * (at IDX_GAME_AXIS_VALUE): * 00 = axis 1, 01 = axis 2, 10 = axis 3, 11 = axis 4: */ #define GAME_AXES_READ_MASK … /* enable to have the latch continuously accept ADC values * (and continuously cause interrupts in case interrupts are enabled); * AD1815JS.pdf says it's ~16ms interval there: */ #define GAME_AXES_LATCH_ENABLE … /* joystick data (measured axes) ready for reading: */ #define GAME_AXES_SAMPLING_READY … /* NOTE: other card specs (SiS960 and others!) state that the * game position latches should be frozen when reading and be freed * (== reset?) after reading!!! * Freezing most likely means disabling 0x40 (GAME_AXES_LATCH_ENABLE), * but how to free the value? */ /* An internet search for "gameport latch ADC" should provide some insight * into how to program such a gameport system. */ /* writing 0xf0 to 01H once reset both counters to 0, in some special mode!? * yup, in case 6AH 0x20 is not enabled * (and 0x40 is sufficient, 0xf0 is not needed) */ #define IDX_GAME_AXIS_VALUE … /* R: value of currently configured axis (word value!); * W: trigger axis measurement */ #define IDX_GAME_HWCONFIG … /* note: bits 4 to 7 are never set (== 0) when reading! * --> reserved bits? */ /* enables IRQ notification upon axes measurement ready: */ #define GAME_HWCFG_IRQ_ENABLE … /* these bits choose a different frequency for the * internal ADC counter increment. * hmm, seems to be a combo of bits: * 00 --> standard frequency * 10 --> 1/2 * 01 --> 1/20 * 11 --> 1/200: */ #define GAME_HWCFG_ADC_COUNTER_FREQ_MASK … /* FIXME: these values might be reversed... */ #define GAME_HWCFG_ADC_COUNTER_FREQ_STD … #define GAME_HWCFG_ADC_COUNTER_FREQ_1_2 … #define GAME_HWCFG_ADC_COUNTER_FREQ_1_20 … #define GAME_HWCFG_ADC_COUNTER_FREQ_1_200 … /* enable gameport legacy I/O address (0x200) * I was unable to locate any configurability for a different address: */ #define GAME_HWCFG_LEGACY_ADDRESS_ENABLE … /*** MPU401 ***/ #define AZF_IO_SIZE_MPU … #define AZF_IO_SIZE_MPU_PM … /*** OPL3 synth ***/ /* (only 0x06 of 0x08 bytes saved/restored by Windows driver) */ #define AZF_IO_SIZE_OPL3 … #define AZF_IO_SIZE_OPL3_PM … /* hmm, given that a standard OPL3 has 4 registers only, * there might be some enhanced functionality lurking at the end * (especially since register 0x04 has a "non-empty" value 0xfe) */ /*** mixer I/O area port indices ***/ /* (only 0x22 of 0x40 bytes saved/restored by Windows driver) * UNFORTUNATELY azf3328 is NOT truly AC97 compliant: see main file intro */ #define AZF_IO_SIZE_MIXER … #define AZF_IO_SIZE_MIXER_PM … #define MIXER_VOLUME_RIGHT_MASK … #define MIXER_VOLUME_LEFT_MASK … #define MIXER_MUTE_MASK … #define IDX_MIXER_RESET … #define IDX_MIXER_PLAY_MASTER … #define IDX_MIXER_MODEMOUT … #define IDX_MIXER_BASSTREBLE … #define MIXER_BASSTREBLE_TREBLE_VOLUME_MASK … #define MIXER_BASSTREBLE_BASS_VOLUME_MASK … #define IDX_MIXER_PCBEEP … #define IDX_MIXER_MODEMIN … #define IDX_MIXER_MIC … #define MIXER_MIC_MICGAIN_20DB_ENHANCEMENT_MASK … #define IDX_MIXER_LINEIN … #define IDX_MIXER_CDAUDIO … #define IDX_MIXER_VIDEO … #define IDX_MIXER_AUX … #define IDX_MIXER_WAVEOUT … #define IDX_MIXER_FMSYNTH … #define IDX_MIXER_REC_SELECT … #define MIXER_REC_SELECT_MIC … #define MIXER_REC_SELECT_CD … #define MIXER_REC_SELECT_VIDEO … #define MIXER_REC_SELECT_AUX … #define MIXER_REC_SELECT_LINEIN … #define MIXER_REC_SELECT_MIXSTEREO … #define MIXER_REC_SELECT_MIXMONO … #define MIXER_REC_SELECT_MONOIN … #define IDX_MIXER_REC_VOLUME … #define IDX_MIXER_ADVCTL1 … /* unlisted bits are unmodifiable */ #define MIXER_ADVCTL1_3DWIDTH_MASK … #define MIXER_ADVCTL1_HIFI3D_MASK … #define IDX_MIXER_ADVCTL2 … /* unlisted bits are unmodifiable */ #define MIXER_ADVCTL2_LPBK … #define MIXER_ADVCTL2_MS … #define MIXER_ADVCTL2_MIX … #define MIXER_ADVCTL2_3D … #define MIXER_ADVCTL2_POP … #define IDX_MIXER_SOMETHING30H … /* driver internal flags */ #define SET_CHAN_LEFT … #define SET_CHAN_RIGHT … /* helper macro to align I/O port ranges to 32bit I/O width */ #define AZF_ALIGN(x) … #endif /* __SOUND_AZT3328_H */