// SPDX-License-Identifier: GPL-2.0-or-later /* * ALSA driver for Intel ICH (i8x0) chipsets * * Copyright (c) 2000 Jaroslav Kysela <[email protected]> * * This code also contains alpha support for SiS 735 chipsets provided * by Mike Pieper <[email protected]>. We have no datasheet * for SiS735, so the code is not fully functional. * */ #include <linux/io.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/slab.h> #include <linux/module.h> #include <sound/core.h> #include <sound/pcm.h> #include <sound/ac97_codec.h> #include <sound/info.h> #include <sound/initval.h> MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; static int index = …; /* Index 0-MAX */ static char *id = …; /* ID for this card */ static int ac97_clock; static char *ac97_quirk; static bool buggy_semaphore; static int buggy_irq = …; /* auto-check */ static bool xbox; static int spdif_aclink = …; static int inside_vm = …; module_param(index, int, 0444); MODULE_PARM_DESC(…) …; module_param(id, charp, 0444); MODULE_PARM_DESC(…) …; module_param(ac97_clock, int, 0444); MODULE_PARM_DESC(…) …; module_param(ac97_quirk, charp, 0444); MODULE_PARM_DESC(…) …; module_param(buggy_semaphore, bool, 0444); MODULE_PARM_DESC(…) …; module_param(buggy_irq, bint, 0444); MODULE_PARM_DESC(…) …; module_param(xbox, bool, 0444); MODULE_PARM_DESC(…) …; module_param(spdif_aclink, int, 0444); MODULE_PARM_DESC(…) …; module_param(inside_vm, bint, 0444); MODULE_PARM_DESC(…) …; /* just for backward compatibility */ static bool enable; module_param(enable, bool, 0444); static int joystick; module_param(joystick, int, 0444); /* * Direct registers */ enum { … }; #define ICHREG(x) … #define DEFINE_REGSET(name,base) … /* busmaster blocks */ DEFINE_REGSET(OFF, 0); /* offset */ DEFINE_REGSET(PI, 0x00); /* PCM in */ DEFINE_REGSET(PO, 0x10); /* PCM out */ DEFINE_REGSET(MC, 0x20); /* Mic in */ /* ICH4 busmaster blocks */ DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */ DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */ DEFINE_REGSET(SP, 0x60); /* SPDIF out */ /* values for each busmaster block */ /* LVI */ #define ICH_REG_LVI_MASK … /* SR */ #define ICH_FIFOE … #define ICH_BCIS … #define ICH_LVBCI … #define ICH_CELV … #define ICH_DCH … /* PIV */ #define ICH_REG_PIV_MASK … /* CR */ #define ICH_IOCE … #define ICH_FEIE … #define ICH_LVBIE … #define ICH_RESETREGS … #define ICH_STARTBM … /* global block */ #define ICH_REG_GLOB_CNT … #define ICH_PCM_SPDIF_MASK … #define ICH_PCM_SPDIF_NONE … #define ICH_PCM_SPDIF_78 … #define ICH_PCM_SPDIF_69 … #define ICH_PCM_SPDIF_1011 … #define ICH_PCM_20BIT … #define ICH_PCM_246_MASK … #define ICH_PCM_8 … #define ICH_PCM_6 … #define ICH_PCM_4 … #define ICH_PCM_2 … #define ICH_SIS_PCM_246_MASK … #define ICH_SIS_PCM_6 … #define ICH_SIS_PCM_4 … #define ICH_SIS_PCM_2 … #define ICH_TRIE … #define ICH_SRIE … #define ICH_PRIE … #define ICH_ACLINK … #define ICH_AC97WARM … #define ICH_AC97COLD … #define ICH_GIE … #define ICH_REG_GLOB_STA … #define ICH_TRI … #define ICH_TCR … #define ICH_BCS … #define ICH_SPINT … #define ICH_P2INT … #define ICH_M2INT … #define ICH_SAMPLE_CAP … #define ICH_SAMPLE_16_20 … #define ICH_MULTICHAN_CAP … #define ICH_SIS_TRI … #define ICH_SIS_TCR … #define ICH_MD3 … #define ICH_AD3 … #define ICH_RCS … #define ICH_BIT3 … #define ICH_BIT2 … #define ICH_BIT1 … #define ICH_SRI … #define ICH_PRI … #define ICH_SCR … #define ICH_PCR … #define ICH_MCINT … #define ICH_POINT … #define ICH_PIINT … #define ICH_NVSPINT … #define ICH_MOINT … #define ICH_MIINT … #define ICH_GSCI … #define ICH_REG_ACC_SEMA … #define ICH_CAS … #define ICH_REG_SDM … #define ICH_DI2L_MASK … #define ICH_DI2L_SHIFT … #define ICH_DI1L_MASK … #define ICH_DI1L_SHIFT … #define ICH_SE … #define ICH_LDI_MASK … #define ICH_MAX_FRAGS … /* * registers for Ali5455 */ /* ALi 5455 busmaster blocks */ DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */ DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */ DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */ DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */ DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */ DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */ DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */ DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */ DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */ DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */ DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */ enum { … }; #define ALI_CAS_SEM_BUSY … #define ALI_CPR_ADDR_SECONDARY … #define ALI_CPR_ADDR_READ … #define ALI_CSPSR_CODEC_READY … #define ALI_CSPSR_READ_OK … #define ALI_CSPSR_WRITE_OK … /* interrupts for the whole chip by interrupt status register finish */ #define ALI_INT_MICIN2 … #define ALI_INT_PCMIN2 … #define ALI_INT_I2SIN … #define ALI_INT_SPDIFOUT … #define ALI_INT_SPDIFIN … #define ALI_INT_LFEOUT … #define ALI_INT_CENTEROUT … #define ALI_INT_CODECSPDIFOUT … #define ALI_INT_MICIN … #define ALI_INT_PCMOUT … #define ALI_INT_PCMIN … #define ALI_INT_CPRAIS … #define ALI_INT_SPRAIS … #define ALI_INT_GPIO … #define ALI_INT_MASK … #define ICH_ALI_SC_RESET … #define ICH_ALI_SC_AC97_DBL … #define ICH_ALI_SC_CODEC_SPDF … #define ICH_ALI_SC_IN_BITS … #define ICH_ALI_SC_OUT_BITS … #define ICH_ALI_SC_6CH_CFG … #define ICH_ALI_SC_PCM_4 … #define ICH_ALI_SC_PCM_6 … #define ICH_ALI_SC_PCM_246_MASK … #define ICH_ALI_SS_SEC_ID … #define ICH_ALI_SS_PRI_ID … #define ICH_ALI_IF_AC97SP … #define ICH_ALI_IF_MC … #define ICH_ALI_IF_PI … #define ICH_ALI_IF_MC2 … #define ICH_ALI_IF_PI2 … #define ICH_ALI_IF_LINE_SRC … #define ICH_ALI_IF_MIC_SRC … #define ICH_ALI_IF_SPDF_SRC … #define ICH_ALI_IF_AC97_OUT … #define ICH_ALI_IF_PO_SPDF … #define ICH_ALI_IF_PO … /* * */ enum { … }; enum { … }; enum { … }; #define get_ichdev(substream) … struct ichdev { … }; struct intel8x0 { … }; static const struct pci_device_id snd_intel8x0_ids[] = …; MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids); /* * Lowlevel I/O - busmaster */ static inline u8 igetbyte(struct intel8x0 *chip, u32 offset) { … } static inline u16 igetword(struct intel8x0 *chip, u32 offset) { … } static inline u32 igetdword(struct intel8x0 *chip, u32 offset) { … } static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val) { … } static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val) { … } static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val) { … } /* * Lowlevel I/O - AC'97 registers */ static inline u16 iagetword(struct intel8x0 *chip, u32 offset) { … } static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val) { … } /* * Basic I/O */ /* * access to AC97 codec via normal i/o (for ICH and SIS7012) */ static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec) { … } static void snd_intel8x0_codec_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) { … } static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97, unsigned short reg) { … } static void snd_intel8x0_codec_read_test(struct intel8x0 *chip, unsigned int codec) { … } /* * access to AC97 for Ali5455 */ static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask) { … } static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip) { … } static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg) { … } static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) { … } /* * DMA I/O */ static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev) { … } /* * Interrupt handler */ static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev) { … } static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id) { … } /* * PCM part */ static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd) { … } static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd) { … } static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) { … } static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream) { … } static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip, struct snd_pcm_runtime *runtime) { … } static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream) { … } static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream) { … } static const struct snd_pcm_hardware snd_intel8x0_stream = …; static const unsigned int channels4[] = …; static const struct snd_pcm_hw_constraint_list hw_constraints_channels4 = …; static const unsigned int channels6[] = …; static const struct snd_pcm_hw_constraint_list hw_constraints_channels6 = …; static const unsigned int channels8[] = …; static const struct snd_pcm_hw_constraint_list hw_constraints_channels8 = …; static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev) { … } static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream) { … } static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream) { … } static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream) { … } static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream) { … } static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream) { … } static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream) { … } static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream) { … } static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream) { … } static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream) { … } static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream) { … } static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream) { … } static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream) { … } static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream) { … } static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream) { … } #if 0 // NYI static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream) { struct intel8x0 *chip = snd_pcm_substream_chip(substream); return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]); } static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream) { struct intel8x0 *chip = snd_pcm_substream_chip(substream); chip->ichd[ALID_SPDIFIN].substream = NULL; return 0; } static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream) { struct intel8x0 *chip = snd_pcm_substream_chip(substream); return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]); } static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream) { struct intel8x0 *chip = snd_pcm_substream_chip(substream); chip->ichd[ALID_SPDIFOUT].substream = NULL; return 0; } #endif static const struct snd_pcm_ops snd_intel8x0_playback_ops = …; static const struct snd_pcm_ops snd_intel8x0_capture_ops = …; static const struct snd_pcm_ops snd_intel8x0_capture_mic_ops = …; static const struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = …; static const struct snd_pcm_ops snd_intel8x0_capture2_ops = …; static const struct snd_pcm_ops snd_intel8x0_spdif_ops = …; static const struct snd_pcm_ops snd_intel8x0_ali_playback_ops = …; static const struct snd_pcm_ops snd_intel8x0_ali_capture_ops = …; static const struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = …; static const struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = …; #if 0 // NYI static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = { .open = snd_intel8x0_ali_spdifin_open, .close = snd_intel8x0_ali_spdifin_close, .hw_params = snd_intel8x0_hw_params, .hw_free = snd_intel8x0_hw_free, .prepare = snd_intel8x0_pcm_prepare, .trigger = snd_intel8x0_pcm_trigger, .pointer = snd_intel8x0_pcm_pointer, }; static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = { .open = snd_intel8x0_ali_spdifout_open, .close = snd_intel8x0_ali_spdifout_close, .hw_params = snd_intel8x0_hw_params, .hw_free = snd_intel8x0_hw_free, .prepare = snd_intel8x0_pcm_prepare, .trigger = snd_intel8x0_pcm_trigger, .pointer = snd_intel8x0_pcm_pointer, }; #endif // NYI struct ich_pcm_table { … }; #define intel8x0_dma_type(chip) … static int snd_intel8x0_pcm1(struct intel8x0 *chip, int device, const struct ich_pcm_table *rec) { … } static const struct ich_pcm_table intel_pcms[] = …; static const struct ich_pcm_table nforce_pcms[] = …; static const struct ich_pcm_table ali_pcms[] = …; static int snd_intel8x0_pcm(struct intel8x0 *chip) { … } /* * Mixer part */ static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus) { … } static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97) { … } static const struct ac97_pcm ac97_pcm_defs[] = …; static const struct ac97_quirk ac97_quirks[] = …; static int snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock, const char *quirk_override) { … } /* * */ static void do_ali_reset(struct intel8x0 *chip) { … } #ifdef CONFIG_SND_AC97_POWER_SAVE static const struct snd_pci_quirk ich_chip_reset_mode[] = …; static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip) { … } #define snd_intel8x0_ich_chip_can_cold_reset(chip) … #else #define snd_intel8x0_ich_chip_cold_reset … #define snd_intel8x0_ich_chip_can_cold_reset … #endif static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip) { … } static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing) { … } static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing) { … } static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing) { … } static void snd_intel8x0_free(struct snd_card *card) { … } /* * power management */ static int intel8x0_suspend(struct device *dev) { … } static int intel8x0_resume(struct device *dev) { … } static DEFINE_SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume); #define INTEL8X0_TESTBUF_SIZE … static void intel8x0_measure_ac97_clock(struct intel8x0 *chip) { … } static const struct snd_pci_quirk intel8x0_clock_list[] = …; static int intel8x0_in_clock_list(struct intel8x0 *chip) { … } static void snd_intel8x0_proc_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer) { … } static void snd_intel8x0_proc_init(struct intel8x0 *chip) { … } struct ich_reg_info { … }; static const unsigned int ich_codec_bits[3] = …; static const unsigned int sis_codec_bits[3] = …; static int snd_intel8x0_inside_vm(struct pci_dev *pci) { … } static int snd_intel8x0_init(struct snd_card *card, struct pci_dev *pci, unsigned long device_type) { … } static struct shortname_table { … } shortnames[] = …; static const struct snd_pci_quirk spdif_aclink_defaults[] = …; /* look up allow/deny list for SPDIF over ac-link */ static int check_default_spdif_aclink(struct pci_dev *pci) { … } static int __snd_intel8x0_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { … } static int snd_intel8x0_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { … } static struct pci_driver intel8x0_driver = …; module_pci_driver(…) …;
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