/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8550_H #define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8550_H /* CAM_CC clocks */ #define CAM_CC_BPS_AHB_CLK … #define CAM_CC_BPS_CLK … #define CAM_CC_BPS_CLK_SRC … #define CAM_CC_BPS_FAST_AHB_CLK … #define CAM_CC_CAMNOC_AXI_CLK … #define CAM_CC_CAMNOC_AXI_CLK_SRC … #define CAM_CC_CAMNOC_DCD_XO_CLK … #define CAM_CC_CAMNOC_XO_CLK … #define CAM_CC_CCI_0_CLK … #define CAM_CC_CCI_0_CLK_SRC … #define CAM_CC_CCI_1_CLK … #define CAM_CC_CCI_1_CLK_SRC … #define CAM_CC_CCI_2_CLK … #define CAM_CC_CCI_2_CLK_SRC … #define CAM_CC_CORE_AHB_CLK … #define CAM_CC_CPAS_AHB_CLK … #define CAM_CC_CPAS_BPS_CLK … #define CAM_CC_CPAS_CRE_CLK … #define CAM_CC_CPAS_FAST_AHB_CLK … #define CAM_CC_CPAS_IFE_0_CLK … #define CAM_CC_CPAS_IFE_1_CLK … #define CAM_CC_CPAS_IFE_2_CLK … #define CAM_CC_CPAS_IFE_LITE_CLK … #define CAM_CC_CPAS_IPE_NPS_CLK … #define CAM_CC_CPAS_SBI_CLK … #define CAM_CC_CPAS_SFE_0_CLK … #define CAM_CC_CPAS_SFE_1_CLK … #define CAM_CC_CPHY_RX_CLK_SRC … #define CAM_CC_CRE_AHB_CLK … #define CAM_CC_CRE_CLK … #define CAM_CC_CRE_CLK_SRC … #define CAM_CC_CSI0PHYTIMER_CLK … #define CAM_CC_CSI0PHYTIMER_CLK_SRC … #define CAM_CC_CSI1PHYTIMER_CLK … #define CAM_CC_CSI1PHYTIMER_CLK_SRC … #define CAM_CC_CSI2PHYTIMER_CLK … #define CAM_CC_CSI2PHYTIMER_CLK_SRC … #define CAM_CC_CSI3PHYTIMER_CLK … #define CAM_CC_CSI3PHYTIMER_CLK_SRC … #define CAM_CC_CSI4PHYTIMER_CLK … #define CAM_CC_CSI4PHYTIMER_CLK_SRC … #define CAM_CC_CSI5PHYTIMER_CLK … #define CAM_CC_CSI5PHYTIMER_CLK_SRC … #define CAM_CC_CSI6PHYTIMER_CLK … #define CAM_CC_CSI6PHYTIMER_CLK_SRC … #define CAM_CC_CSI7PHYTIMER_CLK … #define CAM_CC_CSI7PHYTIMER_CLK_SRC … #define CAM_CC_CSID_CLK … #define CAM_CC_CSID_CLK_SRC … #define CAM_CC_CSID_CSIPHY_RX_CLK … #define CAM_CC_CSIPHY0_CLK … #define CAM_CC_CSIPHY1_CLK … #define CAM_CC_CSIPHY2_CLK … #define CAM_CC_CSIPHY3_CLK … #define CAM_CC_CSIPHY4_CLK … #define CAM_CC_CSIPHY5_CLK … #define CAM_CC_CSIPHY6_CLK … #define CAM_CC_CSIPHY7_CLK … #define CAM_CC_DRV_AHB_CLK … #define CAM_CC_DRV_XO_CLK … #define CAM_CC_FAST_AHB_CLK_SRC … #define CAM_CC_GDSC_CLK … #define CAM_CC_ICP_AHB_CLK … #define CAM_CC_ICP_CLK … #define CAM_CC_ICP_CLK_SRC … #define CAM_CC_IFE_0_CLK … #define CAM_CC_IFE_0_CLK_SRC … #define CAM_CC_IFE_0_DSP_CLK … #define CAM_CC_IFE_0_DSP_CLK_SRC … #define CAM_CC_IFE_0_FAST_AHB_CLK … #define CAM_CC_IFE_1_CLK … #define CAM_CC_IFE_1_CLK_SRC … #define CAM_CC_IFE_1_DSP_CLK … #define CAM_CC_IFE_1_DSP_CLK_SRC … #define CAM_CC_IFE_1_FAST_AHB_CLK … #define CAM_CC_IFE_2_CLK … #define CAM_CC_IFE_2_CLK_SRC … #define CAM_CC_IFE_2_DSP_CLK … #define CAM_CC_IFE_2_DSP_CLK_SRC … #define CAM_CC_IFE_2_FAST_AHB_CLK … #define CAM_CC_IFE_LITE_AHB_CLK … #define CAM_CC_IFE_LITE_CLK … #define CAM_CC_IFE_LITE_CLK_SRC … #define CAM_CC_IFE_LITE_CPHY_RX_CLK … #define CAM_CC_IFE_LITE_CSID_CLK … #define CAM_CC_IFE_LITE_CSID_CLK_SRC … #define CAM_CC_IPE_NPS_AHB_CLK … #define CAM_CC_IPE_NPS_CLK … #define CAM_CC_IPE_NPS_CLK_SRC … #define CAM_CC_IPE_NPS_FAST_AHB_CLK … #define CAM_CC_IPE_PPS_CLK … #define CAM_CC_IPE_PPS_FAST_AHB_CLK … #define CAM_CC_JPEG_1_CLK … #define CAM_CC_JPEG_CLK … #define CAM_CC_JPEG_CLK_SRC … #define CAM_CC_MCLK0_CLK … #define CAM_CC_MCLK0_CLK_SRC … #define CAM_CC_MCLK1_CLK … #define CAM_CC_MCLK1_CLK_SRC … #define CAM_CC_MCLK2_CLK … #define CAM_CC_MCLK2_CLK_SRC … #define CAM_CC_MCLK3_CLK … #define CAM_CC_MCLK3_CLK_SRC … #define CAM_CC_MCLK4_CLK … #define CAM_CC_MCLK4_CLK_SRC … #define CAM_CC_MCLK5_CLK … #define CAM_CC_MCLK5_CLK_SRC … #define CAM_CC_MCLK6_CLK … #define CAM_CC_MCLK6_CLK_SRC … #define CAM_CC_MCLK7_CLK … #define CAM_CC_MCLK7_CLK_SRC … #define CAM_CC_PLL0 … #define CAM_CC_PLL0_OUT_EVEN … #define CAM_CC_PLL0_OUT_ODD … #define CAM_CC_PLL1 … #define CAM_CC_PLL1_OUT_EVEN … #define CAM_CC_PLL2 … #define CAM_CC_PLL3 … #define CAM_CC_PLL3_OUT_EVEN … #define CAM_CC_PLL4 … #define CAM_CC_PLL4_OUT_EVEN … #define CAM_CC_PLL5 … #define CAM_CC_PLL5_OUT_EVEN … #define CAM_CC_PLL6 … #define CAM_CC_PLL6_OUT_EVEN … #define CAM_CC_PLL7 … #define CAM_CC_PLL7_OUT_EVEN … #define CAM_CC_PLL8 … #define CAM_CC_PLL8_OUT_EVEN … #define CAM_CC_PLL9 … #define CAM_CC_PLL9_OUT_EVEN … #define CAM_CC_PLL10 … #define CAM_CC_PLL10_OUT_EVEN … #define CAM_CC_PLL11 … #define CAM_CC_PLL11_OUT_EVEN … #define CAM_CC_PLL12 … #define CAM_CC_PLL12_OUT_EVEN … #define CAM_CC_QDSS_DEBUG_CLK … #define CAM_CC_QDSS_DEBUG_CLK_SRC … #define CAM_CC_QDSS_DEBUG_XO_CLK … #define CAM_CC_SBI_CLK … #define CAM_CC_SBI_FAST_AHB_CLK … #define CAM_CC_SFE_0_CLK … #define CAM_CC_SFE_0_CLK_SRC … #define CAM_CC_SFE_0_FAST_AHB_CLK … #define CAM_CC_SFE_1_CLK … #define CAM_CC_SFE_1_CLK_SRC … #define CAM_CC_SFE_1_FAST_AHB_CLK … #define CAM_CC_SLEEP_CLK … #define CAM_CC_SLEEP_CLK_SRC … #define CAM_CC_SLOW_AHB_CLK_SRC … #define CAM_CC_XO_CLK_SRC … /* CAM_CC power domains */ #define CAM_CC_BPS_GDSC … #define CAM_CC_IFE_0_GDSC … #define CAM_CC_IFE_1_GDSC … #define CAM_CC_IFE_2_GDSC … #define CAM_CC_IPE_0_GDSC … #define CAM_CC_SBI_GDSC … #define CAM_CC_SFE_0_GDSC … #define CAM_CC_SFE_1_GDSC … #define CAM_CC_TITAN_TOP_GDSC … /* CAM_CC resets */ #define CAM_CC_BPS_BCR … #define CAM_CC_DRV_BCR … #define CAM_CC_ICP_BCR … #define CAM_CC_IFE_0_BCR … #define CAM_CC_IFE_1_BCR … #define CAM_CC_IFE_2_BCR … #define CAM_CC_IPE_0_BCR … #define CAM_CC_QDSS_DEBUG_BCR … #define CAM_CC_SBI_BCR … #define CAM_CC_SFE_0_BCR … #define CAM_CC_SFE_1_BCR … #endif
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