// SPDX-License-Identifier: GPL-2.0-only // motu-protocol-v1.c - a part of driver for MOTU FireWire series // // Copyright (c) 2021 Takashi Sakamoto <[email protected]> #include "motu.h" #include <linux/delay.h> // Status register for MOTU 828 (0x'ffff'f000'0b00). // // 0xffff0000: ISOC_COMM_CONTROL_MASK in motu-stream.c. // 0x00008000: mode of optical input interface. // 0x00008000: for S/PDIF signal. // 0x00000000: disabled or for ADAT signal. // 0x00004000: mode of optical output interface. // 0x00004000: for S/PDIF signal. // 0x00000000: disabled or for ADAT signal. // 0x00003f00: monitor input mode. // 0x00000800: analog-1/2 // 0x00001a00: analog-3/4 // 0x00002c00: analog-5/6 // 0x00003e00: analog-7/8 // 0x00000000: analog-1 // 0x00000900: analog-2 // 0x00001200: analog-3 // 0x00001b00: analog-4 // 0x00002400: analog-5 // 0x00002d00: analog-6 // 0x00003600: analog-7 // 0x00003f00: analog-8 // 0x00000080: enable stream input. // 0x00000040: disable monitor input. // 0x00000008: enable main out. // 0x00000004: rate of sampling clock. // 0x00000004: 48.0 kHz // 0x00000000: 44.1 kHz // 0x00000023: source of sampling clock. // 0x00000003: source packet header (SPH) // 0x00000002: S/PDIF on optical/coaxial interface. // 0x00000021: ADAT on optical interface // 0x00000001: ADAT on Dsub 9pin // 0x00000000: internal #define CLK_828_STATUS_OFFSET … #define CLK_828_STATUS_MASK … #define CLK_828_STATUS_FLAG_OPT_IN_IFACE_IS_SPDIF … #define CLK_828_STATUS_FLAG_OPT_OUT_IFACE_IS_SPDIF … #define CLK_828_STATUS_FLAG_FETCH_PCM_FRAMES … #define CLK_828_STATUS_FLAG_ENABLE_OUTPUT … #define CLK_828_STATUS_FLAG_RATE_48000 … #define CLK_828_STATUS_MASK_SRC … #define CLK_828_STATUS_FLAG_SRC_ADAT_ON_OPT … #define CLK_828_STATUS_FLAG_SRC_SPH … #define CLK_828_STATUS_FLAG_SRC_SPDIF … #define CLK_828_STATUS_FLAG_SRC_ADAT_ON_DSUB … #define CLK_828_STATUS_FLAG_SRC_INTERNAL … // Status register for MOTU 896 (0x'ffff'f000'0b14). // // 0xf0000000: enable physical and stream input to DAC. // 0x80000000: disable // 0x40000000: disable // 0x20000000: enable (prior to the other bits) // 0x10000000: disable // 0x00000000: disable // 0x08000000: speed of word clock signal output on BNC interface. // 0x00000000: force to low rate (44.1/48.0 kHz). // 0x08000000: follow to system clock. // 0x04000000: something relevant to clock. // 0x03000000: enable output. // 0x02000000: enabled irreversibly once standing unless the device voluntarily disables it. // 0x01000000: enabled irreversibly once standing unless the device voluntarily disables it. // 0x00ffff00: monitor input mode. // 0x00000000: disabled // 0x00004800: analog-1/2 // 0x00005a00: analog-3/4 // 0x00006c00: analog-5/6 // 0x00007e00: analog-7/8 // 0x00104800: AES/EBU-1/2 // 0x00004000: analog-1 // 0x00004900: analog-2 // 0x00005200: analog-3 // 0x00005b00: analog-4 // 0x00006400: analog-5 // 0x00006d00: analog-6 // 0x00007600: analog-7 // 0x00007f00: analog-8 // 0x00104000: AES/EBU-1 // 0x00104900: AES/EBU-2 // 0x00000060: sample rate conversion for AES/EBU input/output. // 0x00000000: None // 0x00000020: input signal is converted to system rate // 0x00000040: output is slave to input, ignoring system rate // 0x00000060: output is double rate than system rate // 0x00000018: nominal rate of sampling clock. // 0x00000000: 44.1 kHz // 0x00000008: 48.0 kHz // 0x00000010: 88.2 kHz // 0x00000018: 96.0 kHz // 0x00000007: source of sampling clock. // 0x00000000: internal // 0x00000001: ADAT on optical interface // 0x00000002: AES/EBU on XLR // 0x00000003: source packet header (SPH) // 0x00000004: word clock on BNC // 0x00000005: ADAT on Dsub 9pin #define CLK_896_STATUS_OFFSET … #define CLK_896_STATUS_FLAG_FETCH_ENABLE … #define CLK_896_STATUS_FLAG_OUTPUT_ON … #define CLK_896_STATUS_MASK_SRC … #define CLK_896_STATUS_FLAG_SRC_INTERNAL … #define CLK_896_STATUS_FLAG_SRC_ADAT_ON_OPT … #define CLK_896_STATUS_FLAG_SRC_AESEBU … #define CLK_896_STATUS_FLAG_SRC_SPH … #define CLK_896_STATUS_FLAG_SRC_WORD … #define CLK_896_STATUS_FLAG_SRC_ADAT_ON_DSUB … #define CLK_896_STATUS_MASK_RATE … #define CLK_896_STATUS_FLAG_RATE_44100 … #define CLK_896_STATUS_FLAG_RATE_48000 … #define CLK_896_STATUS_FLAG_RATE_88200 … #define CLK_896_STATUS_FLAG_RATE_96000 … static void parse_clock_rate_828(u32 data, unsigned int *rate) { … } static int get_clock_rate_828(struct snd_motu *motu, unsigned int *rate) { … } static int parse_clock_rate_896(u32 data, unsigned int *rate) { … } static int get_clock_rate_896(struct snd_motu *motu, unsigned int *rate) { … } int snd_motu_protocol_v1_get_clock_rate(struct snd_motu *motu, unsigned int *rate) { … } static int set_clock_rate_828(struct snd_motu *motu, unsigned int rate) { … } static int set_clock_rate_896(struct snd_motu *motu, unsigned int rate) { … } int snd_motu_protocol_v1_set_clock_rate(struct snd_motu *motu, unsigned int rate) { … } static int get_clock_source_828(struct snd_motu *motu, enum snd_motu_clock_source *src) { … } static int get_clock_source_896(struct snd_motu *motu, enum snd_motu_clock_source *src) { … } int snd_motu_protocol_v1_get_clock_source(struct snd_motu *motu, enum snd_motu_clock_source *src) { … } static int switch_fetching_mode_828(struct snd_motu *motu, bool enable) { … } static int switch_fetching_mode_896(struct snd_motu *motu, bool enable) { … } int snd_motu_protocol_v1_switch_fetching_mode(struct snd_motu *motu, bool enable) { … } static int detect_packet_formats_828(struct snd_motu *motu) { … } static int detect_packet_formats_896(struct snd_motu *motu) { … } int snd_motu_protocol_v1_cache_packet_formats(struct snd_motu *motu) { … } const struct snd_motu_spec snd_motu_spec_828 = …; const struct snd_motu_spec snd_motu_spec_896 = …;
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