/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) ST-Ericsson SA 2010 * * Author: Srinidhi Kasagar <[email protected]> */ #ifndef MFD_AB8500_H #define MFD_AB8500_H #include <linux/atomic.h> #include <linux/mutex.h> #include <linux/irqdomain.h> struct device; /* * AB IC versions * * AB8500_VERSION_AB8500 should be 0xFF but will never be read as need a * non-supported multi-byte I2C access via PRCMU. Set to 0x00 to ease the * print of version string. */ enum ab8500_version { … }; /* AB8500 CIDs*/ #define AB8500_CUTEARLY … #define AB8500_CUT1P0 … #define AB8500_CUT1P1 … #define AB8500_CUT1P2 … #define AB8500_CUT2P0 … #define AB8500_CUT3P0 … #define AB8500_CUT3P3 … /* * AB8500 bank addresses */ #define AB8500_M_FSM_RANK … #define AB8500_SYS_CTRL1_BLOCK … #define AB8500_SYS_CTRL2_BLOCK … #define AB8500_REGU_CTRL1 … #define AB8500_REGU_CTRL2 … #define AB8500_USB … #define AB8500_TVOUT … #define AB8500_DBI … #define AB8500_ECI_AV_ACC … #define AB8500_RESERVED … #define AB8500_GPADC … #define AB8500_CHARGER … #define AB8500_GAS_GAUGE … #define AB8500_AUDIO … #define AB8500_INTERRUPT … #define AB8500_RTC … #define AB8500_MISC … #define AB8500_DEVELOPMENT … #define AB8500_DEBUG … #define AB8500_PROD_TEST … #define AB8500_STE_TEST … #define AB8500_OTP_EMUL … #define AB8500_DEBUG_FIELD_LAST … /* * Interrupts * Values used to index into array ab8500_irq_regoffset[] defined in * drivers/mdf/ab8500-core.c */ /* Definitions for AB8500, AB9540 and AB8540 */ /* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */ #define AB8500_INT_MAIN_EXT_CH_NOT_OK … #define AB8500_INT_UN_PLUG_TV_DET … #define AB8500_INT_PLUG_TV_DET … #define AB8500_INT_TEMP_WARM … #define AB8500_INT_PON_KEY2DB_F … #define AB8500_INT_PON_KEY2DB_R … #define AB8500_INT_PON_KEY1DB_F … #define AB8500_INT_PON_KEY1DB_R … /* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */ #define AB8500_INT_BATT_OVV … #define AB8500_INT_MAIN_CH_UNPLUG_DET … #define AB8500_INT_MAIN_CH_PLUG_DET … #define AB8500_INT_VBUS_DET_F … #define AB8500_INT_VBUS_DET_R … /* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */ #define AB8500_INT_VBUS_CH_DROP_END … #define AB8500_INT_RTC_60S … #define AB8500_INT_RTC_ALARM … #define AB8540_INT_BIF_INT … #define AB8500_INT_BAT_CTRL_INDB … #define AB8500_INT_CH_WD_EXP … #define AB8500_INT_VBUS_OVV … #define AB8500_INT_MAIN_CH_DROP_END … /* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */ #define AB8500_INT_CCN_CONV_ACC … #define AB8500_INT_INT_AUD … #define AB8500_INT_CCEOC … #define AB8500_INT_CC_INT_CALIB … #define AB8500_INT_LOW_BAT_F … #define AB8500_INT_LOW_BAT_R … #define AB8500_INT_BUP_CHG_NOT_OK … #define AB8500_INT_BUP_CHG_OK … /* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */ #define AB8500_INT_GP_HW_ADC_CONV_END … #define AB8500_INT_ACC_DETECT_1DB_F … #define AB8500_INT_ACC_DETECT_1DB_R … #define AB8500_INT_ACC_DETECT_22DB_F … #define AB8500_INT_ACC_DETECT_22DB_R … #define AB8500_INT_ACC_DETECT_21DB_F … #define AB8500_INT_ACC_DETECT_21DB_R … #define AB8500_INT_GP_SW_ADC_CONV_END … /* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */ #define AB8500_INT_GPIO6R … #define AB8500_INT_GPIO7R … #define AB8500_INT_GPIO8R … #define AB8500_INT_GPIO9R … #define AB8500_INT_GPIO10R … #define AB8500_INT_GPIO11R … #define AB8500_INT_GPIO12R … #define AB8500_INT_GPIO13R … /* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */ #define AB8500_INT_GPIO24R … #define AB8500_INT_GPIO25R … #define AB8500_INT_GPIO36R … #define AB8500_INT_GPIO37R … #define AB8500_INT_GPIO38R … #define AB8500_INT_GPIO39R … #define AB8500_INT_GPIO40R … #define AB8500_INT_GPIO41R … /* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */ #define AB8500_INT_GPIO6F … #define AB8500_INT_GPIO7F … #define AB8500_INT_GPIO8F … #define AB8500_INT_GPIO9F … #define AB8500_INT_GPIO10F … #define AB8500_INT_GPIO11F … #define AB8500_INT_GPIO12F … #define AB8500_INT_GPIO13F … /* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */ #define AB8500_INT_GPIO24F … #define AB8500_INT_GPIO25F … #define AB8500_INT_GPIO36F … #define AB8500_INT_GPIO37F … #define AB8500_INT_GPIO38F … #define AB8500_INT_GPIO39F … #define AB8500_INT_GPIO40F … #define AB8500_INT_GPIO41F … /* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */ #define AB8500_INT_ADP_SOURCE_ERROR … #define AB8500_INT_ADP_SINK_ERROR … #define AB8500_INT_ADP_PROBE_PLUG … #define AB8500_INT_ADP_PROBE_UNPLUG … #define AB8500_INT_ADP_SENSE_OFF … #define AB8500_INT_USB_PHY_POWER_ERR … #define AB8500_INT_USB_LINK_STATUS … /* ab8500_irq_regoffset[10] -> IT[Source|Latch|Mask]19 */ #define AB8500_INT_BTEMP_LOW … #define AB8500_INT_BTEMP_LOW_MEDIUM … #define AB8500_INT_BTEMP_MEDIUM_HIGH … #define AB8500_INT_BTEMP_HIGH … /* ab8500_irq_regoffset[11] -> IT[Source|Latch|Mask]20 */ #define AB8500_INT_SRP_DETECT … #define AB8500_INT_USB_CHARGER_NOT_OKR … #define AB8500_INT_ID_WAKEUP_R … #define AB8500_INT_ID_DET_PLUGR … #define AB8500_INT_ID_DET_R1R … #define AB8500_INT_ID_DET_R2R … #define AB8500_INT_ID_DET_R3R … #define AB8500_INT_ID_DET_R4R … /* ab8500_irq_regoffset[12] -> IT[Source|Latch|Mask]21 */ #define AB8500_INT_ID_WAKEUP_F … #define AB8500_INT_ID_DET_PLUGF … #define AB8500_INT_ID_DET_R1F … #define AB8500_INT_ID_DET_R2F … #define AB8500_INT_ID_DET_R3F … #define AB8500_INT_ID_DET_R4F … #define AB8500_INT_CHAUTORESTARTAFTSEC … #define AB8500_INT_CHSTOPBYSEC … /* ab8500_irq_regoffset[13] -> IT[Source|Latch|Mask]22 */ #define AB8500_INT_USB_CH_TH_PROT_F … #define AB8500_INT_USB_CH_TH_PROT_R … #define AB8500_INT_MAIN_CH_TH_PROT_F … #define AB8500_INT_MAIN_CH_TH_PROT_R … #define AB8500_INT_CHCURLIMNOHSCHIRP … #define AB8500_INT_CHCURLIMHSCHIRP … #define AB8500_INT_XTAL32K_KO … /* Definitions for AB9540 / AB8505 */ /* ab8500_irq_regoffset[14] -> IT[Source|Latch|Mask]13 */ #define AB9540_INT_GPIO50R … #define AB9540_INT_GPIO51R … #define AB9540_INT_GPIO52R … #define AB9540_INT_GPIO53R … #define AB9540_INT_GPIO54R … #define AB9540_INT_IEXT_CH_RF_BFN_R … /* ab8500_irq_regoffset[15] -> IT[Source|Latch|Mask]14 */ #define AB9540_INT_GPIO50F … #define AB9540_INT_GPIO51F … #define AB9540_INT_GPIO52F … #define AB9540_INT_GPIO53F … #define AB9540_INT_GPIO54F … #define AB9540_INT_IEXT_CH_RF_BFN_F … /* ab8500_irq_regoffset[16] -> IT[Source|Latch|Mask]25 */ #define AB8505_INT_KEYSTUCK … #define AB8505_INT_IKR … #define AB8505_INT_IKP … #define AB8505_INT_KP … #define AB8505_INT_KEYDEGLITCH … #define AB8505_INT_MODPWRSTATUSF … #define AB8505_INT_MODPWRSTATUSR … /* ab8500_irq_regoffset[17] -> IT[Source|Latch|Mask]6 */ #define AB8500_INT_HOOK_DET_NEG_F … #define AB8500_INT_HOOK_DET_NEG_R … #define AB8500_INT_HOOK_DET_POS_F … #define AB8500_INT_HOOK_DET_POS_R … #define AB8500_INT_PLUG_DET_COMP_F … #define AB8500_INT_PLUG_DET_COMP_R … /* ab8500_irq_regoffset[18] -> IT[Source|Latch|Mask]23 */ #define AB8505_INT_COLL … #define AB8505_INT_RESERR … #define AB8505_INT_FRAERR … #define AB8505_INT_COMERR … #define AB8505_INT_SPDSET … #define AB8505_INT_DSENT … #define AB8505_INT_DREC … #define AB8505_INT_ACC_INT … /* ab8500_irq_regoffset[19] -> IT[Source|Latch|Mask]24 */ #define AB8505_INT_NOPINT … /* ab8540_irq_regoffset[20] -> IT[Source|Latch|Mask]26 */ #define AB8540_INT_IDPLUGDETCOMPF … #define AB8540_INT_IDPLUGDETCOMPR … #define AB8540_INT_FMDETCOMPLOF … #define AB8540_INT_FMDETCOMPLOR … #define AB8540_INT_FMDETCOMPHIF … #define AB8540_INT_FMDETCOMPHIR … #define AB8540_INT_ID5VDETCOMPF … #define AB8540_INT_ID5VDETCOMPR … /* ab8540_irq_regoffset[21] -> IT[Source|Latch|Mask]27 */ #define AB8540_INT_GPIO43F … #define AB8540_INT_GPIO43R … #define AB8540_INT_GPIO44F … #define AB8540_INT_GPIO44R … #define AB8540_INT_KEYPOSDETCOMPF … #define AB8540_INT_KEYPOSDETCOMPR … #define AB8540_INT_KEYNEGDETCOMPF … #define AB8540_INT_KEYNEGDETCOMPR … /* ab8540_irq_regoffset[22] -> IT[Source|Latch|Mask]28 */ #define AB8540_INT_GPIO1VBATF … #define AB8540_INT_GPIO1VBATR … #define AB8540_INT_GPIO2VBATF … #define AB8540_INT_GPIO2VBATR … #define AB8540_INT_GPIO3VBATF … #define AB8540_INT_GPIO3VBATR … #define AB8540_INT_GPIO4VBATF … #define AB8540_INT_GPIO4VBATR … /* ab8540_irq_regoffset[23] -> IT[Source|Latch|Mask]29 */ #define AB8540_INT_SYSCLKREQ2F … #define AB8540_INT_SYSCLKREQ2R … #define AB8540_INT_SYSCLKREQ3F … #define AB8540_INT_SYSCLKREQ3R … #define AB8540_INT_SYSCLKREQ4F … #define AB8540_INT_SYSCLKREQ4R … #define AB8540_INT_SYSCLKREQ5F … #define AB8540_INT_SYSCLKREQ5R … /* ab8540_irq_regoffset[24] -> IT[Source|Latch|Mask]30 */ #define AB8540_INT_PWMOUT1F … #define AB8540_INT_PWMOUT1R … #define AB8540_INT_PWMCTRL0F … #define AB8540_INT_PWMCTRL0R … #define AB8540_INT_PWMCTRL1F … #define AB8540_INT_PWMCTRL1R … #define AB8540_INT_SYSCLKREQ6F … #define AB8540_INT_SYSCLKREQ6R … /* ab8540_irq_regoffset[25] -> IT[Source|Latch|Mask]31 */ #define AB8540_INT_PWMEXTVIBRA1F … #define AB8540_INT_PWMEXTVIBRA1R … #define AB8540_INT_PWMEXTVIBRA2F … #define AB8540_INT_PWMEXTVIBRA2R … #define AB8540_INT_PWMOUT2F … #define AB8540_INT_PWMOUT2R … #define AB8540_INT_PWMOUT3F … #define AB8540_INT_PWMOUT3R … /* ab8540_irq_regoffset[26] -> IT[Source|Latch|Mask]32 */ #define AB8540_INT_ADDATA2F … #define AB8540_INT_ADDATA2R … #define AB8540_INT_DADATA2F … #define AB8540_INT_DADATA2R … #define AB8540_INT_FSYNC2F … #define AB8540_INT_FSYNC2R … #define AB8540_INT_BITCLK2F … #define AB8540_INT_BITCLK2R … /* ab8540_irq_regoffset[27] -> IT[Source|Latch|Mask]33 */ #define AB8540_INT_RTC_1S … /* * AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the * entire platform. This is a "compile time" constant so this must be set to * the largest possible value that may be encountered with different AB SOCs. * Of the currently supported AB devices, AB8500 and AB9540, it is the AB9540 * which is larger. */ #define AB8500_NR_IRQS … #define AB8505_NR_IRQS … #define AB9540_NR_IRQS … #define AB8540_NR_IRQS … /* This is set to the roof of any AB8500 chip variant IRQ counts */ #define AB8500_MAX_NR_IRQS … #define AB8500_NUM_IRQ_REGS … #define AB9540_NUM_IRQ_REGS … #define AB8540_NUM_IRQ_REGS … /* Turn On Status Event */ #define AB8500_POR_ON_VBAT … #define AB8500_POW_KEY_1_ON … #define AB8500_POW_KEY_2_ON … #define AB8500_RTC_ALARM … #define AB8500_MAIN_CH_DET … #define AB8500_VBUS_DET … #define AB8500_USB_ID_DET … /** * struct ab8500 - ab8500 internal structure * @dev: parent device * @lock: read/write operations lock * @irq_lock: genirq bus lock * @transfer_ongoing: 0 if no transfer ongoing * @irq: irq line * @irq_domain: irq domain * @version: chip version id (e.g. ab8500 or ab9540) * @chip_id: chip revision id * @write: register write * @write_masked: masked register write * @read: register read * @rx_buf: rx buf for SPI * @tx_buf: tx buf for SPI * @mask: cache of IRQ regs for bus lock * @oldmask: cache of previous IRQ regs for bus lock * @mask_size: Actual number of valid entries in mask[], oldmask[] and * irq_reg_offset * @irq_reg_offset: Array of offsets into IRQ registers */ struct ab8500 { … }; struct ab8500_codec_platform_data; struct ab8500_sysctrl_platform_data; /** * struct ab8500_platform_data - AB8500 platform data * @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used * @init: board-specific initialization after detection of ab8500 */ struct ab8500_platform_data { … }; extern int ab8500_suspend(struct ab8500 *ab8500); static inline int is_ab8500(struct ab8500 *ab) { … } static inline int is_ab8505(struct ab8500 *ab) { … } static inline int is_ab9540(struct ab8500 *ab) { … } static inline int is_ab8540(struct ab8500 *ab) { … } /* exclude also ab8505, ab9540... */ static inline int is_ab8500_1p0_or_earlier(struct ab8500 *ab) { … } /* exclude also ab8505, ab9540... */ static inline int is_ab8500_1p1_or_earlier(struct ab8500 *ab) { … } /* exclude also ab8505, ab9540... */ static inline int is_ab8500_2p0_or_earlier(struct ab8500 *ab) { … } static inline int is_ab8500_3p3_or_earlier(struct ab8500 *ab) { … } /* exclude also ab8505, ab9540... */ static inline int is_ab8500_2p0(struct ab8500 *ab) { … } static inline int is_ab8505_1p0_or_earlier(struct ab8500 *ab) { … } static inline int is_ab8505_2p0(struct ab8500 *ab) { … } static inline int is_ab9540_1p0_or_earlier(struct ab8500 *ab) { … } static inline int is_ab9540_2p0(struct ab8500 *ab) { … } /* * Be careful, the marketing name for this chip is 2.1 * but the value read from the chip is 3.0 (0x30) */ static inline int is_ab9540_3p0(struct ab8500 *ab) { … } static inline int is_ab8540_1p0_or_earlier(struct ab8500 *ab) { … } static inline int is_ab8540_1p1_or_earlier(struct ab8500 *ab) { … } static inline int is_ab8540_1p2_or_earlier(struct ab8500 *ab) { … } static inline int is_ab8540_2p0_or_earlier(struct ab8500 *ab) { … } static inline int is_ab8540_2p0(struct ab8500 *ab) { … } static inline int is_ab8505_2p0_earlier(struct ab8500 *ab) { … } static inline int is_ab9540_2p0_or_earlier(struct ab8500 *ab) { … } void ab8500_override_turn_on_stat(u8 mask, u8 set); static inline void ab8500_dump_all_banks(struct device *dev) { … } static inline void ab8500_debug_register_interrupt(int line) { … } #endif /* MFD_AB8500_H */
Codebase Browser
linux