linux/include/dt-bindings/clock/qcom,dispcc-sm8250.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
 */

#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H

/* DISP_CC clock registers */
#define DISP_CC_MDSS_AHB_CLK
#define DISP_CC_MDSS_AHB_CLK_SRC
#define DISP_CC_MDSS_BYTE0_CLK
#define DISP_CC_MDSS_BYTE0_CLK_SRC
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC
#define DISP_CC_MDSS_BYTE0_INTF_CLK
#define DISP_CC_MDSS_BYTE1_CLK
#define DISP_CC_MDSS_BYTE1_CLK_SRC
#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC
#define DISP_CC_MDSS_BYTE1_INTF_CLK
#define DISP_CC_MDSS_DP_AUX1_CLK
#define DISP_CC_MDSS_DP_AUX1_CLK_SRC
#define DISP_CC_MDSS_DP_AUX_CLK
#define DISP_CC_MDSS_DP_AUX_CLK_SRC
#define DISP_CC_MDSS_DP_LINK1_CLK
#define DISP_CC_MDSS_DP_LINK1_CLK_SRC
#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC
#define DISP_CC_MDSS_DP_LINK1_INTF_CLK
#define DISP_CC_MDSS_DP_LINK_CLK
#define DISP_CC_MDSS_DP_LINK_CLK_SRC
#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC
#define DISP_CC_MDSS_DP_LINK_INTF_CLK
#define DISP_CC_MDSS_DP_PIXEL1_CLK
#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC
#define DISP_CC_MDSS_DP_PIXEL2_CLK
#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC
#define DISP_CC_MDSS_DP_PIXEL_CLK
#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC
#define DISP_CC_MDSS_ESC0_CLK
#define DISP_CC_MDSS_ESC0_CLK_SRC
#define DISP_CC_MDSS_ESC1_CLK
#define DISP_CC_MDSS_ESC1_CLK_SRC
#define DISP_CC_MDSS_MDP_CLK
#define DISP_CC_MDSS_MDP_CLK_SRC
#define DISP_CC_MDSS_MDP_LUT_CLK
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK
#define DISP_CC_MDSS_PCLK0_CLK
#define DISP_CC_MDSS_PCLK0_CLK_SRC
#define DISP_CC_MDSS_PCLK1_CLK
#define DISP_CC_MDSS_PCLK1_CLK_SRC
#define DISP_CC_MDSS_ROT_CLK
#define DISP_CC_MDSS_ROT_CLK_SRC
#define DISP_CC_MDSS_RSCC_AHB_CLK
#define DISP_CC_MDSS_RSCC_VSYNC_CLK
#define DISP_CC_MDSS_VSYNC_CLK
#define DISP_CC_MDSS_VSYNC_CLK_SRC
#define DISP_CC_PLL0
#define DISP_CC_PLL1
#define DISP_CC_MDSS_EDP_AUX_CLK
#define DISP_CC_MDSS_EDP_AUX_CLK_SRC
#define DISP_CC_MDSS_EDP_GTC_CLK
#define DISP_CC_MDSS_EDP_GTC_CLK_SRC
#define DISP_CC_MDSS_EDP_LINK_CLK
#define DISP_CC_MDSS_EDP_LINK_CLK_SRC
#define DISP_CC_MDSS_EDP_LINK_INTF_CLK
#define DISP_CC_MDSS_EDP_PIXEL_CLK
#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC
#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC

/* DISP_CC Reset */
#define DISP_CC_MDSS_CORE_BCR
#define DISP_CC_MDSS_RSCC_BCR

/* DISP_CC GDSCR */
#define MDSS_GDSC

#endif