linux/sound/soc/codecs/cs53l30.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * ALSA SoC CS53L30 codec driver
 *
 * Copyright 2015 Cirrus Logic, Inc.
 *
 * Author: Paul Handrigan <[email protected]>,
 *         Tim Howe <[email protected]>
 */

#ifndef __CS53L30_H__
#define __CS53L30_H__

/* I2C Registers */
#define CS53L30_DEVID_AB
#define CS53L30_DEVID_CD
#define CS53L30_DEVID_E
#define CS53L30_REVID
#define CS53L30_PWRCTL
#define CS53L30_MCLKCTL
#define CS53L30_INT_SR_CTL
#define CS53L30_MICBIAS_CTL
#define CS53L30_ASPCFG_CTL
#define CS53L30_ASP_CTL1
#define CS53L30_ASP_TDMTX_CTL1
#define CS53L30_ASP_TDMTX_CTL2
#define CS53L30_ASP_TDMTX_CTL3
#define CS53L30_ASP_TDMTX_CTL4
#define CS53L30_ASP_TDMTX_EN1
#define CS53L30_ASP_TDMTX_EN2
#define CS53L30_ASP_TDMTX_EN3
#define CS53L30_ASP_TDMTX_EN4
#define CS53L30_ASP_TDMTX_EN5
#define CS53L30_ASP_TDMTX_EN6
#define CS53L30_ASP_CTL2
#define CS53L30_SFT_RAMP
#define CS53L30_LRCK_CTL1
#define CS53L30_LRCK_CTL2
#define CS53L30_MUTEP_CTL1
#define CS53L30_MUTEP_CTL2
#define CS53L30_INBIAS_CTL1
#define CS53L30_INBIAS_CTL2
#define CS53L30_DMIC1_STR_CTL
#define CS53L30_DMIC2_STR_CTL
#define CS53L30_ADCDMIC1_CTL1
#define CS53L30_ADCDMIC1_CTL2
#define CS53L30_ADC1_CTL3
#define CS53L30_ADC1_NG_CTL
#define CS53L30_ADC1A_AFE_CTL
#define CS53L30_ADC1B_AFE_CTL
#define CS53L30_ADC1A_DIG_VOL
#define CS53L30_ADC1B_DIG_VOL
#define CS53L30_ADCDMIC2_CTL1
#define CS53L30_ADCDMIC2_CTL2
#define CS53L30_ADC2_CTL3
#define CS53L30_ADC2_NG_CTL
#define CS53L30_ADC2A_AFE_CTL
#define CS53L30_ADC2B_AFE_CTL
#define CS53L30_ADC2A_DIG_VOL
#define CS53L30_ADC2B_DIG_VOL
#define CS53L30_INT_MASK
#define CS53L30_IS
#define CS53L30_MAX_REGISTER

#define CS53L30_TDM_SLOT_MAX
#define CS53L30_ASP_TDMTX_CTL(x)
/* x : index for registers; n : index for slot; 8 slots per register */
#define CS53L30_ASP_TDMTX_ENx(x)
#define CS53L30_ASP_TDMTX_ENn(n)
#define CS53L30_ASP_TDMTX_ENx_MAX

/* Device ID */
#define CS53L30_DEVID

/* PDN_DONE Poll Maximum
 * If soft ramp is set it will take much longer to power down
 * the system.
 */
#define CS53L30_PDN_POLL_MAX

/* Bitfield Definitions */

/* R6 (0x06) CS53L30_PWRCTL - Power Control */
#define CS53L30_PDN_ULP_SHIFT
#define CS53L30_PDN_ULP_MASK
#define CS53L30_PDN_ULP
#define CS53L30_PDN_LP_SHIFT
#define CS53L30_PDN_LP_MASK
#define CS53L30_PDN_LP
#define CS53L30_DISCHARGE_FILT_SHIFT
#define CS53L30_DISCHARGE_FILT_MASK
#define CS53L30_DISCHARGE_FILT
#define CS53L30_THMS_PDN_SHIFT
#define CS53L30_THMS_PDN_MASK
#define CS53L30_THMS_PDN

#define CS53L30_PWRCTL_DEFAULT

/* R7 (0x07) CS53L30_MCLKCTL - MCLK Control */
#define CS53L30_MCLK_DIS_SHIFT
#define CS53L30_MCLK_DIS_MASK
#define CS53L30_MCLK_DIS
#define CS53L30_MCLK_INT_SCALE_SHIFT
#define CS53L30_MCLK_INT_SCALE_MASK
#define CS53L30_MCLK_INT_SCALE
#define CS53L30_DMIC_DRIVE_SHIFT
#define CS53L30_DMIC_DRIVE_MASK
#define CS53L30_DMIC_DRIVE
#define CS53L30_MCLK_DIV_SHIFT
#define CS53L30_MCLK_DIV_WIDTH
#define CS53L30_MCLK_DIV_MASK
#define CS53L30_MCLK_DIV_BY_1
#define CS53L30_MCLK_DIV_BY_2
#define CS53L30_MCLK_DIV_BY_3
#define CS53L30_SYNC_EN_SHIFT
#define CS53L30_SYNC_EN_MASK
#define CS53L30_SYNC_EN

#define CS53L30_MCLKCTL_DEFAULT

/* R8 (0x08) CS53L30_INT_SR_CTL - Internal Sample Rate Control */
#define CS53L30_INTRNL_FS_RATIO_SHIFT
#define CS53L30_INTRNL_FS_RATIO_MASK
#define CS53L30_INTRNL_FS_RATIO
#define CS53L30_MCLK_19MHZ_EN_SHIFT
#define CS53L30_MCLK_19MHZ_EN_MASK
#define CS53L30_MCLK_19MHZ_EN

/* 0x6 << 1 is reserved bits */
#define CS53L30_INT_SR_CTL_DEFAULT

/* R10 (0x0A) CS53L30_MICBIAS_CTL - Mic Bias Control */
#define CS53L30_MIC4_BIAS_PDN_SHIFT
#define CS53L30_MIC4_BIAS_PDN_MASK
#define CS53L30_MIC4_BIAS_PDN
#define CS53L30_MIC3_BIAS_PDN_SHIFT
#define CS53L30_MIC3_BIAS_PDN_MASK
#define CS53L30_MIC3_BIAS_PDN
#define CS53L30_MIC2_BIAS_PDN_SHIFT
#define CS53L30_MIC2_BIAS_PDN_MASK
#define CS53L30_MIC2_BIAS_PDN
#define CS53L30_MIC1_BIAS_PDN_SHIFT
#define CS53L30_MIC1_BIAS_PDN_MASK
#define CS53L30_MIC1_BIAS_PDN
#define CS53L30_MICx_BIAS_PDN
#define CS53L30_VP_MIN_SHIFT
#define CS53L30_VP_MIN_MASK
#define CS53L30_VP_MIN
#define CS53L30_MIC_BIAS_CTRL_SHIFT
#define CS53L30_MIC_BIAS_CTRL_WIDTH
#define CS53L30_MIC_BIAS_CTRL_MASK
#define CS53L30_MIC_BIAS_CTRL_HIZ
#define CS53L30_MIC_BIAS_CTRL_1V8
#define CS53L30_MIC_BIAS_CTRL_2V75

#define CS53L30_MICBIAS_CTL_DEFAULT

/* R12 (0x0C) CS53L30_ASPCFG_CTL - ASP Configuration Control */
#define CS53L30_ASP_MS_SHIFT
#define CS53L30_ASP_MS_MASK
#define CS53L30_ASP_MS
#define CS53L30_ASP_SCLK_INV_SHIFT
#define CS53L30_ASP_SCLK_INV_MASK
#define CS53L30_ASP_SCLK_INV
#define CS53L30_ASP_RATE_SHIFT
#define CS53L30_ASP_RATE_WIDTH
#define CS53L30_ASP_RATE_MASK
#define CS53L30_ASP_RATE_48K

#define CS53L30_ASPCFG_CTL_DEFAULT

/* R13/R24 (0x0D/0x18) CS53L30_ASP_CTL1 & CS53L30_ASP_CTL2 - ASP Control 1~2 */
#define CS53L30_ASP_TDM_PDN_SHIFT
#define CS53L30_ASP_TDM_PDN_MASK
#define CS53L30_ASP_TDM_PDN
#define CS53L30_ASP_SDOUTx_PDN_SHIFT
#define CS53L30_ASP_SDOUTx_PDN_MASK
#define CS53L30_ASP_SDOUTx_PDN
#define CS53L30_ASP_3ST_SHIFT
#define CS53L30_ASP_3ST_MASK
#define CS53L30_ASP_3ST
#define CS53L30_SHIFT_LEFT_SHIFT
#define CS53L30_SHIFT_LEFT_MASK
#define CS53L30_SHIFT_LEFT
#define CS53L30_ASP_SDOUTx_DRIVE_SHIFT
#define CS53L30_ASP_SDOUTx_DRIVE_MASK
#define CS53L30_ASP_SDOUTx_DRIVE

#define CS53L30_ASP_CTL1_DEFAULT
#define CS53L30_ASP_CTL2_DEFAULT

/* R14 (0x0E) ~ R17 (0x11) CS53L30_ASP_TDMTX_CTLx - ASP TDM TX Control 1~4 */
#define CS53L30_ASP_CHx_TX_STATE_SHIFT
#define CS53L30_ASP_CHx_TX_STATE_MASK
#define CS53L30_ASP_CHx_TX_STATE
#define CS53L30_ASP_CHx_TX_LOC_SHIFT
#define CS53L30_ASP_CHx_TX_LOC_WIDTH
#define CS53L30_ASP_CHx_TX_LOC_MASK
#define CS53L30_ASP_CHx_TX_LOC_MAX
#define CS53L30_ASP_CHx_TX_LOC(x)

#define CS53L30_ASP_TDMTX_CTLx_DEFAULT

/* R18 (0x12) ~ R23 (0x17) CS53L30_ASP_TDMTX_ENx - ASP TDM TX Enable 1~6 */
#define CS53L30_ASP_TDMTX_ENx_DEFAULT

/* R26 (0x1A) CS53L30_SFT_RAMP - Soft Ramp Control */
#define CS53L30_DIGSFT_SHIFT
#define CS53L30_DIGSFT_MASK
#define CS53L30_DIGSFT

#define CS53L30_SFT_RMP_DEFAULT

/* R28 (0x1C) CS53L30_LRCK_CTL2 - LRCK Control 2 */
#define CS53L30_LRCK_50_NPW_SHIFT
#define CS53L30_LRCK_50_NPW_MASK
#define CS53L30_LRCK_50_NPW
#define CS53L30_LRCK_TPWH_SHIFT
#define CS53L30_LRCK_TPWH_WIDTH
#define CS53L30_LRCK_TPWH_MASK
#define CS53L30_LRCK_TPWH(x)

#define CS53L30_LRCK_CTLx_DEFAULT

/* R31 (0x1F) CS53L30_MUTEP_CTL1 - MUTE Pin Control 1 */
#define CS53L30_MUTE_PDN_ULP_SHIFT
#define CS53L30_MUTE_PDN_ULP_MASK
#define CS53L30_MUTE_PDN_ULP
#define CS53L30_MUTE_PDN_LP_SHIFT
#define CS53L30_MUTE_PDN_LP_MASK
#define CS53L30_MUTE_PDN_LP
#define CS53L30_MUTE_M4B_PDN_SHIFT
#define CS53L30_MUTE_M4B_PDN_MASK
#define CS53L30_MUTE_M4B_PDN
#define CS53L30_MUTE_M3B_PDN_SHIFT
#define CS53L30_MUTE_M3B_PDN_MASK
#define CS53L30_MUTE_M3B_PDN
#define CS53L30_MUTE_M2B_PDN_SHIFT
#define CS53L30_MUTE_M2B_PDN_MASK
#define CS53L30_MUTE_M2B_PDN
#define CS53L30_MUTE_M1B_PDN_SHIFT
#define CS53L30_MUTE_M1B_PDN_MASK
#define CS53L30_MUTE_M1B_PDN
/* Note: be careful - x starts from 0 */
#define CS53L30_MUTE_MxB_PDN_SHIFT(x)
#define CS53L30_MUTE_MxB_PDN_MASK(x)
#define CS53L30_MUTE_MxB_PDN(x)
#define CS53L30_MUTE_MB_ALL_PDN_SHIFT
#define CS53L30_MUTE_MB_ALL_PDN_MASK
#define CS53L30_MUTE_MB_ALL_PDN

#define CS53L30_MUTEP_CTL1_MUTEALL
#define CS53L30_MUTEP_CTL1_DEFAULT

/* R32 (0x20) CS53L30_MUTEP_CTL2 - MUTE Pin Control 2 */
#define CS53L30_MUTE_PIN_POLARITY_SHIFT
#define CS53L30_MUTE_PIN_POLARITY_MASK
#define CS53L30_MUTE_PIN_POLARITY
#define CS53L30_MUTE_ASP_TDM_PDN_SHIFT
#define CS53L30_MUTE_ASP_TDM_PDN_MASK
#define CS53L30_MUTE_ASP_TDM_PDN
#define CS53L30_MUTE_ASP_SDOUT2_PDN_SHIFT
#define CS53L30_MUTE_ASP_SDOUT2_PDN_MASK
#define CS53L30_MUTE_ASP_SDOUT2_PDN
#define CS53L30_MUTE_ASP_SDOUT1_PDN_SHIFT
#define CS53L30_MUTE_ASP_SDOUT1_PDN_MASK
#define CS53L30_MUTE_ASP_SDOUT1_PDN
/* Note: be careful - x starts from 0 */
#define CS53L30_MUTE_ASP_SDOUTx_PDN_SHIFT(x)
#define CS53L30_MUTE_ASP_SDOUTx_PDN_MASK(x)
#define CS53L30_MUTE_ASP_SDOUTx_PDN
#define CS53L30_MUTE_ADC2B_PDN_SHIFT
#define CS53L30_MUTE_ADC2B_PDN_MASK
#define CS53L30_MUTE_ADC2B_PDN
#define CS53L30_MUTE_ADC2A_PDN_SHIFT
#define CS53L30_MUTE_ADC2A_PDN_MASK
#define CS53L30_MUTE_ADC2A_PDN
#define CS53L30_MUTE_ADC1B_PDN_SHIFT
#define CS53L30_MUTE_ADC1B_PDN_MASK
#define CS53L30_MUTE_ADC1B_PDN
#define CS53L30_MUTE_ADC1A_PDN_SHIFT
#define CS53L30_MUTE_ADC1A_PDN_MASK
#define CS53L30_MUTE_ADC1A_PDN

#define CS53L30_MUTEP_CTL2_DEFAULT

/* R33 (0x21) CS53L30_INBIAS_CTL1 - Input Bias Control 1 */
#define CS53L30_IN4M_BIAS_SHIFT
#define CS53L30_IN4M_BIAS_WIDTH
#define CS53L30_IN4M_BIAS_MASK
#define CS53L30_IN4M_BIAS_OPEN
#define CS53L30_IN4M_BIAS_PULL_DOWN
#define CS53L30_IN4M_BIAS_VCM
#define CS53L30_IN4P_BIAS_SHIFT
#define CS53L30_IN4P_BIAS_WIDTH
#define CS53L30_IN4P_BIAS_MASK
#define CS53L30_IN4P_BIAS_OPEN
#define CS53L30_IN4P_BIAS_PULL_DOWN
#define CS53L30_IN4P_BIAS_VCM
#define CS53L30_IN3M_BIAS_SHIFT
#define CS53L30_IN3M_BIAS_WIDTH
#define CS53L30_IN3M_BIAS_MASK
#define CS53L30_IN3M_BIAS_OPEN
#define CS53L30_IN3M_BIAS_PULL_DOWN
#define CS53L30_IN3M_BIAS_VCM
#define CS53L30_IN3P_BIAS_SHIFT
#define CS53L30_IN3P_BIAS_WIDTH
#define CS53L30_IN3P_BIAS_MASK
#define CS53L30_IN3P_BIAS_OPEN
#define CS53L30_IN3P_BIAS_PULL_DOWN
#define CS53L30_IN3P_BIAS_VCM

#define CS53L30_INBIAS_CTL1_DEFAULT

/* R34 (0x22) CS53L30_INBIAS_CTL2 - Input Bias Control 2 */
#define CS53L30_IN2M_BIAS_SHIFT
#define CS53L30_IN2M_BIAS_WIDTH
#define CS53L30_IN2M_BIAS_MASK
#define CS53L30_IN2M_BIAS_OPEN
#define CS53L30_IN2M_BIAS_PULL_DOWN
#define CS53L30_IN2M_BIAS_VCM
#define CS53L30_IN2P_BIAS_SHIFT
#define CS53L30_IN2P_BIAS_WIDTH
#define CS53L30_IN2P_BIAS_MASK
#define CS53L30_IN2P_BIAS_OPEN
#define CS53L30_IN2P_BIAS_PULL_DOWN
#define CS53L30_IN2P_BIAS_VCM
#define CS53L30_IN1M_BIAS_SHIFT
#define CS53L30_IN1M_BIAS_WIDTH
#define CS53L30_IN1M_BIAS_MASK
#define CS53L30_IN1M_BIAS_OPEN
#define CS53L30_IN1M_BIAS_PULL_DOWN
#define CS53L30_IN1M_BIAS_VCM
#define CS53L30_IN1P_BIAS_SHIFT
#define CS53L30_IN1P_BIAS_WIDTH
#define CS53L30_IN1P_BIAS_MASK
#define CS53L30_IN1P_BIAS_OPEN
#define CS53L30_IN1P_BIAS_PULL_DOWN
#define CS53L30_IN1P_BIAS_VCM

#define CS53L30_INBIAS_CTL2_DEFAULT

/* R35 (0x23) & R36 (0x24) CS53L30_DMICx_STR_CTL - DMIC1 & DMIC2 Stereo Control */
#define CS53L30_DMICx_STEREO_ENB_SHIFT
#define CS53L30_DMICx_STEREO_ENB_MASK
#define CS53L30_DMICx_STEREO_ENB

/* 0x88 and 0xCC are reserved bits */
#define CS53L30_DMIC1_STR_CTL_DEFAULT
#define CS53L30_DMIC2_STR_CTL_DEFAULT

/* R37/R45 (0x25/0x2D) CS53L30_ADCDMICx_CTL1 - ADC1/DMIC1 & ADC2/DMIC2 Control 1 */
#define CS53L30_ADCxB_PDN_SHIFT
#define CS53L30_ADCxB_PDN_MASK
#define CS53L30_ADCxB_PDN
#define CS53L30_ADCxA_PDN_SHIFT
#define CS53L30_ADCxA_PDN_MASK
#define CS53L30_ADCxA_PDN
#define CS53L30_DMICx_PDN_SHIFT
#define CS53L30_DMICx_PDN_MASK
#define CS53L30_DMICx_PDN
#define CS53L30_DMICx_SCLK_DIV_SHIFT
#define CS53L30_DMICx_SCLK_DIV_MASK
#define CS53L30_DMICx_SCLK_DIV
#define CS53L30_CH_TYPE_SHIFT
#define CS53L30_CH_TYPE_MASK
#define CS53L30_CH_TYPE

#define CS53L30_ADCDMICx_PDN_MASK
#define CS53L30_ADCDMICx_CTL1_DEFAULT

/* R38/R46 (0x26/0x2E) CS53L30_ADCDMICx_CTL2 - ADC1/DMIC1 & ADC2/DMIC2 Control 2 */
#define CS53L30_ADCx_NOTCH_DIS_SHIFT
#define CS53L30_ADCx_NOTCH_DIS_MASK
#define CS53L30_ADCx_NOTCH_DIS
#define CS53L30_ADCxB_INV_SHIFT
#define CS53L30_ADCxB_INV_MASK
#define CS53L30_ADCxB_INV
#define CS53L30_ADCxA_INV_SHIFT
#define CS53L30_ADCxA_INV_MASK
#define CS53L30_ADCxA_INV
#define CS53L30_ADCxB_DIG_BOOST_SHIFT
#define CS53L30_ADCxB_DIG_BOOST_MASK
#define CS53L30_ADCxB_DIG_BOOST
#define CS53L30_ADCxA_DIG_BOOST_SHIFT
#define CS53L30_ADCxA_DIG_BOOST_MASK
#define CS53L30_ADCxA_DIG_BOOST

#define CS53L30_ADCDMIC1_CTL2_DEFAULT

/* R39/R47 (0x27/0x2F) CS53L30_ADCx_CTL3 - ADC1/ADC2 Control 3 */
#define CS53L30_ADCx_HPF_EN_SHIFT
#define CS53L30_ADCx_HPF_EN_MASK
#define CS53L30_ADCx_HPF_EN
#define CS53L30_ADCx_HPF_CF_SHIFT
#define CS53L30_ADCx_HPF_CF_WIDTH
#define CS53L30_ADCx_HPF_CF_MASK
#define CS53L30_ADCx_HPF_CF_1HZ86
#define CS53L30_ADCx_HPF_CF_120HZ
#define CS53L30_ADCx_HPF_CF_235HZ
#define CS53L30_ADCx_HPF_CF_466HZ
#define CS53L30_ADCx_NG_ALL_SHIFT
#define CS53L30_ADCx_NG_ALL_MASK
#define CS53L30_ADCx_NG_ALL

#define CS53L30_ADCx_CTL3_DEFAULT

/* R40/R48 (0x28/0x30) CS53L30_ADCx_NG_CTL - ADC1/ADC2 Noise Gate Control */
#define CS53L30_ADCxB_NG_SHIFT
#define CS53L30_ADCxB_NG_MASK
#define CS53L30_ADCxB_NG
#define CS53L30_ADCxA_NG_SHIFT
#define CS53L30_ADCxA_NG_MASK
#define CS53L30_ADCxA_NG
#define CS53L30_ADCx_NG_BOOST_SHIFT
#define CS53L30_ADCx_NG_BOOST_MASK
#define CS53L30_ADCx_NG_BOOST
#define CS53L30_ADCx_NG_THRESH_SHIFT
#define CS53L30_ADCx_NG_THRESH_WIDTH
#define CS53L30_ADCx_NG_THRESH_MASK
#define CS53L30_ADCx_NG_DELAY_SHIFT
#define CS53L30_ADCx_NG_DELAY_WIDTH
#define CS53L30_ADCx_NG_DELAY_MASK

#define CS53L30_ADCx_NG_CTL_DEFAULT

/* R41/R42/R49/R50 (0x29/0x2A/0x31/0x32) CS53L30_ADCxy_AFE_CTL - ADC1A/1B/2A/2B AFE Control */
#define CS53L30_ADCxy_PREAMP_SHIFT
#define CS53L30_ADCxy_PREAMP_WIDTH
#define CS53L30_ADCxy_PREAMP_MASK
#define CS53L30_ADCxy_PGA_VOL_SHIFT
#define CS53L30_ADCxy_PGA_VOL_WIDTH
#define CS53L30_ADCxy_PGA_VOL_MASK

#define CS53L30_ADCxy_AFE_CTL_DEFAULT

/* R43/R44/R51/R52 (0x2B/0x2C/0x33/0x34) CS53L30_ADCxy_DIG_VOL - ADC1A/1B/2A/2B Digital Volume */
#define CS53L30_ADCxy_VOL_MUTE

#define CS53L30_ADCxy_DIG_VOL_DEFAULT

/* CS53L30_INT */
#define CS53L30_PDN_DONE
#define CS53L30_THMS_TRIP
#define CS53L30_SYNC_DONE
#define CS53L30_ADC2B_OVFL
#define CS53L30_ADC2A_OVFL
#define CS53L30_ADC1B_OVFL
#define CS53L30_ADC1A_OVFL
#define CS53L30_MUTE_PIN
#define CS53L30_DEVICE_INT_MASK

#endif	/* __CS53L30_H__ */