// SPDX-License-Identifier: GPL-2.0 // // JZ4725B CODEC driver // // Copyright (C) 2019, Paul Cercueil <[email protected]> #include <linux/kernel.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/regmap.h> #include <linux/clk.h> #include <linux/delay.h> #include <sound/core.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include <sound/initval.h> #include <sound/soc.h> #include <sound/tlv.h> #define ICDC_RGADW_OFFSET … #define ICDC_RGDATA_OFFSET … /* ICDC internal register access control register(RGADW) */ #define ICDC_RGADW_RGWR … #define ICDC_RGADW_RGADDR_OFFSET … #define ICDC_RGADW_RGADDR_MASK … #define ICDC_RGADW_RGDIN_OFFSET … #define ICDC_RGADW_RGDIN_MASK … /* ICDC internal register data output register (RGDATA)*/ #define ICDC_RGDATA_IRQ … #define ICDC_RGDATA_RGDOUT_OFFSET … #define ICDC_RGDATA_RGDOUT_MASK … /* JZ internal register space */ enum { … }; #define REG_AICR_CONFIG1_OFFSET … #define REG_AICR_CONFIG1_MASK … #define REG_CR1_SB_MICBIAS_OFFSET … #define REG_CR1_MONO_OFFSET … #define REG_CR1_DAC_MUTE_OFFSET … #define REG_CR1_HP_DIS_OFFSET … #define REG_CR1_DACSEL_OFFSET … #define REG_CR1_BYPASS_OFFSET … #define REG_CR2_DAC_DEEMP_OFFSET … #define REG_CR2_DAC_ADWL_OFFSET … #define REG_CR2_DAC_ADWL_MASK … #define REG_CR2_ADC_ADWL_OFFSET … #define REG_CR2_ADC_ADWL_MASK … #define REG_CR2_ADC_HPF_OFFSET … #define REG_CR3_SB_MIC1_OFFSET … #define REG_CR3_SB_MIC2_OFFSET … #define REG_CR3_SIDETONE1_OFFSET … #define REG_CR3_SIDETONE2_OFFSET … #define REG_CR3_MICDIFF_OFFSET … #define REG_CR3_MICSTEREO_OFFSET … #define REG_CR3_INSEL_OFFSET … #define REG_CR3_INSEL_MASK … #define REG_CCR1_CONFIG4_OFFSET … #define REG_CCR1_CONFIG4_MASK … #define REG_CCR2_DFREQ_OFFSET … #define REG_CCR2_DFREQ_MASK … #define REG_CCR2_AFREQ_OFFSET … #define REG_CCR2_AFREQ_MASK … #define REG_PMR1_SB_DAC_OFFSET … #define REG_PMR1_SB_OUT_OFFSET … #define REG_PMR1_SB_MIX_OFFSET … #define REG_PMR1_SB_ADC_OFFSET … #define REG_PMR1_SB_LIN_OFFSET … #define REG_PMR1_SB_IND_OFFSET … #define REG_PMR2_LRGI_OFFSET … #define REG_PMR2_RLGI_OFFSET … #define REG_PMR2_LRGOD_OFFSET … #define REG_PMR2_RLGOD_OFFSET … #define REG_PMR2_GIM_OFFSET … #define REG_PMR2_SB_MC_OFFSET … #define REG_PMR2_SB_OFFSET … #define REG_PMR2_SB_SLEEP_OFFSET … #define REG_IFR_RAMP_UP_DONE_OFFSET … #define REG_IFR_RAMP_DOWN_DONE_OFFSET … #define REG_CGR1_GODL_OFFSET … #define REG_CGR1_GODL_MASK … #define REG_CGR1_GODR_OFFSET … #define REG_CGR1_GODR_MASK … #define REG_CGR2_GO1R_OFFSET … #define REG_CGR2_GO1R_MASK … #define REG_CGR3_GO1L_OFFSET … #define REG_CGR3_GO1L_MASK … #define REG_CGR4_GO2R_OFFSET … #define REG_CGR4_GO2R_MASK … #define REG_CGR5_GO2L_OFFSET … #define REG_CGR5_GO2L_MASK … #define REG_CGR6_GO3R_OFFSET … #define REG_CGR6_GO3R_MASK … #define REG_CGR7_GO3L_OFFSET … #define REG_CGR7_GO3L_MASK … #define REG_CGR8_GOR_OFFSET … #define REG_CGR8_GOR_MASK … #define REG_CGR9_GOL_OFFSET … #define REG_CGR9_GOL_MASK … #define REG_CGR10_GIL_OFFSET … #define REG_CGR10_GIR_OFFSET … struct jz_icdc { … }; static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(jz4725b_adc_tlv, 0, 150, 0); static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(jz4725b_dac_tlv, -2250, 150, 0); static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(jz4725b_mix_tlv, 0, 11, TLV_DB_SCALE_ITEM(-2250, 0, 0), 12, 31, TLV_DB_SCALE_ITEM(-2250, 150, 0), ); static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(jz4725b_out_tlv, 0, 11, TLV_DB_SCALE_ITEM(-3350, 200, 0), 12, 23, TLV_DB_SCALE_ITEM(-1050, 100, 0), 24, 31, TLV_DB_SCALE_ITEM( 100, 50, 0), ); static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(jz4725b_mic_boost_tlv, 0, 2000, 0); static const char * const jz4725b_mic_mode_texts[] = …; static const struct soc_enum jz4725b_mic_mode_enum = …; static const struct snd_kcontrol_new jz4725b_codec_controls[] = …; static const char * const jz4725b_codec_adc_src_texts[] = …; static const unsigned int jz4725b_codec_adc_src_values[] = …; static SOC_VALUE_ENUM_SINGLE_DECL(jz4725b_codec_adc_src_enum, JZ4725B_CODEC_REG_CR3, REG_CR3_INSEL_OFFSET, REG_CR3_INSEL_MASK, jz4725b_codec_adc_src_texts, jz4725b_codec_adc_src_values); static const struct snd_kcontrol_new jz4725b_codec_adc_src_ctrl = …; static const struct snd_kcontrol_new jz4725b_codec_mixer_controls[] = …; static int jz4725b_out_stage_enable(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static const struct snd_soc_dapm_widget jz4725b_codec_dapm_widgets[] = …; static const struct snd_soc_dapm_route jz4725b_codec_dapm_routes[] = …; static int jz4725b_codec_set_bias_level(struct snd_soc_component *component, enum snd_soc_bias_level level) { … } static int jz4725b_codec_dev_probe(struct snd_soc_component *component) { … } static void jz4725b_codec_dev_remove(struct snd_soc_component *component) { … } static const struct snd_soc_component_driver jz4725b_codec = …; static const unsigned int jz4725b_codec_sample_rates[] = …; static int jz4725b_codec_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { … } static const struct snd_soc_dai_ops jz4725b_codec_dai_ops = …; #define JZ_ICDC_FORMATS … static struct snd_soc_dai_driver jz4725b_codec_dai = …; static bool jz4725b_codec_volatile(struct device *dev, unsigned int reg) { … } static bool jz4725b_codec_can_access_reg(struct device *dev, unsigned int reg) { … } static int jz4725b_codec_io_wait(struct jz_icdc *icdc) { … } static int jz4725b_codec_reg_read(void *context, unsigned int reg, unsigned int *val) { … } static int jz4725b_codec_reg_write(void *context, unsigned int reg, unsigned int val) { … } static const u8 jz4725b_codec_reg_defaults[] = …; static const struct regmap_config jz4725b_codec_regmap_config = …; static int jz4725b_codec_probe(struct platform_device *pdev) { … } static const struct of_device_id jz4725b_codec_of_matches[] = …; MODULE_DEVICE_TABLE(of, jz4725b_codec_of_matches); static struct platform_driver jz4725b_codec_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
Codebase Browser
linux