// SPDX-License-Identifier: GPL-2.0 // // Ingenic JZ4760 CODEC driver // // Copyright (C) 2021, Christophe Branchereau <[email protected]> // Copyright (C) 2021, Paul Cercueil <[email protected]> #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/iopoll.h> #include <linux/module.h> #include <linux/regmap.h> #include <linux/time64.h> #include <sound/pcm_params.h> #include <sound/soc.h> #include <sound/soc-dai.h> #include <sound/soc-dapm.h> #include <sound/tlv.h> #define ICDC_RGADW_OFFSET … #define ICDC_RGDATA_OFFSET … /* ICDC internal register access control register(RGADW) */ #define ICDC_RGADW_RGWR … #define ICDC_RGADW_RGADDR_MASK … #define ICDC_RGADW_RGDIN_MASK … /* ICDC internal register data output register (RGDATA)*/ #define ICDC_RGDATA_IRQ … #define ICDC_RGDATA_RGDOUT_MASK … /* Internal register space, accessed through regmap */ enum { … }; #define REG_AICR_DAC_ADWL_MASK … #define REG_AICR_DAC_SERIAL … #define REG_AICR_DAC_I2S … #define REG_AICR_ADC_ADWL_MASK … #define REG_AICR_ADC_SERIAL … #define REG_AICR_ADC_I2S … #define REG_CR1_HP_LOAD … #define REG_CR1_HP_MUTE … #define REG_CR1_LO_MUTE_OFFSET … #define REG_CR1_BTL_MUTE_OFFSET … #define REG_CR1_OUTSEL_OFFSET … #define REG_CR1_OUTSEL_MASK … #define REG_CR2_DAC_MONO … #define REG_CR2_DAC_MUTE … #define REG_CR2_DAC_NOMAD … #define REG_CR2_DAC_RIGHT_ONLY … #define REG_CR3_ADC_INSEL_OFFSET … #define REG_CR3_ADC_INSEL_MASK … #define REG_CR3_MICSTEREO_OFFSET … #define REG_CR3_MICDIFF_OFFSET … #define REG_CR4_ADC_HPF_OFFSET … #define REG_CR4_ADC_RIGHT_ONLY … #define REG_CCR1_CRYSTAL_MASK … #define REG_CCR2_DAC_FREQ_MASK … #define REG_CCR2_ADC_FREQ_MASK … #define REG_PMR1_SB … #define REG_PMR1_SB_SLEEP … #define REG_PMR1_SB_AIP_OFFSET … #define REG_PMR1_SB_LINE_OFFSET … #define REG_PMR1_SB_MIC1_OFFSET … #define REG_PMR1_SB_MIC2_OFFSET … #define REG_PMR1_SB_BYPASS_OFFSET … #define REG_PMR1_SB_MICBIAS_OFFSET … #define REG_PMR2_SB_ADC_OFFSET … #define REG_PMR2_SB_HP_OFFSET … #define REG_PMR2_SB_BTL_OFFSET … #define REG_PMR2_SB_LOUT_OFFSET … #define REG_PMR2_SB_DAC_OFFSET … #define REG_ICR_INT_FORM_MASK … #define REG_ICR_ALL_MASK … #define REG_ICR_JACK_MASK … #define REG_ICR_SCMC_MASK … #define REG_ICR_RUP_MASK … #define REG_ICR_RDO_MASK … #define REG_ICR_GUP_MASK … #define REG_ICR_GDO_MASK … #define REG_IFR_ALL_MASK … #define REG_IFR_JACK … #define REG_IFR_JACK_EVENT … #define REG_IFR_SCMC … #define REG_IFR_RUP … #define REG_IFR_RDO … #define REG_IFR_GUP … #define REG_IFR_GDO … #define REG_GCR_GAIN_OFFSET … #define REG_GCR_GAIN_MAX … #define REG_GCR_RL … #define REG_GCR_GIM1_MASK … #define REG_GCR_GIM2_MASK … #define REG_GCR_GIM_GAIN_MAX … #define REG_AGC1_EN … #define REG_AGC1_TARGET_MASK … #define REG_AGC2_NG_THR_MASK … #define REG_AGC2_HOLD_MASK … #define REG_AGC3_ATK_MASK … #define REG_AGC3_DCY_MASK … #define REG_AGC4_AGC_MAX_MASK … #define REG_AGC5_AGC_MIN_MASK … #define REG_MIX1_MIX_REC_MASK … #define REG_MIX1_GIMIX_MASK … #define REG_MIX2_DAC_MIX_MASK … #define REG_MIX2_GOMIX_MASK … /* codec private data */ struct jz_codec { … }; static int jz4760_codec_set_bias_level(struct snd_soc_component *codec, enum snd_soc_bias_level level) { … } static int jz4760_codec_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { … } static void jz4760_codec_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { … } static int jz4760_codec_pcm_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) { … } static int jz4760_codec_mute_stream(struct snd_soc_dai *dai, int mute, int direction) { … } /* unit: 0.01dB */ static const DECLARE_TLV_DB_MINMAX_MUTE(dac_tlv, -3100, 100); static const DECLARE_TLV_DB_SCALE(adc_tlv, 0, 100, 0); static const DECLARE_TLV_DB_MINMAX(out_tlv, -2500, 100); static const DECLARE_TLV_DB_SCALE(linein_tlv, -2500, 100, 0); static const DECLARE_TLV_DB_MINMAX(mixer_tlv, -3100, 0); /* Unconditional controls. */ static const struct snd_kcontrol_new jz4760_codec_snd_controls[] = …; static const struct snd_kcontrol_new jz4760_codec_pcm_playback_controls[] = …; static const struct snd_kcontrol_new jz4760_codec_hp_playback_controls[] = …; static int hpout_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static const char * const jz4760_codec_hp_texts[] = …; static const unsigned int jz4760_codec_hp_values[] = …; static SOC_VALUE_ENUM_SINGLE_DECL(jz4760_codec_hp_enum, JZ4760_CODEC_REG_CR1, REG_CR1_OUTSEL_OFFSET, REG_CR1_OUTSEL_MASK >> REG_CR1_OUTSEL_OFFSET, jz4760_codec_hp_texts, jz4760_codec_hp_values); static const struct snd_kcontrol_new jz4760_codec_hp_source = …; static const char * const jz4760_codec_cap_texts[] = …; static const unsigned int jz4760_codec_cap_values[] = …; static SOC_VALUE_ENUM_SINGLE_DECL(jz4760_codec_cap_enum, JZ4760_CODEC_REG_CR3, REG_CR3_ADC_INSEL_OFFSET, REG_CR3_ADC_INSEL_MASK >> REG_CR3_ADC_INSEL_OFFSET, jz4760_codec_cap_texts, jz4760_codec_cap_values); static const struct snd_kcontrol_new jz4760_codec_cap_source = …; static const struct snd_kcontrol_new jz4760_codec_mic_controls[] = …; static const struct snd_kcontrol_new jz4760_codec_line_out_switch = …; static const struct snd_kcontrol_new jz4760_codec_btl_out_switch = …; static const struct snd_soc_dapm_widget jz4760_codec_dapm_widgets[] = …; /* Unconditional routes. */ static const struct snd_soc_dapm_route jz4760_codec_dapm_routes[] = …; static void jz4760_codec_codec_init_regs(struct snd_soc_component *codec) { … } static int jz4760_codec_codec_probe(struct snd_soc_component *codec) { … } static void jz4760_codec_codec_remove(struct snd_soc_component *codec) { … } static const struct snd_soc_component_driver jz4760_codec_soc_codec_dev = …; static const unsigned int jz4760_codec_sample_rates[] = …; static int jz4760_codec_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { … } static const struct snd_soc_dai_ops jz4760_codec_dai_ops = …; #define JZ_CODEC_FORMATS … static struct snd_soc_dai_driver jz4760_codec_dai = …; static bool jz4760_codec_volatile(struct device *dev, unsigned int reg) { … } static bool jz4760_codec_writeable(struct device *dev, unsigned int reg) { … } static int jz4760_codec_io_wait(struct jz_codec *codec) { … } static int jz4760_codec_reg_read(void *context, unsigned int reg, unsigned int *val) { … } static int jz4760_codec_reg_write(void *context, unsigned int reg, unsigned int val) { … } static const u8 jz4760_codec_reg_defaults[] = …; static const struct regmap_config jz4760_codec_regmap_config = …; static int jz4760_codec_probe(struct platform_device *pdev) { … } static const struct of_device_id jz4760_codec_of_matches[] = …; MODULE_DEVICE_TABLE(of, jz4760_codec_of_matches); static struct platform_driver jz4760_codec_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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