// SPDX-License-Identifier: GPL-2.0 // // Ingenic JZ4770 CODEC driver // // Copyright (C) 2012, Maarten ter Huurne <[email protected]> // Copyright (C) 2019, Paul Cercueil <[email protected]> #include <linux/clk.h> #include <linux/delay.h> #include <linux/iopoll.h> #include <linux/module.h> #include <linux/regmap.h> #include <linux/time64.h> #include <sound/pcm_params.h> #include <sound/soc.h> #include <sound/soc-dai.h> #include <sound/soc-dapm.h> #include <sound/tlv.h> #define ICDC_RGADW_OFFSET … #define ICDC_RGDATA_OFFSET … /* ICDC internal register access control register(RGADW) */ #define ICDC_RGADW_RGWR … #define ICDC_RGADW_RGADDR_OFFSET … #define ICDC_RGADW_RGADDR_MASK … #define ICDC_RGADW_RGDIN_OFFSET … #define ICDC_RGADW_RGDIN_MASK … /* ICDC internal register data output register (RGDATA)*/ #define ICDC_RGDATA_IRQ … #define ICDC_RGDATA_RGDOUT_OFFSET … #define ICDC_RGDATA_RGDOUT_MASK … /* Internal register space, accessed through regmap */ enum { … }; #define REG_AICR_DAC_ADWL_OFFSET … #define REG_AICR_DAC_ADWL_MASK … #define REG_AICR_DAC_SERIAL … #define REG_AICR_DAC_I2S … #define REG_AICR_ADC_ADWL_OFFSET … #define REG_AICR_ADC_ADWL_MASK … #define REG_AICR_ADC_SERIAL … #define REG_AICR_ADC_I2S … #define REG_CR_LO_MUTE_OFFSET … #define REG_CR_LO_SB_OFFSET … #define REG_CR_LO_SEL_OFFSET … #define REG_CR_LO_SEL_MASK … #define REG_CR_HP_MUTE … #define REG_CR_HP_LOAD … #define REG_CR_HP_SB_OFFSET … #define REG_CR_HP_SB_HPCM_OFFSET … #define REG_CR_HP_SEL_OFFSET … #define REG_CR_HP_SEL_MASK … #define REG_CR_DAC_MUTE … #define REG_CR_DAC_MONO … #define REG_CR_DAC_LEFT_ONLY … #define REG_CR_DAC_SB_OFFSET … #define REG_CR_DAC_LRSWAP … #define REG_CR_MIC_STEREO_OFFSET … #define REG_CR_MIC_IDIFF_OFFSET … #define REG_CR_MIC_SB_MIC2_OFFSET … #define REG_CR_MIC_SB_MIC1_OFFSET … #define REG_CR_MIC_BIAS_V0_OFFSET … #define REG_CR_MIC_BIAS_SB_OFFSET … #define REG_CR_LI_LIBY_OFFSET … #define REG_CR_LI_SB_OFFSET … #define REG_CR_ADC_DMIC_SEL … #define REG_CR_ADC_MONO … #define REG_CR_ADC_LEFT_ONLY … #define REG_CR_ADC_SB_OFFSET … #define REG_CR_ADC_LRSWAP … #define REG_CR_ADC_IN_SEL_OFFSET … #define REG_CR_ADC_IN_SEL_MASK … #define REG_CR_VIC_SB_SLEEP … #define REG_CR_VIC_SB … #define REG_CCR_CRYSTAL_OFFSET … #define REG_CCR_CRYSTAL_MASK … #define REG_FCR_DAC_FREQ_OFFSET … #define REG_FCR_DAC_FREQ_MASK … #define REG_FCR_ADC_FREQ_OFFSET … #define REG_FCR_ADC_FREQ_MASK … #define REG_ICR_INT_FORM_OFFSET … #define REG_ICR_INT_FORM_MASK … #define REG_IMR_ALL_MASK … #define REG_IMR_SCLR_MASK … #define REG_IMR_JACK_MASK … #define REG_IMR_SCMC_MASK … #define REG_IMR_RUP_MASK … #define REG_IMR_RDO_MASK … #define REG_IMR_GUP_MASK … #define REG_IMR_GDO_MASK … #define REG_IFR_ALL_MASK … #define REG_IFR_SCLR … #define REG_IFR_JACK … #define REG_IFR_SCMC … #define REG_IFR_RUP … #define REG_IFR_RDO … #define REG_IFR_GUP … #define REG_IFR_GDO … #define REG_GCR_HPL_LRGO … #define REG_GCR_DACL_RLGOD … #define REG_GCR_GAIN_OFFSET … #define REG_GCR_GAIN_MAX … #define REG_GCR_MIC_GAIN_OFFSET … #define REG_GCR_MIC_GAIN_MAX … #define REG_GCR_ADC_GAIN_OFFSET … #define REG_GCR_ADC_GAIN_MAX … #define REG_AGC1_EN … /* codec private data */ struct jz_codec { … }; static int jz4770_codec_set_bias_level(struct snd_soc_component *codec, enum snd_soc_bias_level level) { … } static int jz4770_codec_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { … } static void jz4770_codec_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { … } static int jz4770_codec_pcm_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) { … } static int jz4770_codec_mute_stream(struct snd_soc_dai *dai, int mute, int direction) { … } /* unit: 0.01dB */ static const DECLARE_TLV_DB_MINMAX_MUTE(dac_tlv, -3100, 0); static const DECLARE_TLV_DB_SCALE(adc_tlv, 0, 100, 0); static const DECLARE_TLV_DB_MINMAX(out_tlv, -2500, 600); static const DECLARE_TLV_DB_SCALE(linein_tlv, -2500, 100, 0); static const DECLARE_TLV_DB_MINMAX(mixer_tlv, -3100, 0); /* Unconditional controls. */ static const struct snd_kcontrol_new jz4770_codec_snd_controls[] = …; static const struct snd_kcontrol_new jz4770_codec_pcm_playback_controls[] = …; static const struct snd_kcontrol_new jz4770_codec_hp_playback_controls[] = …; static int hpout_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static int adc_poweron_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static const char * const jz4770_codec_hp_texts[] = …; static const unsigned int jz4770_codec_hp_values[] = …; static SOC_VALUE_ENUM_SINGLE_DECL(jz4770_codec_hp_enum, JZ4770_CODEC_REG_CR_HP, REG_CR_HP_SEL_OFFSET, REG_CR_HP_SEL_MASK, jz4770_codec_hp_texts, jz4770_codec_hp_values); static const struct snd_kcontrol_new jz4770_codec_hp_source = …; static SOC_VALUE_ENUM_SINGLE_DECL(jz4770_codec_lo_enum, JZ4770_CODEC_REG_CR_LO, REG_CR_LO_SEL_OFFSET, REG_CR_LO_SEL_MASK, jz4770_codec_hp_texts, jz4770_codec_hp_values); static const struct snd_kcontrol_new jz4770_codec_lo_source = …; static const char * const jz4770_codec_cap_texts[] = …; static const unsigned int jz4770_codec_cap_values[] = …; static SOC_VALUE_ENUM_SINGLE_DECL(jz4770_codec_cap_enum, JZ4770_CODEC_REG_CR_ADC, REG_CR_ADC_IN_SEL_OFFSET, REG_CR_ADC_IN_SEL_MASK, jz4770_codec_cap_texts, jz4770_codec_cap_values); static const struct snd_kcontrol_new jz4770_codec_cap_source = …; static const struct snd_kcontrol_new jz4770_codec_mic_controls[] = …; static const struct snd_soc_dapm_widget jz4770_codec_dapm_widgets[] = …; /* Unconditional routes. */ static const struct snd_soc_dapm_route jz4770_codec_dapm_routes[] = …; static void jz4770_codec_codec_init_regs(struct snd_soc_component *codec) { … } static int jz4770_codec_codec_probe(struct snd_soc_component *codec) { … } static void jz4770_codec_codec_remove(struct snd_soc_component *codec) { … } static const struct snd_soc_component_driver jz4770_codec_soc_codec_dev = …; static const unsigned int jz4770_codec_sample_rates[] = …; static int jz4770_codec_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { … } static const struct snd_soc_dai_ops jz4770_codec_dai_ops = …; #define JZ_CODEC_FORMATS … static struct snd_soc_dai_driver jz4770_codec_dai = …; static bool jz4770_codec_volatile(struct device *dev, unsigned int reg) { … } static bool jz4770_codec_readable(struct device *dev, unsigned int reg) { … } static bool jz4770_codec_writeable(struct device *dev, unsigned int reg) { … } static int jz4770_codec_io_wait(struct jz_codec *codec) { … } static int jz4770_codec_reg_read(void *context, unsigned int reg, unsigned int *val) { … } static int jz4770_codec_reg_write(void *context, unsigned int reg, unsigned int val) { … } static const u8 jz4770_codec_reg_defaults[] = …; static const struct regmap_config jz4770_codec_regmap_config = …; static int jz4770_codec_probe(struct platform_device *pdev) { … } static const struct of_device_id jz4770_codec_of_matches[] = …; MODULE_DEVICE_TABLE(of, jz4770_codec_of_matches); static struct platform_driver jz4770_codec_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
Codebase Browser
linux