/* SPDX-License-Identifier: GPL-2.0-only */ /* * lm49453.h - LM49453 ALSA Soc Audio drive * * Copyright (c) 2012 Texas Instruments, Inc */ #ifndef _LM49453_H #define _LM49453_H #include <linux/bitops.h> /* LM49453_P0 register space for page0 */ #define LM49453_P0_PMC_SETUP_REG … #define LM49453_P0_PLL_CLK_SEL1_REG … #define LM49453_P0_PLL_CLK_SEL2_REG … #define LM49453_P0_PMC_CLK_DIV_REG … #define LM49453_P0_HSDET_CLK_DIV_REG … #define LM49453_P0_DMIC_CLK_DIV_REG … #define LM49453_P0_ADC_CLK_DIV_REG … #define LM49453_P0_DAC_OT_CLK_DIV_REG … #define LM49453_P0_PLL_HF_M_REG … #define LM49453_P0_PLL_LF_M_REG … #define LM49453_P0_PLL_NL_REG … #define LM49453_P0_PLL_N_MODL_REG … #define LM49453_P0_PLL_N_MODH_REG … #define LM49453_P0_PLL_P1_REG … #define LM49453_P0_PLL_P2_REG … #define LM49453_P0_FLL_REF_FREQL_REG … #define LM49453_P0_FLL_REF_FREQH_REG … #define LM49453_P0_VCO_TARGETLL_REG … #define LM49453_P0_VCO_TARGETLH_REG … #define LM49453_P0_VCO_TARGETHL_REG … #define LM49453_P0_VCO_TARGETHH_REG … #define LM49453_P0_PLL_CONFIG_REG … #define LM49453_P0_DAC_CLK_SEL_REG … #define LM49453_P0_DAC_HP_CLK_DIV_REG … /* Analog Mixer Input Stages */ #define LM49453_P0_MICL_REG … #define LM49453_P0_MICR_REG … #define LM49453_P0_EP_REG … #define LM49453_P0_DIS_PKVL_FB_REG … /* Analog Mixer Output Stages */ #define LM49453_P0_ANALOG_MIXER_ADC_REG … /*ADC or DAC */ #define LM49453_P0_ADC_DSP_REG … #define LM49453_P0_DAC_DSP_REG … /* EFFECTS ENABLES */ #define LM49453_P0_ADC_FX_ENABLES_REG … /* GPIO */ #define LM49453_P0_GPIO1_REG … #define LM49453_P0_GPIO2_REG … #define LM49453_P0_GPIO3_REG … #define LM49453_P0_HAP_CTL_REG … #define LM49453_P0_HAP_FREQ_PROG_LEFTL_REG … #define LM49453_P0_HAP_FREQ_PROG_LEFTH_REG … #define LM49453_P0_HAP_FREQ_PROG_RIGHTL_REG … #define LM49453_P0_HAP_FREQ_PROG_RIGHTH_REG … /* DIGITAL MIXER */ #define LM49453_P0_DMIX_CLK_SEL_REG … #define LM49453_P0_PORT1_RX_LVL1_REG … #define LM49453_P0_PORT1_RX_LVL2_REG … #define LM49453_P0_PORT2_RX_LVL_REG … #define LM49453_P0_PORT1_TX1_REG … #define LM49453_P0_PORT1_TX2_REG … #define LM49453_P0_PORT1_TX3_REG … #define LM49453_P0_PORT1_TX4_REG … #define LM49453_P0_PORT1_TX5_REG … #define LM49453_P0_PORT1_TX6_REG … #define LM49453_P0_PORT1_TX7_REG … #define LM49453_P0_PORT1_TX8_REG … #define LM49453_P0_PORT2_TX1_REG … #define LM49453_P0_PORT2_TX2_REG … #define LM49453_P0_STN_SEL_REG … #define LM49453_P0_DACHPL1_REG … #define LM49453_P0_DACHPL2_REG … #define LM49453_P0_DACHPR1_REG … #define LM49453_P0_DACHPR2_REG … #define LM49453_P0_DACLOL1_REG … #define LM49453_P0_DACLOL2_REG … #define LM49453_P0_DACLOR1_REG … #define LM49453_P0_DACLOR2_REG … #define LM49453_P0_DACLSL1_REG … #define LM49453_P0_DACLSL2_REG … #define LM49453_P0_DACLSR1_REG … #define LM49453_P0_DACLSR2_REG … #define LM49453_P0_DACHAL1_REG … #define LM49453_P0_DACHAL2_REG … #define LM49453_P0_DACHAR1_REG … #define LM49453_P0_DACHAR2_REG … /* AUDIO PORT 1 (TDM) */ #define LM49453_P0_AUDIO_PORT1_BASIC_REG … #define LM49453_P0_AUDIO_PORT1_CLK_GEN1_REG … #define LM49453_P0_AUDIO_PORT1_CLK_GEN2_REG … #define LM49453_P0_AUDIO_PORT1_CLK_GEN3_REG … #define LM49453_P0_AUDIO_PORT1_SYNC_RATE_REG … #define LM49453_P0_AUDIO_PORT1_SYNC_SDO_SETUP_REG … #define LM49453_P0_AUDIO_PORT1_DATA_WIDTH_REG … #define LM49453_P0_AUDIO_PORT1_RX_MSB_REG … #define LM49453_P0_AUDIO_PORT1_TX_MSB_REG … #define LM49453_P0_AUDIO_PORT1_TDM_CHANNELS_REG … /* AUDIO PORT 2 */ #define LM49453_P0_AUDIO_PORT2_BASIC_REG … #define LM49453_P0_AUDIO_PORT2_CLK_GEN1_REG … #define LM49453_P0_AUDIO_PORT2_CLK_GEN2_REG … #define LM49453_P0_AUDIO_PORT2_SYNC_GEN_REG … #define LM49453_P0_AUDIO_PORT2_DATA_WIDTH_REG … #define LM49453_P0_AUDIO_PORT2_RX_MODE_REG … #define LM49453_P0_AUDIO_PORT2_TX_MODE_REG … /* SAMPLE RATE */ #define LM49453_P0_PORT1_SR_LSB_REG … #define LM49453_P0_PORT1_SR_MSB_REG … #define LM49453_P0_PORT2_SR_LSB_REG … #define LM49453_P0_PORT2_SR_MSB_REG … /* EFFECTS - HPFs */ #define LM49453_P0_HPF_REG … /* EFFECTS ADC ALC */ #define LM49453_P0_ADC_ALC1_REG … #define LM49453_P0_ADC_ALC2_REG … #define LM49453_P0_ADC_ALC3_REG … #define LM49453_P0_ADC_ALC4_REG … #define LM49453_P0_ADC_ALC5_REG … #define LM49453_P0_ADC_ALC6_REG … #define LM49453_P0_ADC_ALC7_REG … #define LM49453_P0_ADC_ALC8_REG … #define LM49453_P0_DMIC1_LEVELL_REG … #define LM49453_P0_DMIC1_LEVELR_REG … #define LM49453_P0_DMIC2_LEVELL_REG … #define LM49453_P0_DMIC2_LEVELR_REG … #define LM49453_P0_ADC_LEVELL_REG … #define LM49453_P0_ADC_LEVELR_REG … #define LM49453_P0_DAC_HP_LEVELL_REG … #define LM49453_P0_DAC_HP_LEVELR_REG … #define LM49453_P0_DAC_LO_LEVELL_REG … #define LM49453_P0_DAC_LO_LEVELR_REG … #define LM49453_P0_DAC_LS_LEVELL_REG … #define LM49453_P0_DAC_LS_LEVELR_REG … #define LM49453_P0_DAC_HA_LEVELL_REG … #define LM49453_P0_DAC_HA_LEVELR_REG … #define LM49453_P0_SOFT_MUTE_REG … #define LM49453_P0_DMIC_MUTE_CFG_REG … #define LM49453_P0_ADC_MUTE_CFG_REG … #define LM49453_P0_DAC_MUTE_CFG_REG … /*DIGITAL MIC1 */ #define LM49453_P0_DIGITAL_MIC1_CONFIG_REG … #define LM49453_P0_DIGITAL_MIC1_DATA_DELAYL_REG … #define LM49453_P0_DIGITAL_MIC1_DATA_DELAYR_REG … /*DIGITAL MIC2 */ #define LM49453_P0_DIGITAL_MIC2_CONFIG_REG … #define LM49453_P0_DIGITAL_MIC2_DATA_DELAYL_REG … #define LM49453_P0_DIGITAL_MIC2_DATA_DELAYR_REG … /* ADC DECIMATOR */ #define LM49453_P0_ADC_DECIMATOR_REG … /* DAC CONFIGURE */ #define LM49453_P0_DAC_CONFIG_REG … /* SIDETONE */ #define LM49453_P0_STN_VOL_ADCL_REG … #define LM49453_P0_STN_VOL_ADCR_REG … #define LM49453_P0_STN_VOL_DMIC1L_REG … #define LM49453_P0_STN_VOL_DMIC1R_REG … #define LM49453_P0_STN_VOL_DMIC2L_REG … #define LM49453_P0_STN_VOL_DMIC2R_REG … /* ADC/DAC CLIPPING MONITORS (Read Only/Write to Clear) */ #define LM49453_P0_ADC_DEC_CLIP_REG … #define LM49453_P0_ADC_HPF_CLIP_REG … #define LM49453_P0_ADC_LVL_CLIP_REG … #define LM49453_P0_DAC_LVL_CLIP_REG … /* ADC ALC EFFECT MONITORS (Read Only) */ #define LM49453_P0_ADC_LVLMONL_REG … #define LM49453_P0_ADC_LVLMONR_REG … #define LM49453_P0_ADC_ALCMONL_REG … #define LM49453_P0_ADC_ALCMONR_REG … #define LM49453_P0_ADC_MUTED_REG … #define LM49453_P0_DAC_MUTED_REG … /* HEADSET DETECT */ #define LM49453_P0_HSD_PPB_LONG_CNT_LIMITL_REG … #define LM49453_P0_HSD_PPB_LONG_CNT_LIMITR_REG … #define LM49453_P0_HSD_PIN3_4_EX_LOOP_CNT_LIMITL_REG … #define LM49453_P0_HSD_PIN3_4_EX_LOOP_CNT_LIMITH_REG … #define LM49453_P0_HSD_TIMEOUT1_REG … #define LM49453_P0_HSD_TIMEOUT2_REG … #define LM49453_P0_HSD_TIMEOUT3_REG … #define LM49453_P0_HSD_PIN3_4_CFG_REG … #define LM49453_P0_HSD_IRQ1_REG … #define LM49453_P0_HSD_IRQ2_REG … #define LM49453_P0_HSD_IRQ3_REG … #define LM49453_P0_HSD_IRQ4_REG … #define LM49453_P0_HSD_IRQ_MASK1_REG … #define LM49453_P0_HSD_IRQ_MASK2_REG … #define LM49453_P0_HSD_IRQ_MASK3_REG … #define LM49453_P0_HSD_R_HPLL_REG … #define LM49453_P0_HSD_R_HPLH_REG … #define LM49453_P0_HSD_R_HPLU_REG … #define LM49453_P0_HSD_R_HPRL_REG … #define LM49453_P0_HSD_R_HPRH_REG … #define LM49453_P0_HSD_R_HPRU_REG … #define LM49453_P0_HSD_VEL_L_FINALL_REG … #define LM49453_P0_HSD_VEL_L_FINALH_REG … #define LM49453_P0_HSD_VEL_L_FINALU_REG … #define LM49453_P0_HSD_RO_FINALL_REG … #define LM49453_P0_HSD_RO_FINALH_REG … #define LM49453_P0_HSD_RO_FINALU_REG … #define LM49453_P0_HSD_VMIC_BIAS_FINALL_REG … #define LM49453_P0_HSD_VMIC_BIAS_FINALH_REG … #define LM49453_P0_HSD_VMIC_BIAS_FINALU_REG … #define LM49453_P0_HSD_PIN_CONFIG_REG … #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS1_REG … #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS2_REG … #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS3_REG … #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATEL_REG … #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATEH_REG … /* I/O PULLDOWN CONFIG */ #define LM49453_P0_PULL_CONFIG1_REG … #define LM49453_P0_PULL_CONFIG2_REG … #define LM49453_P0_PULL_CONFIG3_REG … /* RESET */ #define LM49453_P0_RESET_REG … /* PAGE */ #define LM49453_PAGE_REG … #define LM49453_MAX_REGISTER … /* LM49453_P0_PMC_SETUP_REG (0x00h) */ #define LM49453_PMC_SETUP_CHIP_EN … #define LM49453_PMC_SETUP_PLL_EN … #define LM49453_PMC_SETUP_PLL_P2_EN … #define LM49453_PMC_SETUP_PLL_FLL … #define LM49453_PMC_SETUP_MCLK_OVER … #define LM49453_PMC_SETUP_RTC_CLK_OVER … #define LM49453_PMC_SETUP_CHIP_ACTIVE … /* Chip Enable bits */ #define LM49453_CHIP_EN_SHUTDOWN … #define LM49453_CHIP_EN … #define LM49453_CHIP_EN_HSD_DETECT … #define LM49453_CHIP_EN_INVALID_HSD … /* LM49453_P0_PLL_CLK_SEL1_REG (0x01h) */ #define LM49453_CLK_SEL1_MCLK_SEL … #define LM49453_CLK_SEL1_RTC_SEL … #define LM49453_CLK_SEL1_PORT1_SEL … #define LM49453_CLK_SEL1_PORT2_SEL … /* LM49453_P0_PLL_CLK_SEL2_REG (0x02h) */ #define LM49453_CLK_SEL2_ADC_CLK_SEL … /* LM49453_P0_FLL_REF_FREQL_REG (0x0F) */ #define LM49453_FLL_REF_FREQ_VAL … /* LM49453_P0_VCO_TARGETLL_REG (0x11) */ #define LM49453_VCO_TARGET_VAL … /* LM49453_P0_ADC_DSP_REG (0x30h) */ #define LM49453_ADC_DSP_ADC_MUTEL … #define LM49453_ADC_DSP_ADC_MUTER … #define LM49453_ADC_DSP_DMIC1_MUTEL … #define LM49453_ADC_DSP_DMIC1_MUTER … #define LM49453_ADC_DSP_DMIC2_MUTEL … #define LM49453_ADC_DSP_DMIC2_MUTER … #define LM49453_ADC_DSP_MUTE_ALL … /* LM49453_P0_DAC_DSP_REG (0x31h) */ #define LM49453_DAC_DSP_MUTE_ALL … /* LM49453_P0_AUDIO_PORT1_BASIC_REG (0x60h) */ #define LM49453_AUDIO_PORT1_BASIC_FMT_MASK … #define LM49453_AUDIO_PORT1_BASIC_CLK_MS … #define LM49453_AUDIO_PORT1_BASIC_SYNC_MS … /* LM49453_P0_RESET_REG (0xFEh) */ #define LM49453_RESET_REG_RST … /* Page select register bits (0xFF) */ #define LM49453_PAGE0_SELECT … #define LM49453_PAGE1_SELECT … /* LM49453_P0_HSD_PIN3_4_CFG_REG (Jack Pin config - 0xD7) */ #define LM49453_JACK_DISABLE … #define LM49453_JACK_CONFIG1 … #define LM49453_JACK_CONFIG2 … #define LM49453_JACK_CONFIG3 … #define LM49453_JACK_CONFIG4 … #define LM49453_JACK_CONFIG5 … /* Page 1 REGISTERS */ /* SIDETONE */ #define LM49453_P1_SIDETONE_SA0L_REG … #define LM49453_P1_SIDETONE_SA0H_REG … #define LM49453_P1_SIDETONE_SAB0U_REG … #define LM49453_P1_SIDETONE_SB0L_REG … #define LM49453_P1_SIDETONE_SB0H_REG … #define LM49453_P1_SIDETONE_SH0L_REG … #define LM49453_P1_SIDETONE_SH0H_REG … #define LM49453_P1_SIDETONE_SH0U_REG … #define LM49453_P1_SIDETONE_SA1L_REG … #define LM49453_P1_SIDETONE_SA1H_REG … #define LM49453_P1_SIDETONE_SAB1U_REG … #define LM49453_P1_SIDETONE_SB1L_REG … #define LM49453_P1_SIDETONE_SB1H_REG … #define LM49453_P1_SIDETONE_SH1L_REG … #define LM49453_P1_SIDETONE_SH1H_REG … #define LM49453_P1_SIDETONE_SH1U_REG … #define LM49453_P1_SIDETONE_SA2L_REG … #define LM49453_P1_SIDETONE_SA2H_REG … #define LM49453_P1_SIDETONE_SAB2U_REG … #define LM49453_P1_SIDETONE_SB2L_REG … #define LM49453_P1_SIDETONE_SB2H_REG … #define LM49453_P1_SIDETONE_SH2L_REG … #define LM49453_P1_SIDETONE_SH2H_REG … #define LM49453_P1_SIDETONE_SH2U_REG … #define LM49453_P1_SIDETONE_SA3L_REG … #define LM49453_P1_SIDETONE_SA3H_REG … #define LM49453_P1_SIDETONE_SAB3U_REG … #define LM49453_P1_SIDETONE_SB3L_REG … #define LM49453_P1_SIDETONE_SB3H_REG … #define LM49453_P1_SIDETONE_SH3L_REG … #define LM49453_P1_SIDETONE_SH3H_REG … #define LM49453_P1_SIDETONE_SH3U_REG … #define LM49453_P1_SIDETONE_SA4L_REG … #define LM49453_P1_SIDETONE_SA4H_REG … #define LM49453_P1_SIDETONE_SAB4U_REG … #define LM49453_P1_SIDETONE_SB4L_REG … #define LM49453_P1_SIDETONE_SB4H_REG … #define LM49453_P1_SIDETONE_SH4L_REG … #define LM49453_P1_SIDETONE_SH4H_REG … #define LM49453_P1_SIDETONE_SH4U_REG … #define LM49453_P1_SIDETONE_SA5L_REG … #define LM49453_P1_SIDETONE_SA5H_REG … #define LM49453_P1_SIDETONE_SAB5U_REG … #define LM49453_P1_SIDETONE_SB5L_REG … #define LM49453_P1_SIDETONE_SB5H_REG … #define LM49453_P1_SIDETONE_SH5L_REG … #define LM49453_P1_SIDETONE_SH5H_REG … #define LM49453_P1_SIDETONE_SH5U_REG … /* CHARGE PUMP CONFIG */ #define LM49453_P1_CP_CONFIG1_REG … #define LM49453_P1_CP_CONFIG2_REG … #define LM49453_P1_CP_CONFIG3_REG … #define LM49453_P1_CP_CONFIG4_REG … #define LM49453_P1_CP_LA_VTH1L_REG … #define LM49453_P1_CP_LA_VTH1M_REG … #define LM49453_P1_CP_LA_VTH2L_REG … #define LM49453_P1_CP_LA_VTH2M_REG … #define LM49453_P1_CP_LA_VTH3L_REG … #define LM49453_P1_CP_LA_VTH3H_REG … #define LM49453_P1_CP_CLK_DIV_REG … /* DAC */ #define LM49453_P1_DAC_CHOP_REG … #define LM49453_CLK_SRC_MCLK … #endif
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