/* SPDX-License-Identifier: GPL-2.0-only */ /* * max98090.h -- MAX98090 ALSA SoC Audio driver * * Copyright 2011-2012 Maxim Integrated Products */ #ifndef _MAX98090_H #define _MAX98090_H /* * The default operating frequency for a DMIC attached to the codec. * This can be overridden by a device tree property. */ #define MAX98090_DEFAULT_DMIC_FREQ … /* * MAX98090 Register Definitions */ #define M98090_REG_SOFTWARE_RESET … #define M98090_REG_DEVICE_STATUS … #define M98090_REG_JACK_STATUS … #define M98090_REG_INTERRUPT_S … #define M98090_REG_QUICK_SYSTEM_CLOCK … #define M98090_REG_QUICK_SAMPLE_RATE … #define M98090_REG_DAI_INTERFACE … #define M98090_REG_DAC_PATH … #define M98090_REG_MIC_DIRECT_TO_ADC … #define M98090_REG_LINE_TO_ADC … #define M98090_REG_ANALOG_MIC_LOOP … #define M98090_REG_ANALOG_LINE_LOOP … #define M98090_REG_RESERVED … #define M98090_REG_LINE_INPUT_CONFIG … #define M98090_REG_LINE_INPUT_LEVEL … #define M98090_REG_INPUT_MODE … #define M98090_REG_MIC1_INPUT_LEVEL … #define M98090_REG_MIC2_INPUT_LEVEL … #define M98090_REG_MIC_BIAS_VOLTAGE … #define M98090_REG_DIGITAL_MIC_ENABLE … #define M98090_REG_DIGITAL_MIC_CONFIG … #define M98090_REG_LEFT_ADC_MIXER … #define M98090_REG_RIGHT_ADC_MIXER … #define M98090_REG_LEFT_ADC_LEVEL … #define M98090_REG_RIGHT_ADC_LEVEL … #define M98090_REG_ADC_BIQUAD_LEVEL … #define M98090_REG_ADC_SIDETONE … #define M98090_REG_SYSTEM_CLOCK … #define M98090_REG_CLOCK_MODE … #define M98090_REG_CLOCK_RATIO_NI_MSB … #define M98090_REG_CLOCK_RATIO_NI_LSB … #define M98090_REG_CLOCK_RATIO_MI_MSB … #define M98090_REG_CLOCK_RATIO_MI_LSB … #define M98090_REG_MASTER_MODE … #define M98090_REG_INTERFACE_FORMAT … #define M98090_REG_TDM_CONTROL … #define M98090_REG_TDM_FORMAT … #define M98090_REG_IO_CONFIGURATION … #define M98090_REG_FILTER_CONFIG … #define M98090_REG_DAI_PLAYBACK_LEVEL … #define M98090_REG_DAI_PLAYBACK_LEVEL_EQ … #define M98090_REG_LEFT_HP_MIXER … #define M98090_REG_RIGHT_HP_MIXER … #define M98090_REG_HP_CONTROL … #define M98090_REG_LEFT_HP_VOLUME … #define M98090_REG_RIGHT_HP_VOLUME … #define M98090_REG_LEFT_SPK_MIXER … #define M98090_REG_RIGHT_SPK_MIXER … #define M98090_REG_SPK_CONTROL … #define M98090_REG_LEFT_SPK_VOLUME … #define M98090_REG_RIGHT_SPK_VOLUME … #define M98090_REG_DRC_TIMING … #define M98090_REG_DRC_COMPRESSOR … #define M98090_REG_DRC_EXPANDER … #define M98090_REG_DRC_GAIN … #define M98090_REG_RCV_LOUTL_MIXER … #define M98090_REG_RCV_LOUTL_CONTROL … #define M98090_REG_RCV_LOUTL_VOLUME … #define M98090_REG_LOUTR_MIXER … #define M98090_REG_LOUTR_CONTROL … #define M98090_REG_LOUTR_VOLUME … #define M98090_REG_JACK_DETECT … #define M98090_REG_INPUT_ENABLE … #define M98090_REG_OUTPUT_ENABLE … #define M98090_REG_LEVEL_CONTROL … #define M98090_REG_DSP_FILTER_ENABLE … #define M98090_REG_BIAS_CONTROL … #define M98090_REG_DAC_CONTROL … #define M98090_REG_ADC_CONTROL … #define M98090_REG_DEVICE_SHUTDOWN … #define M98090_REG_EQUALIZER_BASE … #define M98090_REG_RECORD_BIQUAD_BASE … #define M98090_REG_DMIC3_VOLUME … #define M98090_REG_DMIC4_VOLUME … #define M98090_REG_DMIC34_BQ_PREATTEN … #define M98090_REG_RECORD_TDM_SLOT … #define M98090_REG_SAMPLE_RATE … #define M98090_REG_DMIC34_BIQUAD_BASE … #define M98090_REG_REVISION_ID … #define M98090_REG_CNT … #define MAX98090_MAX_REGISTER … /* MAX98090 Register Bit Fields */ /* * M98090_REG_SOFTWARE_RESET */ #define M98090_SWRESET_MASK … #define M98090_SWRESET_SHIFT … #define M98090_SWRESET_WIDTH … /* * M98090_REG_DEVICE_STATUS */ #define M98090_CLD_MASK … #define M98090_CLD_SHIFT … #define M98090_CLD_WIDTH … #define M98090_SLD_MASK … #define M98090_SLD_SHIFT … #define M98090_SLD_WIDTH … #define M98090_ULK_MASK … #define M98090_ULK_SHIFT … #define M98090_ULK_WIDTH … #define M98090_JDET_MASK … #define M98090_JDET_SHIFT … #define M98090_JDET_WIDTH … #define M98090_DRCACT_MASK … #define M98090_DRCACT_SHIFT … #define M98090_DRCACT_WIDTH … #define M98090_DRCCLP_MASK … #define M98090_DRCCLP_SHIFT … #define M98090_DRCCLP_WIDTH … /* * M98090_REG_JACK_STATUS */ #define M98090_LSNS_MASK … #define M98090_LSNS_SHIFT … #define M98090_LSNS_WIDTH … #define M98090_JKSNS_MASK … #define M98090_JKSNS_SHIFT … #define M98090_JKSNS_WIDTH … /* * M98090_REG_INTERRUPT_S */ #define M98090_ICLD_MASK … #define M98090_ICLD_SHIFT … #define M98090_ICLD_WIDTH … #define M98090_ISLD_MASK … #define M98090_ISLD_SHIFT … #define M98090_ISLD_WIDTH … #define M98090_IULK_MASK … #define M98090_IULK_SHIFT … #define M98090_IULK_WIDTH … #define M98090_IJDET_MASK … #define M98090_IJDET_SHIFT … #define M98090_IJDET_WIDTH … #define M98090_IDRCACT_MASK … #define M98090_IDRCACT_SHIFT … #define M98090_IDRCACT_WIDTH … #define M98090_IDRCCLP_MASK … #define M98090_IDRCCLP_SHIFT … #define M98090_IDRCCLP_WIDTH … /* * M98090_REG_QUICK_SYSTEM_CLOCK */ #define M98090_26M_MASK … #define M98090_26M_SHIFT … #define M98090_26M_WIDTH … #define M98090_19P2M_MASK … #define M98090_19P2M_SHIFT … #define M98090_19P2M_WIDTH … #define M98090_13M_MASK … #define M98090_13M_SHIFT … #define M98090_13M_WIDTH … #define M98090_12P288M_MASK … #define M98090_12P288M_SHIFT … #define M98090_12P288M_WIDTH … #define M98090_12M_MASK … #define M98090_12M_SHIFT … #define M98090_12M_WIDTH … #define M98090_11P2896M_MASK … #define M98090_11P2896M_SHIFT … #define M98090_11P2896M_WIDTH … #define M98090_256FS_MASK … #define M98090_256FS_SHIFT … #define M98090_256FS_WIDTH … #define M98090_CLK_ALL_SHIFT … #define M98090_CLK_ALL_WIDTH … #define M98090_CLK_ALL_NUM … /* * M98090_REG_QUICK_SAMPLE_RATE */ #define M98090_SR_96K_MASK … #define M98090_SR_96K_SHIFT … #define M98090_SR_96K_WIDTH … #define M98090_SR_32K_MASK … #define M98090_SR_32K_SHIFT … #define M98090_SR_32K_WIDTH … #define M98090_SR_48K_MASK … #define M98090_SR_48K_SHIFT … #define M98090_SR_48K_WIDTH … #define M98090_SR_44K1_MASK … #define M98090_SR_44K1_SHIFT … #define M98090_SR_44K1_WIDTH … #define M98090_SR_16K_MASK … #define M98090_SR_16K_SHIFT … #define M98090_SR_16K_WIDTH … #define M98090_SR_8K_MASK … #define M98090_SR_8K_SHIFT … #define M98090_SR_8K_WIDTH … #define M98090_SR_MASK … #define M98090_SR_ALL_SHIFT … #define M98090_SR_ALL_WIDTH … #define M98090_SR_ALL_NUM … /* * M98090_REG_DAI_INTERFACE */ #define M98090_RJ_M_MASK … #define M98090_RJ_M_SHIFT … #define M98090_RJ_M_WIDTH … #define M98090_RJ_S_MASK … #define M98090_RJ_S_SHIFT … #define M98090_RJ_S_WIDTH … #define M98090_LJ_M_MASK … #define M98090_LJ_M_SHIFT … #define M98090_LJ_M_WIDTH … #define M98090_LJ_S_MASK … #define M98090_LJ_S_SHIFT … #define M98090_LJ_S_WIDTH … #define M98090_I2S_M_MASK … #define M98090_I2S_M_SHIFT … #define M98090_I2S_M_WIDTH … #define M98090_I2S_S_MASK … #define M98090_I2S_S_SHIFT … #define M98090_I2S_S_WIDTH … #define M98090_DAI_ALL_SHIFT … #define M98090_DAI_ALL_WIDTH … #define M98090_DAI_ALL_NUM … /* * M98090_REG_DAC_PATH */ #define M98090_DIG2_HP_MASK … #define M98090_DIG2_HP_SHIFT … #define M98090_DIG2_HP_WIDTH … #define M98090_DIG2_EAR_MASK … #define M98090_DIG2_EAR_SHIFT … #define M98090_DIG2_EAR_WIDTH … #define M98090_DIG2_SPK_MASK … #define M98090_DIG2_SPK_SHIFT … #define M98090_DIG2_SPK_WIDTH … #define M98090_DIG2_LOUT_MASK … #define M98090_DIG2_LOUT_SHIFT … #define M98090_DIG2_LOUT_WIDTH … #define M98090_DIG2_ALL_SHIFT … #define M98090_DIG2_ALL_WIDTH … #define M98090_DIG2_ALL_NUM … /* * M98090_REG_MIC_DIRECT_TO_ADC */ #define M98090_IN12_MIC1_MASK … #define M98090_IN12_MIC1_SHIFT … #define M98090_IN12_MIC1_WIDTH … #define M98090_IN34_MIC2_MASK … #define M98090_IN34_MIC2_SHIFT … #define M98090_IN34_MIC2_WIDTH … #define M98090_IN56_MIC1_MASK … #define M98090_IN56_MIC1_SHIFT … #define M98090_IN56_MIC1_WIDTH … #define M98090_IN56_MIC2_MASK … #define M98090_IN56_MIC2_SHIFT … #define M98090_IN56_MIC2_WIDTH … #define M98090_IN12_DADC_MASK … #define M98090_IN12_DADC_SHIFT … #define M98090_IN12_DADC_WIDTH … #define M98090_IN34_DADC_MASK … #define M98090_IN34_DADC_SHIFT … #define M98090_IN34_DADC_WIDTH … #define M98090_IN56_DADC_MASK … #define M98090_IN56_DADC_SHIFT … #define M98090_IN56_DADC_WIDTH … #define M98090_MIC_ALL_SHIFT … #define M98090_MIC_ALL_WIDTH … #define M98090_MIC_ALL_NUM … /* * M98090_REG_LINE_TO_ADC */ #define M98090_IN12S_AB_MASK … #define M98090_IN12S_AB_SHIFT … #define M98090_IN12S_AB_WIDTH … #define M98090_IN34S_AB_MASK … #define M98090_IN34S_AB_SHIFT … #define M98090_IN34S_AB_WIDTH … #define M98090_IN56S_AB_MASK … #define M98090_IN56S_AB_SHIFT … #define M98090_IN56S_AB_WIDTH … #define M98090_IN34D_A_MASK … #define M98090_IN34D_A_SHIFT … #define M98090_IN34D_A_WIDTH … #define M98090_IN56D_B_MASK … #define M98090_IN56D_B_SHIFT … #define M98090_IN56D_B_WIDTH … #define M98090_LINE_ALL_SHIFT … #define M98090_LINE_ALL_WIDTH … #define M98090_LINE_ALL_NUM … /* * M98090_REG_ANALOG_MIC_LOOP */ #define M98090_IN12_M1HPL_MASK … #define M98090_IN12_M1HPL_SHIFT … #define M98090_IN12_M1HPL_WIDTH … #define M98090_IN12_M1SPKL_MASK … #define M98090_IN12_M1SPKL_SHIFT … #define M98090_IN12_M1SPKL_WIDTH … #define M98090_IN12_M1EAR_MASK … #define M98090_IN12_M1EAR_SHIFT … #define M98090_IN12_M1EAR_WIDTH … #define M98090_IN12_M1LOUTL_MASK … #define M98090_IN12_M1LOUTL_SHIFT … #define M98090_IN12_M1LOUTL_WIDTH … #define M98090_IN34_M2HPR_MASK … #define M98090_IN34_M2HPR_SHIFT … #define M98090_IN34_M2HPR_WIDTH … #define M98090_IN34_M2SPKR_MASK … #define M98090_IN34_M2SPKR_SHIFT … #define M98090_IN34_M2SPKR_WIDTH … #define M98090_IN34_M2EAR_MASK … #define M98090_IN34_M2EAR_SHIFT … #define M98090_IN34_M2EAR_WIDTH … #define M98090_IN34_M2LOUTR_MASK … #define M98090_IN34_M2LOUTR_SHIFT … #define M98090_IN34_M2LOUTR_WIDTH … #define M98090_AMIC_ALL_SHIFT … #define M98090_AMIC_ALL_WIDTH … #define M98090_AMIC_ALL_NUM … /* * M98090_REG_ANALOG_LINE_LOOP */ #define M98090_IN12S_ABHP_MASK … #define M98090_IN12S_ABHP_SHIFT … #define M98090_IN12S_ABHP_WIDTH … #define M98090_IN34D_ASPKL_MASK … #define M98090_IN34D_ASPKL_SHIFT … #define M98090_IN34D_ASPKL_WIDTH … #define M98090_IN34D_AEAR_MASK … #define M98090_IN34D_AEAR_SHIFT … #define M98090_IN34D_AEAR_WIDTH … #define M98090_IN12S_ABLOUT_MASK … #define M98090_IN12S_ABLOUT_SHIFT … #define M98090_IN12S_ABLOUT_WIDTH … #define M98090_IN34S_ABHP_MASK … #define M98090_IN34S_ABHP_SHIFT … #define M98090_IN34S_ABHP_WIDTH … #define M98090_IN56D_BSPKR_MASK … #define M98090_IN56D_BSPKR_SHIFT … #define M98090_IN56D_BSPKR_WIDTH … #define M98090_IN56D_BEAR_MASK … #define M98090_IN56D_BEAR_SHIFT … #define M98090_IN56D_BEAR_WIDTH … #define M98090_IN34S_ABLOUT_MASK … #define M98090_IN34S_ABLOUT_SHIFT … #define M98090_IN34S_ABLOUT_WIDTH … #define M98090_ALIN_ALL_SHIFT … #define M98090_ALIN_ALL_WIDTH … #define M98090_ALIN_ALL_NUM … /* * M98090_REG_RESERVED */ /* * M98090_REG_LINE_INPUT_CONFIG */ #define M98090_IN34DIFF_MASK … #define M98090_IN34DIFF_SHIFT … #define M98090_IN34DIFF_WIDTH … #define M98090_IN56DIFF_MASK … #define M98090_IN56DIFF_SHIFT … #define M98090_IN56DIFF_WIDTH … #define M98090_IN1SEEN_MASK … #define M98090_IN1SEEN_SHIFT … #define M98090_IN1SEEN_WIDTH … #define M98090_IN2SEEN_MASK … #define M98090_IN2SEEN_SHIFT … #define M98090_IN2SEEN_WIDTH … #define M98090_IN3SEEN_MASK … #define M98090_IN3SEEN_SHIFT … #define M98090_IN3SEEN_WIDTH … #define M98090_IN4SEEN_MASK … #define M98090_IN4SEEN_SHIFT … #define M98090_IN4SEEN_WIDTH … #define M98090_IN5SEEN_MASK … #define M98090_IN5SEEN_SHIFT … #define M98090_IN5SEEN_WIDTH … #define M98090_IN6SEEN_MASK … #define M98090_IN6SEEN_SHIFT … #define M98090_IN6SEEN_WIDTH … /* * M98090_REG_LINE_INPUT_LEVEL */ #define M98090_MIXG135_MASK … #define M98090_MIXG135_SHIFT … #define M98090_MIXG135_WIDTH … #define M98090_MIXG135_NUM … #define M98090_MIXG246_MASK … #define M98090_MIXG246_SHIFT … #define M98090_MIXG246_WIDTH … #define M98090_MIXG246_NUM … #define M98090_LINAPGA_MASK … #define M98090_LINAPGA_SHIFT … #define M98090_LINAPGA_WIDTH … #define M98090_LINAPGA_NUM … #define M98090_LINBPGA_MASK … #define M98090_LINBPGA_SHIFT … #define M98090_LINBPGA_WIDTH … #define M98090_LINBPGA_NUM … /* * M98090_REG_INPUT_MODE */ #define M98090_EXTBUFA_MASK … #define M98090_EXTBUFA_SHIFT … #define M98090_EXTBUFA_WIDTH … #define M98090_EXTBUFA_NUM … #define M98090_EXTBUFB_MASK … #define M98090_EXTBUFB_SHIFT … #define M98090_EXTBUFB_WIDTH … #define M98090_EXTBUFB_NUM … #define M98090_EXTMIC_MASK … #define M98090_EXTMIC_SHIFT … #define M98090_EXTMIC1_SHIFT … #define M98090_EXTMIC2_SHIFT … #define M98090_EXTMIC_WIDTH … #define M98090_EXTMIC_NONE … #define M98090_EXTMIC_MIC1 … #define M98090_EXTMIC_MIC2 … /* * M98090_REG_MIC1_INPUT_LEVEL */ #define M98090_MIC_PA1EN_MASK … #define M98090_MIC_PA1EN_SHIFT … #define M98090_MIC_PA1EN_WIDTH … #define M98090_MIC_PA1EN_NUM … #define M98090_MIC_PGAM1_MASK … #define M98090_MIC_PGAM1_SHIFT … #define M98090_MIC_PGAM1_WIDTH … #define M98090_MIC_PGAM1_NUM … /* * M98090_REG_MIC2_INPUT_LEVEL */ #define M98090_MIC_PA2EN_MASK … #define M98090_MIC_PA2EN_SHIFT … #define M98090_MIC_PA2EN_WIDTH … #define M98090_MIC_PA2EN_NUM … #define M98090_MIC_PGAM2_MASK … #define M98090_MIC_PGAM2_SHIFT … #define M98090_MIC_PGAM2_WIDTH … #define M98090_MIC_PGAM2_NUM … /* * M98090_REG_MIC_BIAS_VOLTAGE */ #define M98090_MBVSEL_MASK … #define M98090_MBVSEL_SHIFT … #define M98090_MBVSEL_WIDTH … #define M98090_MBVSEL_2V8 … #define M98090_MBVSEL_2V55 … #define M98090_MBVSEL_2V4 … #define M98090_MBVSEL_2V2 … /* * M98090_REG_DIGITAL_MIC_ENABLE */ #define M98090_MICCLK_MASK … #define M98090_MICCLK_SHIFT … #define M98090_MICCLK_WIDTH … #define M98090_DIGMIC4_MASK … #define M98090_DIGMIC4_SHIFT … #define M98090_DIGMIC4_WIDTH … #define M98090_DIGMIC4_NUM … #define M98090_DIGMIC3_MASK … #define M98090_DIGMIC3_SHIFT … #define M98090_DIGMIC3_WIDTH … #define M98090_DIGMIC3_NUM … #define M98090_DIGMICR_MASK … #define M98090_DIGMICR_SHIFT … #define M98090_DIGMICR_WIDTH … #define M98090_DIGMICR_NUM … #define M98090_DIGMICL_MASK … #define M98090_DIGMICL_SHIFT … #define M98090_DIGMICL_WIDTH … #define M98090_DIGMICL_NUM … /* * M98090_REG_DIGITAL_MIC_CONFIG */ #define M98090_DMIC_COMP_MASK … #define M98090_DMIC_COMP_SHIFT … #define M98090_DMIC_COMP_WIDTH … #define M98090_DMIC_COMP_NUM … #define M98090_DMIC_FREQ_MASK … #define M98090_DMIC_FREQ_SHIFT … #define M98090_DMIC_FREQ_WIDTH … /* * M98090_REG_LEFT_ADC_MIXER */ #define M98090_MIXADL_MIC2_MASK … #define M98090_MIXADL_MIC2_SHIFT … #define M98090_MIXADL_MIC2_WIDTH … #define M98090_MIXADL_MIC1_MASK … #define M98090_MIXADL_MIC1_SHIFT … #define M98090_MIXADL_MIC1_WIDTH … #define M98090_MIXADL_LINEB_MASK … #define M98090_MIXADL_LINEB_SHIFT … #define M98090_MIXADL_LINEB_WIDTH … #define M98090_MIXADL_LINEA_MASK … #define M98090_MIXADL_LINEA_SHIFT … #define M98090_MIXADL_LINEA_WIDTH … #define M98090_MIXADL_IN65DIFF_MASK … #define M98090_MIXADL_IN65DIFF_SHIFT … #define M98090_MIXADL_IN65DIFF_WIDTH … #define M98090_MIXADL_IN34DIFF_MASK … #define M98090_MIXADL_IN34DIFF_SHIFT … #define M98090_MIXADL_IN34DIFF_WIDTH … #define M98090_MIXADL_IN12DIFF_MASK … #define M98090_MIXADL_IN12DIFF_SHIFT … #define M98090_MIXADL_IN12DIFF_WIDTH … #define M98090_MIXADL_MASK … #define M98090_MIXADL_SHIFT … #define M98090_MIXADL_WIDTH … /* * M98090_REG_RIGHT_ADC_MIXER */ #define M98090_MIXADR_MIC2_MASK … #define M98090_MIXADR_MIC2_SHIFT … #define M98090_MIXADR_MIC2_WIDTH … #define M98090_MIXADR_MIC1_MASK … #define M98090_MIXADR_MIC1_SHIFT … #define M98090_MIXADR_MIC1_WIDTH … #define M98090_MIXADR_LINEB_MASK … #define M98090_MIXADR_LINEB_SHIFT … #define M98090_MIXADR_LINEB_WIDTH … #define M98090_MIXADR_LINEA_MASK … #define M98090_MIXADR_LINEA_SHIFT … #define M98090_MIXADR_LINEA_WIDTH … #define M98090_MIXADR_IN65DIFF_MASK … #define M98090_MIXADR_IN65DIFF_SHIFT … #define M98090_MIXADR_IN65DIFF_WIDTH … #define M98090_MIXADR_IN34DIFF_MASK … #define M98090_MIXADR_IN34DIFF_SHIFT … #define M98090_MIXADR_IN34DIFF_WIDTH … #define M98090_MIXADR_IN12DIFF_MASK … #define M98090_MIXADR_IN12DIFF_SHIFT … #define M98090_MIXADR_IN12DIFF_WIDTH … #define M98090_MIXADR_MASK … #define M98090_MIXADR_SHIFT … #define M98090_MIXADR_WIDTH … /* * M98090_REG_LEFT_ADC_LEVEL */ #define M98090_AVLG_MASK … #define M98090_AVLG_SHIFT … #define M98090_AVLG_WIDTH … #define M98090_AVLG_NUM … #define M98090_AVL_MASK … #define M98090_AVL_SHIFT … #define M98090_AVL_WIDTH … #define M98090_AVL_NUM … /* * M98090_REG_RIGHT_ADC_LEVEL */ #define M98090_AVRG_MASK … #define M98090_AVRG_SHIFT … #define M98090_AVRG_WIDTH … #define M98090_AVRG_NUM … #define M98090_AVR_MASK … #define M98090_AVR_SHIFT … #define M98090_AVR_WIDTH … #define M98090_AVR_NUM … /* * M98090_REG_ADC_BIQUAD_LEVEL */ #define M98090_AVBQ_MASK … #define M98090_AVBQ_SHIFT … #define M98090_AVBQ_WIDTH … #define M98090_AVBQ_NUM … /* * M98090_REG_ADC_SIDETONE */ #define M98090_DSTSR_MASK … #define M98090_DSTSR_SHIFT … #define M98090_DSTSR_WIDTH … #define M98090_DSTSL_MASK … #define M98090_DSTSL_SHIFT … #define M98090_DSTSL_WIDTH … #define M98090_DVST_MASK … #define M98090_DVST_SHIFT … #define M98090_DVST_WIDTH … #define M98090_DVST_NUM … /* * M98090_REG_SYSTEM_CLOCK */ #define M98090_PSCLK_MASK … #define M98090_PSCLK_SHIFT … #define M98090_PSCLK_WIDTH … #define M98090_PSCLK_DISABLED … #define M98090_PSCLK_DIV1 … #define M98090_PSCLK_DIV2 … #define M98090_PSCLK_DIV4 … /* * M98090_REG_CLOCK_MODE */ #define M98090_FREQ_MASK … #define M98090_FREQ_SHIFT … #define M98090_FREQ_WIDTH … #define M98090_USE_M1_MASK … #define M98090_USE_M1_SHIFT … #define M98090_USE_M1_WIDTH … #define M98090_USE_M1_NUM … /* * M98090_REG_CLOCK_RATIO_NI_MSB */ #define M98090_NI_HI_MASK … #define M98090_NI_HI_SHIFT … #define M98090_NI_HI_WIDTH … #define M98090_NI_HI_NUM … /* * M98090_REG_CLOCK_RATIO_NI_LSB */ #define M98090_NI_LO_MASK … #define M98090_NI_LO_SHIFT … #define M98090_NI_LO_WIDTH … #define M98090_NI_LO_NUM … /* * M98090_REG_CLOCK_RATIO_MI_MSB */ #define M98090_MI_HI_MASK … #define M98090_MI_HI_SHIFT … #define M98090_MI_HI_WIDTH … #define M98090_MI_HI_NUM … /* * M98090_REG_CLOCK_RATIO_MI_LSB */ #define M98090_MI_LO_MASK … #define M98090_MI_LO_SHIFT … #define M98090_MI_LO_WIDTH … #define M98090_MI_LO_NUM … /* * M98090_REG_MASTER_MODE */ #define M98090_MAS_MASK … #define M98090_MAS_SHIFT … #define M98090_MAS_WIDTH … #define M98090_BSEL_MASK … #define M98090_BSEL_SHIFT … #define M98090_BSEL_WIDTH … #define M98090_BSEL_32 … #define M98090_BSEL_48 … #define M98090_BSEL_64 … /* * M98090_REG_INTERFACE_FORMAT */ #define M98090_RJ_MASK … #define M98090_RJ_SHIFT … #define M98090_RJ_WIDTH … #define M98090_WCI_MASK … #define M98090_WCI_SHIFT … #define M98090_WCI_WIDTH … #define M98090_BCI_MASK … #define M98090_BCI_SHIFT … #define M98090_BCI_WIDTH … #define M98090_DLY_MASK … #define M98090_DLY_SHIFT … #define M98090_DLY_WIDTH … #define M98090_WS_MASK … #define M98090_WS_SHIFT … #define M98090_WS_WIDTH … #define M98090_WS_NUM … /* * M98090_REG_TDM_CONTROL */ #define M98090_FSW_MASK … #define M98090_FSW_SHIFT … #define M98090_FSW_WIDTH … #define M98090_TDM_MASK … #define M98090_TDM_SHIFT … #define M98090_TDM_WIDTH … #define M98090_TDM_NUM … /* * M98090_REG_TDM_FORMAT */ #define M98090_TDM_SLOTL_MASK … #define M98090_TDM_SLOTL_SHIFT … #define M98090_TDM_SLOTL_WIDTH … #define M98090_TDM_SLOTL_NUM … #define M98090_TDM_SLOTR_MASK … #define M98090_TDM_SLOTR_SHIFT … #define M98090_TDM_SLOTR_WIDTH … #define M98090_TDM_SLOTR_NUM … #define M98090_TDM_SLOTDLY_MASK … #define M98090_TDM_SLOTDLY_SHIFT … #define M98090_TDM_SLOTDLY_WIDTH … #define M98090_TDM_SLOTDLY_NUM … /* * M98090_REG_IO_CONFIGURATION */ #define M98090_LTEN_MASK … #define M98090_LTEN_SHIFT … #define M98090_LTEN_WIDTH … #define M98090_LTEN_NUM … #define M98090_LBEN_MASK … #define M98090_LBEN_SHIFT … #define M98090_LBEN_WIDTH … #define M98090_LBEN_NUM … #define M98090_DMONO_MASK … #define M98090_DMONO_SHIFT … #define M98090_DMONO_WIDTH … #define M98090_DMONO_NUM … #define M98090_HIZOFF_MASK … #define M98090_HIZOFF_SHIFT … #define M98090_HIZOFF_WIDTH … #define M98090_HIZOFF_NUM … #define M98090_SDOEN_MASK … #define M98090_SDOEN_SHIFT … #define M98090_SDOEN_WIDTH … #define M98090_SDOEN_NUM … #define M98090_SDIEN_MASK … #define M98090_SDIEN_SHIFT … #define M98090_SDIEN_WIDTH … #define M98090_SDIEN_NUM … /* * M98090_REG_FILTER_CONFIG */ #define M98090_MODE_MASK … #define M98090_MODE_SHIFT … #define M98090_MODE_WIDTH … #define M98090_AHPF_MASK … #define M98090_AHPF_SHIFT … #define M98090_AHPF_WIDTH … #define M98090_AHPF_NUM … #define M98090_DHPF_MASK … #define M98090_DHPF_SHIFT … #define M98090_DHPF_WIDTH … #define M98090_DHPF_NUM … #define M98090_DHF_MASK … #define M98090_DHF_SHIFT … #define M98090_DHF_WIDTH … #define M98090_FLT_DMIC34MODE_MASK … #define M98090_FLT_DMIC34MODE_SHIFT … #define M98090_FLT_DMIC34MODE_WIDTH … #define M98090_FLT_DMIC34HPF_MASK … #define M98090_FLT_DMIC34HPF_SHIFT … #define M98090_FLT_DMIC34HPF_WIDTH … #define M98090_FLT_DMIC34HPF_NUM … /* * M98090_REG_DAI_PLAYBACK_LEVEL */ #define M98090_DVM_MASK … #define M98090_DVM_SHIFT … #define M98090_DVM_WIDTH … #define M98090_DVG_MASK … #define M98090_DVG_SHIFT … #define M98090_DVG_WIDTH … #define M98090_DVG_NUM … #define M98090_DV_MASK … #define M98090_DV_SHIFT … #define M98090_DV_WIDTH … #define M98090_DV_NUM … /* * M98090_REG_DAI_PLAYBACK_LEVEL_EQ */ #define M98090_EQCLPN_MASK … #define M98090_EQCLPN_SHIFT … #define M98090_EQCLPN_WIDTH … #define M98090_EQCLPN_NUM … #define M98090_DVEQ_MASK … #define M98090_DVEQ_SHIFT … #define M98090_DVEQ_WIDTH … #define M98090_DVEQ_NUM … /* * M98090_REG_LEFT_HP_MIXER */ #define M98090_MIXHPL_MIC2_MASK … #define M98090_MIXHPL_MIC2_SHIFT … #define M98090_MIXHPL_MIC2_WIDTH … #define M98090_MIXHPL_MIC1_MASK … #define M98090_MIXHPL_MIC1_SHIFT … #define M98090_MIXHPL_MIC1_WIDTH … #define M98090_MIXHPL_LINEB_MASK … #define M98090_MIXHPL_LINEB_SHIFT … #define M98090_MIXHPL_LINEB_WIDTH … #define M98090_MIXHPL_LINEA_MASK … #define M98090_MIXHPL_LINEA_SHIFT … #define M98090_MIXHPL_LINEA_WIDTH … #define M98090_MIXHPL_DACR_MASK … #define M98090_MIXHPL_DACR_SHIFT … #define M98090_MIXHPL_DACR_WIDTH … #define M98090_MIXHPL_DACL_MASK … #define M98090_MIXHPL_DACL_SHIFT … #define M98090_MIXHPL_DACL_WIDTH … #define M98090_MIXHPL_MASK … #define M98090_MIXHPL_SHIFT … #define M98090_MIXHPL_WIDTH … /* * M98090_REG_RIGHT_HP_MIXER */ #define M98090_MIXHPR_MIC2_MASK … #define M98090_MIXHPR_MIC2_SHIFT … #define M98090_MIXHPR_MIC2_WIDTH … #define M98090_MIXHPR_MIC1_MASK … #define M98090_MIXHPR_MIC1_SHIFT … #define M98090_MIXHPR_MIC1_WIDTH … #define M98090_MIXHPR_LINEB_MASK … #define M98090_MIXHPR_LINEB_SHIFT … #define M98090_MIXHPR_LINEB_WIDTH … #define M98090_MIXHPR_LINEA_MASK … #define M98090_MIXHPR_LINEA_SHIFT … #define M98090_MIXHPR_LINEA_WIDTH … #define M98090_MIXHPR_DACR_MASK … #define M98090_MIXHPR_DACR_SHIFT … #define M98090_MIXHPR_DACR_WIDTH … #define M98090_MIXHPR_DACL_MASK … #define M98090_MIXHPR_DACL_SHIFT … #define M98090_MIXHPR_DACL_WIDTH … #define M98090_MIXHPR_MASK … #define M98090_MIXHPR_SHIFT … #define M98090_MIXHPR_WIDTH … /* * M98090_REG_HP_CONTROL */ #define M98090_MIXHPRSEL_MASK … #define M98090_MIXHPRSEL_SHIFT … #define M98090_MIXHPRSEL_WIDTH … #define M98090_MIXHPLSEL_MASK … #define M98090_MIXHPLSEL_SHIFT … #define M98090_MIXHPLSEL_WIDTH … #define M98090_MIXHPRG_MASK … #define M98090_MIXHPRG_SHIFT … #define M98090_MIXHPRG_WIDTH … #define M98090_MIXHPRG_NUM … #define M98090_MIXHPLG_MASK … #define M98090_MIXHPLG_SHIFT … #define M98090_MIXHPLG_WIDTH … #define M98090_MIXHPLG_NUM … /* * M98090_REG_LEFT_HP_VOLUME */ #define M98090_HPLM_MASK … #define M98090_HPLM_SHIFT … #define M98090_HPLM_WIDTH … #define M98090_HPVOLL_MASK … #define M98090_HPVOLL_SHIFT … #define M98090_HPVOLL_WIDTH … #define M98090_HPVOLL_NUM … /* * M98090_REG_RIGHT_HP_VOLUME */ #define M98090_HPRM_MASK … #define M98090_HPRM_SHIFT … #define M98090_HPRM_WIDTH … #define M98090_HPVOLR_MASK … #define M98090_HPVOLR_SHIFT … #define M98090_HPVOLR_WIDTH … #define M98090_HPVOLR_NUM … /* * M98090_REG_LEFT_SPK_MIXER */ #define M98090_MIXSPL_MIC2_MASK … #define M98090_MIXSPL_MIC2_SHIFT … #define M98090_MIXSPL_MIC2_WIDTH … #define M98090_MIXSPL_MIC1_MASK … #define M98090_MIXSPL_MIC1_SHIFT … #define M98090_MIXSPL_MIC1_WIDTH … #define M98090_MIXSPL_LINEB_MASK … #define M98090_MIXSPL_LINEB_SHIFT … #define M98090_MIXSPL_LINEB_WIDTH … #define M98090_MIXSPL_LINEA_MASK … #define M98090_MIXSPL_LINEA_SHIFT … #define M98090_MIXSPL_LINEA_WIDTH … #define M98090_MIXSPL_DACR_MASK … #define M98090_MIXSPL_DACR_SHIFT … #define M98090_MIXSPL_DACR_WIDTH … #define M98090_MIXSPL_DACL_MASK … #define M98090_MIXSPL_DACL_SHIFT … #define M98090_MIXSPL_DACL_WIDTH … #define M98090_MIXSPL_MASK … #define M98090_MIXSPL_SHIFT … #define M98090_MIXSPL_WIDTH … #define M98090_MIXSPR_DACR_MASK … #define M98090_MIXSPR_DACR_SHIFT … #define M98090_MIXSPR_DACR_WIDTH … /* * M98090_REG_RIGHT_SPK_MIXER */ #define M98090_SPK_SLAVE_MASK … #define M98090_SPK_SLAVE_SHIFT … #define M98090_SPK_SLAVE_WIDTH … #define M98090_MIXSPR_MIC2_MASK … #define M98090_MIXSPR_MIC2_SHIFT … #define M98090_MIXSPR_MIC2_WIDTH … #define M98090_MIXSPR_MIC1_MASK … #define M98090_MIXSPR_MIC1_SHIFT … #define M98090_MIXSPR_MIC1_WIDTH … #define M98090_MIXSPR_LINEB_MASK … #define M98090_MIXSPR_LINEB_SHIFT … #define M98090_MIXSPR_LINEB_WIDTH … #define M98090_MIXSPR_LINEA_MASK … #define M98090_MIXSPR_LINEA_SHIFT … #define M98090_MIXSPR_LINEA_WIDTH … #define M98090_MIXSPR_DACR_MASK … #define M98090_MIXSPR_DACR_SHIFT … #define M98090_MIXSPR_DACR_WIDTH … #define M98090_MIXSPR_DACL_MASK … #define M98090_MIXSPR_DACL_SHIFT … #define M98090_MIXSPR_DACL_WIDTH … #define M98090_MIXSPR_MASK … #define M98090_MIXSPR_SHIFT … #define M98090_MIXSPR_WIDTH … /* * M98090_REG_SPK_CONTROL */ #define M98090_MIXSPRG_MASK … #define M98090_MIXSPRG_SHIFT … #define M98090_MIXSPRG_WIDTH … #define M98090_MIXSPRG_NUM … #define M98090_MIXSPLG_MASK … #define M98090_MIXSPLG_SHIFT … #define M98090_MIXSPLG_WIDTH … #define M98090_MIXSPLG_NUM … /* * M98090_REG_LEFT_SPK_VOLUME */ #define M98090_SPLM_MASK … #define M98090_SPLM_SHIFT … #define M98090_SPLM_WIDTH … #define M98090_SPVOLL_MASK … #define M98090_SPVOLL_SHIFT … #define M98090_SPVOLL_WIDTH … #define M98090_SPVOLL_NUM … /* * M98090_REG_RIGHT_SPK_VOLUME */ #define M98090_SPRM_MASK … #define M98090_SPRM_SHIFT … #define M98090_SPRM_WIDTH … #define M98090_SPVOLR_MASK … #define M98090_SPVOLR_SHIFT … #define M98090_SPVOLR_WIDTH … #define M98090_SPVOLR_NUM … /* * M98090_REG_DRC_TIMING */ #define M98090_DRCEN_MASK … #define M98090_DRCEN_SHIFT … #define M98090_DRCEN_WIDTH … #define M98090_DRCEN_NUM … #define M98090_DRCRLS_MASK … #define M98090_DRCRLS_SHIFT … #define M98090_DRCRLS_WIDTH … #define M98090_DRCATK_MASK … #define M98090_DRCATK_SHIFT … #define M98090_DRCATK_WIDTH … /* * M98090_REG_DRC_COMPRESSOR */ #define M98090_DRCCMP_MASK … #define M98090_DRCCMP_SHIFT … #define M98090_DRCCMP_WIDTH … #define M98090_DRCTHC_MASK … #define M98090_DRCTHC_SHIFT … #define M98090_DRCTHC_WIDTH … #define M98090_DRCTHC_NUM … /* * M98090_REG_DRC_EXPANDER */ #define M98090_DRCEXP_MASK … #define M98090_DRCEXP_SHIFT … #define M98090_DRCEXP_WIDTH … #define M98090_DRCTHE_MASK … #define M98090_DRCTHE_SHIFT … #define M98090_DRCTHE_WIDTH … #define M98090_DRCTHE_NUM … /* * M98090_REG_DRC_GAIN */ #define M98090_DRCG_MASK … #define M98090_DRCG_SHIFT … #define M98090_DRCG_WIDTH … #define M98090_DRCG_NUM … /* * M98090_REG_RCV_LOUTL_MIXER */ #define M98090_MIXRCVL_MIC2_MASK … #define M98090_MIXRCVL_MIC2_SHIFT … #define M98090_MIXRCVL_MIC2_WIDTH … #define M98090_MIXRCVL_MIC1_MASK … #define M98090_MIXRCVL_MIC1_SHIFT … #define M98090_MIXRCVL_MIC1_WIDTH … #define M98090_MIXRCVL_LINEB_MASK … #define M98090_MIXRCVL_LINEB_SHIFT … #define M98090_MIXRCVL_LINEB_WIDTH … #define M98090_MIXRCVL_LINEA_MASK … #define M98090_MIXRCVL_LINEA_SHIFT … #define M98090_MIXRCVL_LINEA_WIDTH … #define M98090_MIXRCVL_DACR_MASK … #define M98090_MIXRCVL_DACR_SHIFT … #define M98090_MIXRCVL_DACR_WIDTH … #define M98090_MIXRCVL_DACL_MASK … #define M98090_MIXRCVL_DACL_SHIFT … #define M98090_MIXRCVL_DACL_WIDTH … #define M98090_MIXRCVL_MASK … #define M98090_MIXRCVL_SHIFT … #define M98090_MIXRCVL_WIDTH … /* * M98090_REG_RCV_LOUTL_CONTROL */ #define M98090_MIXRCVLG_MASK … #define M98090_MIXRCVLG_SHIFT … #define M98090_MIXRCVLG_WIDTH … #define M98090_MIXRCVLG_NUM … /* * M98090_REG_RCV_LOUTL_VOLUME */ #define M98090_RCVLM_MASK … #define M98090_RCVLM_SHIFT … #define M98090_RCVLM_WIDTH … #define M98090_RCVLVOL_MASK … #define M98090_RCVLVOL_SHIFT … #define M98090_RCVLVOL_WIDTH … #define M98090_RCVLVOL_NUM … /* * M98090_REG_LOUTR_MIXER */ #define M98090_LINMOD_MASK … #define M98090_LINMOD_SHIFT … #define M98090_LINMOD_WIDTH … #define M98090_MIXRCVR_MIC2_MASK … #define M98090_MIXRCVR_MIC2_SHIFT … #define M98090_MIXRCVR_MIC2_WIDTH … #define M98090_MIXRCVR_MIC1_MASK … #define M98090_MIXRCVR_MIC1_SHIFT … #define M98090_MIXRCVR_MIC1_WIDTH … #define M98090_MIXRCVR_LINEB_MASK … #define M98090_MIXRCVR_LINEB_SHIFT … #define M98090_MIXRCVR_LINEB_WIDTH … #define M98090_MIXRCVR_LINEA_MASK … #define M98090_MIXRCVR_LINEA_SHIFT … #define M98090_MIXRCVR_LINEA_WIDTH … #define M98090_MIXRCVR_DACR_MASK … #define M98090_MIXRCVR_DACR_SHIFT … #define M98090_MIXRCVR_DACR_WIDTH … #define M98090_MIXRCVR_DACL_MASK … #define M98090_MIXRCVR_DACL_SHIFT … #define M98090_MIXRCVR_DACL_WIDTH … #define M98090_MIXRCVR_MASK … #define M98090_MIXRCVR_SHIFT … #define M98090_MIXRCVR_WIDTH … /* * M98090_REG_LOUTR_CONTROL */ #define M98090_MIXRCVRG_MASK … #define M98090_MIXRCVRG_SHIFT … #define M98090_MIXRCVRG_WIDTH … #define M98090_MIXRCVRG_NUM … /* * M98090_REG_LOUTR_VOLUME */ #define M98090_RCVRM_MASK … #define M98090_RCVRM_SHIFT … #define M98090_RCVRM_WIDTH … #define M98090_RCVRVOL_MASK … #define M98090_RCVRVOL_SHIFT … #define M98090_RCVRVOL_WIDTH … #define M98090_RCVRVOL_NUM … /* * M98090_REG_JACK_DETECT */ #define M98090_JDETEN_MASK … #define M98090_JDETEN_SHIFT … #define M98090_JDETEN_WIDTH … #define M98090_JDWK_MASK … #define M98090_JDWK_SHIFT … #define M98090_JDWK_WIDTH … #define M98090_JDEB_MASK … #define M98090_JDEB_SHIFT … #define M98090_JDEB_WIDTH … #define M98090_JDEB_25MS … #define M98090_JDEB_50MS … #define M98090_JDEB_100MS … #define M98090_JDEB_200MS … /* * M98090_REG_INPUT_ENABLE */ #define M98090_MBEN_MASK … #define M98090_MBEN_SHIFT … #define M98090_MBEN_WIDTH … #define M98090_LINEAEN_MASK … #define M98090_LINEAEN_SHIFT … #define M98090_LINEAEN_WIDTH … #define M98090_LINEBEN_MASK … #define M98090_LINEBEN_SHIFT … #define M98090_LINEBEN_WIDTH … #define M98090_ADREN_MASK … #define M98090_ADREN_SHIFT … #define M98090_ADREN_WIDTH … #define M98090_ADLEN_MASK … #define M98090_ADLEN_SHIFT … #define M98090_ADLEN_WIDTH … /* * M98090_REG_OUTPUT_ENABLE */ #define M98090_HPREN_MASK … #define M98090_HPREN_SHIFT … #define M98090_HPREN_WIDTH … #define M98090_HPLEN_MASK … #define M98090_HPLEN_SHIFT … #define M98090_HPLEN_WIDTH … #define M98090_SPREN_MASK … #define M98090_SPREN_SHIFT … #define M98090_SPREN_WIDTH … #define M98090_SPLEN_MASK … #define M98090_SPLEN_SHIFT … #define M98090_SPLEN_WIDTH … #define M98090_RCVLEN_MASK … #define M98090_RCVLEN_SHIFT … #define M98090_RCVLEN_WIDTH … #define M98090_RCVREN_MASK … #define M98090_RCVREN_SHIFT … #define M98090_RCVREN_WIDTH … #define M98090_DAREN_MASK … #define M98090_DAREN_SHIFT … #define M98090_DAREN_WIDTH … #define M98090_DALEN_MASK … #define M98090_DALEN_SHIFT … #define M98090_DALEN_WIDTH … /* * M98090_REG_LEVEL_CONTROL */ #define M98090_ZDENN_MASK … #define M98090_ZDENN_SHIFT … #define M98090_ZDENN_WIDTH … #define M98090_ZDENN_NUM … #define M98090_VS2ENN_MASK … #define M98090_VS2ENN_SHIFT … #define M98090_VS2ENN_WIDTH … #define M98090_VS2ENN_NUM … #define M98090_VSENN_MASK … #define M98090_VSENN_SHIFT … #define M98090_VSENN_WIDTH … #define M98090_VSENN_NUM … /* * M98090_REG_DSP_FILTER_ENABLE */ #define M98090_DMIC34BQEN_MASK … #define M98090_DMIC34BQEN_SHIFT … #define M98090_DMIC34BQEN_WIDTH … #define M98090_DMIC34BQEN_NUM … #define M98090_ADCBQEN_MASK … #define M98090_ADCBQEN_SHIFT … #define M98090_ADCBQEN_WIDTH … #define M98090_ADCBQEN_NUM … #define M98090_EQ3BANDEN_MASK … #define M98090_EQ3BANDEN_SHIFT … #define M98090_EQ3BANDEN_WIDTH … #define M98090_EQ3BANDEN_NUM … #define M98090_EQ5BANDEN_MASK … #define M98090_EQ5BANDEN_SHIFT … #define M98090_EQ5BANDEN_WIDTH … #define M98090_EQ5BANDEN_NUM … #define M98090_EQ7BANDEN_MASK … #define M98090_EQ7BANDEN_SHIFT … #define M98090_EQ7BANDEN_WIDTH … #define M98090_EQ7BANDEN_NUM … /* * M98090_REG_BIAS_CONTROL */ #define M98090_VCM_MODE_MASK … #define M98090_VCM_MODE_SHIFT … #define M98090_VCM_MODE_WIDTH … #define M98090_VCM_MODE_NUM … /* * M98090_REG_DAC_CONTROL */ #define M98090_PERFMODE_MASK … #define M98090_PERFMODE_SHIFT … #define M98090_PERFMODE_WIDTH … #define M98090_PERFMODE_NUM … #define M98090_DACHP_MASK … #define M98090_DACHP_SHIFT … #define M98090_DACHP_WIDTH … #define M98090_DACHP_NUM … /* * M98090_REG_ADC_CONTROL */ #define M98090_OSR128_MASK … #define M98090_OSR128_SHIFT … #define M98090_OSR128_WIDTH … #define M98090_ADCDITHER_MASK … #define M98090_ADCDITHER_SHIFT … #define M98090_ADCDITHER_WIDTH … #define M98090_ADCDITHER_NUM … #define M98090_ADCHP_MASK … #define M98090_ADCHP_SHIFT … #define M98090_ADCHP_WIDTH … #define M98090_ADCHP_NUM … /* * M98090_REG_DEVICE_SHUTDOWN */ #define M98090_SHDNN_MASK … #define M98090_SHDNN_SHIFT … #define M98090_SHDNN_WIDTH … /* * M98090_REG_EQUALIZER_BASE */ #define M98090_B0_1_HI_MASK … #define M98090_B0_1_HI_SHIFT … #define M98090_B0_1_HI_WIDTH … #define M98090_B0_1_MID_MASK … #define M98090_B0_1_MID_SHIFT … #define M98090_B0_1_MID_WIDTH … #define M98090_B0_1_LO_MASK … #define M98090_B0_1_LO_SHIFT … #define M98090_B0_1_LO_WIDTH … #define M98090_B1_1_HI_MASK … #define M98090_B1_1_HI_SHIFT … #define M98090_B1_1_HI_WIDTH … #define M98090_B1_1_MID_MASK … #define M98090_B1_1_MID_SHIFT … #define M98090_B1_1_MID_WIDTH … #define M98090_B1_1_LO_MASK … #define M98090_B1_1_LO_SHIFT … #define M98090_B1_1_LO_WIDTH … #define M98090_B2_1_HI_MASK … #define M98090_B2_1_HI_SHIFT … #define M98090_B2_1_HI_WIDTH … #define M98090_B2_1_MID_MASK … #define M98090_B2_1_MID_SHIFT … #define M98090_B2_1_MID_WIDTH … #define M98090_B2_1_LO_MASK … #define M98090_B2_1_LO_SHIFT … #define M98090_B2_1_LO_WIDTH … #define M98090_A1_1_HI_MASK … #define M98090_A1_1_HI_SHIFT … #define M98090_A1_1_HI_WIDTH … #define M98090_A1_1_MID_MASK … #define M98090_A1_1_MID_SHIFT … #define M98090_A1_1_MID_WIDTH … #define M98090_A1_1_LO_MASK … #define M98090_A1_1_LO_SHIFT … #define M98090_A1_1_LO_WIDTH … #define M98090_A2_1_HI_MASK … #define M98090_A2_1_HI_SHIFT … #define M98090_A2_1_HI_WIDTH … #define M98090_A2_1_MID_MASK … #define M98090_A2_1_MID_SHIFT … #define M98090_A2_1_MID_WIDTH … #define M98090_A2_1_LO_MASK … #define M98090_A2_1_LO_SHIFT … #define M98090_A2_1_LO_WIDTH … #define M98090_COEFS_PER_BAND … #define M98090_COEFS_BLK_SZ … #define M98090_COEFS_MAX_SZ … /* * M98090_REG_RECORD_BIQUAD_BASE */ #define M98090_REC_B0_HI_MASK … #define M98090_REC_B0_HI_SHIFT … #define M98090_REC_B0_HI_WIDTH … #define M98090_REC_B0_MID_MASK … #define M98090_REC_B0_MID_SHIFT … #define M98090_REC_B0_MID_WIDTH … #define M98090_REC_B0_LO_MASK … #define M98090_REC_B0_LO_SHIFT … #define M98090_REC_B0_LO_WIDTH … #define M98090_REC_B1_HI_MASK … #define M98090_REC_B1_HI_SHIFT … #define M98090_REC_B1_HI_WIDTH … #define M98090_REC_B1_MID_MASK … #define M98090_REC_B1_MID_SHIFT … #define M98090_REC_B1_MID_WIDTH … #define M98090_REC_B1_LO_MASK … #define M98090_REC_B1_LO_SHIFT … #define M98090_REC_B1_LO_WIDTH … #define M98090_REC_B2_HI_MASK … #define M98090_REC_B2_HI_SHIFT … #define M98090_REC_B2_HI_WIDTH … #define M98090_REC_B2_MID_MASK … #define M98090_REC_B2_MID_SHIFT … #define M98090_REC_B2_MID_WIDTH … #define M98090_REC_B2_LO_MASK … #define M98090_REC_B2_LO_SHIFT … #define M98090_REC_B2_LO_WIDTH … #define M98090_REC_A1_HI_MASK … #define M98090_REC_A1_HI_SHIFT … #define M98090_REC_A1_HI_WIDTH … #define M98090_REC_A1_MID_MASK … #define M98090_REC_A1_MID_SHIFT … #define M98090_REC_A1_MID_WIDTH … #define M98090_REC_A1_LO_MASK … #define M98090_REC_A1_LO_SHIFT … #define M98090_REC_A1_LO_WIDTH … #define M98090_REC_A2_HI_MASK … #define M98090_REC_A2_HI_SHIFT … #define M98090_REC_A2_HI_WIDTH … #define M98090_REC_A2_MID_MASK … #define M98090_REC_A2_MID_SHIFT … #define M98090_REC_A2_MID_WIDTH … #define M98090_REC_A2_LO_MASK … #define M98090_REC_A2_LO_SHIFT … #define M98090_REC_A2_LO_WIDTH … /* * M98090_REG_DMIC3_VOLUME */ #define M98090_DMIC_AV3G_MASK … #define M98090_DMIC_AV3G_SHIFT … #define M98090_DMIC_AV3G_WIDTH … #define M98090_DMIC_AV3G_NUM … #define M98090_DMIC_AV3_MASK … #define M98090_DMIC_AV3_SHIFT … #define M98090_DMIC_AV3_WIDTH … #define M98090_DMIC_AV3_NUM … /* * M98090_REG_DMIC4_VOLUME */ #define M98090_DMIC_AV4G_MASK … #define M98090_DMIC_AV4G_SHIFT … #define M98090_DMIC_AV4G_WIDTH … #define M98090_DMIC_AV4G_NUM … #define M98090_DMIC_AV4_MASK … #define M98090_DMIC_AV4_SHIFT … #define M98090_DMIC_AV4_WIDTH … #define M98090_DMIC_AV4_NUM … /* * M98090_REG_DMIC34_BQ_PREATTEN */ #define M98090_AV34BQ_MASK … #define M98090_AV34BQ_SHIFT … #define M98090_AV34BQ_WIDTH … #define M98090_AV34BQ_NUM … /* * M98090_REG_RECORD_TDM_SLOT */ #define M98090_TDM_SLOTADCL_MASK … #define M98090_TDM_SLOTADCL_SHIFT … #define M98090_TDM_SLOTADCL_WIDTH … #define M98090_TDM_SLOTADCL_NUM … #define M98090_TDM_SLOTADCR_MASK … #define M98090_TDM_SLOTADCR_SHIFT … #define M98090_TDM_SLOTADCR_WIDTH … #define M98090_TDM_SLOTADCR_NUM … #define M98090_TDM_SLOTDMIC3_MASK … #define M98090_TDM_SLOTDMIC3_SHIFT … #define M98090_TDM_SLOTDMIC3_WIDTH … #define M98090_TDM_SLOTDMIC3_NUM … #define M98090_TDM_SLOTDMIC4_MASK … #define M98090_TDM_SLOTDMIC4_SHIFT … #define M98090_TDM_SLOTDMIC4_WIDTH … #define M98090_TDM_SLOTDMIC4_NUM … /* * M98090_REG_SAMPLE_RATE */ #define M98090_DMIC34_ZEROPAD_MASK … #define M98090_DMIC34_ZEROPAD_SHIFT … #define M98090_DMIC34_ZEROPAD_WIDTH … #define M98090_DMIC34_ZEROPAD_NUM … #define M98090_DMIC34_SRDIV_MASK … #define M98090_DMIC34_SRDIV_SHIFT … #define M98090_DMIC34_SRDIV_WIDTH … /* * M98090_REG_DMIC34_BIQUAD_BASE */ #define M98090_DMIC34_B0_HI_MASK … #define M98090_DMIC34_B0_HI_SHIFT … #define M98090_DMIC34_B0_HI_WIDTH … #define M98090_DMIC34_B0_MID_MASK … #define M98090_DMIC34_B0_MID_SHIFT … #define M98090_DMIC34_B0_MID_WIDTH … #define M98090_DMIC34_B0_LO_MASK … #define M98090_DMIC34_B0_LO_SHIFT … #define M98090_DMIC34_B0_LO_WIDTH … #define M98090_DMIC34_B1_HI_MASK … #define M98090_DMIC34_B1_HI_SHIFT … #define M98090_DMIC34_B1_HI_WIDTH … #define M98090_DMIC34_B1_MID_MASK … #define M98090_DMIC34_B1_MID_SHIFT … #define M98090_DMIC34_B1_MID_WIDTH … #define M98090_DMIC34_B1_LO_MASK … #define M98090_DMIC34_B1_LO_SHIFT … #define M98090_DMIC34_B1_LO_WIDTH … #define M98090_DMIC34_B2_HI_MASK … #define M98090_DMIC34_B2_HI_SHIFT … #define M98090_DMIC34_B2_HI_WIDTH … #define M98090_DMIC34_B2_MID_MASK … #define M98090_DMIC34_B2_MID_SHIFT … #define M98090_DMIC34_B2_MID_WIDTH … #define M98090_DMIC34_B2_LO_MASK … #define M98090_DMIC34_B2_LO_SHIFT … #define M98090_DMIC34_B2_LO_WIDTH … #define M98090_DMIC34_A1_HI_MASK … #define M98090_DMIC34_A1_HI_SHIFT … #define M98090_DMIC34_A1_HI_WIDTH … #define M98090_DMIC34_A1_MID_MASK … #define M98090_DMIC34_A1_MID_SHIFT … #define M98090_DMIC34_A1_MID_WIDTH … #define M98090_DMIC34_A1_LO_MASK … #define M98090_DMIC34_A1_LO_SHIFT … #define M98090_DMIC34_A1_LO_WIDTH … #define M98090_DMIC34_A2_HI_MASK … #define M98090_DMIC34_A2_HI_SHIFT … #define M98090_DMIC34_A2_HI_WIDTH … #define M98090_DMIC34_A2_MID_MASK … #define M98090_DMIC34_A2_MID_SHIFT … #define M98090_DMIC34_A2_MID_WIDTH … #define M98090_DMIC34_A2_LO_MASK … #define M98090_DMIC34_A2_LO_SHIFT … #define M98090_DMIC34_A2_LO_WIDTH … #define M98090_JACK_STATE_NO_HEADSET … #define M98090_JACK_STATE_NO_HEADSET_2 … #define M98090_JACK_STATE_HEADPHONE … #define M98090_JACK_STATE_HEADSET … /* * M98090_REG_REVISION_ID */ #define M98090_REVID_MASK … #define M98090_REVID_SHIFT … #define M98090_REVID_WIDTH … #define M98090_REVID_NUM … /* Silicon revision number */ #define M98090_REVA … #define M98091_REVA … enum max98090_type { … }; struct max98090_cdata { … }; struct max98090_priv { … }; int max98090_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack); #endif
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