/* SPDX-License-Identifier: GPL-2.0-only */ /* * max98088.h -- MAX98088 ALSA SoC Audio driver * * Copyright 2010 Maxim Integrated Products */ #ifndef _MAX98088_H #define _MAX98088_H /* * MAX98088 Registers Definition */ #define M98088_REG_00_IRQ_STATUS … #define M98088_REG_01_MIC_STATUS … #define M98088_REG_02_JACK_STATUS … #define M98088_REG_03_BATTERY_VOLTAGE … #define M98088_REG_0F_IRQ_ENABLE … #define M98088_REG_10_SYS_CLK … #define M98088_REG_11_DAI1_CLKMODE … #define M98088_REG_12_DAI1_CLKCFG_HI … #define M98088_REG_13_DAI1_CLKCFG_LO … #define M98088_REG_14_DAI1_FORMAT … #define M98088_REG_15_DAI1_CLOCK … #define M98088_REG_16_DAI1_IOCFG … #define M98088_REG_17_DAI1_TDM … #define M98088_REG_18_DAI1_FILTERS … #define M98088_REG_19_DAI2_CLKMODE … #define M98088_REG_1A_DAI2_CLKCFG_HI … #define M98088_REG_1B_DAI2_CLKCFG_LO … #define M98088_REG_1C_DAI2_FORMAT … #define M98088_REG_1D_DAI2_CLOCK … #define M98088_REG_1E_DAI2_IOCFG … #define M98088_REG_1F_DAI2_TDM … #define M98088_REG_20_DAI2_FILTERS … #define M98088_REG_21_SRC … #define M98088_REG_22_MIX_DAC … #define M98088_REG_23_MIX_ADC_LEFT … #define M98088_REG_24_MIX_ADC_RIGHT … #define M98088_REG_25_MIX_HP_LEFT … #define M98088_REG_26_MIX_HP_RIGHT … #define M98088_REG_27_MIX_HP_CNTL … #define M98088_REG_28_MIX_REC_LEFT … #define M98088_REG_29_MIX_REC_RIGHT … #define M98088_REG_2A_MIC_REC_CNTL … #define M98088_REG_2B_MIX_SPK_LEFT … #define M98088_REG_2C_MIX_SPK_RIGHT … #define M98088_REG_2D_MIX_SPK_CNTL … #define M98088_REG_2E_LVL_SIDETONE … #define M98088_REG_2F_LVL_DAI1_PLAY … #define M98088_REG_30_LVL_DAI1_PLAY_EQ … #define M98088_REG_31_LVL_DAI2_PLAY … #define M98088_REG_32_LVL_DAI2_PLAY_EQ … #define M98088_REG_33_LVL_ADC_L … #define M98088_REG_34_LVL_ADC_R … #define M98088_REG_35_LVL_MIC1 … #define M98088_REG_36_LVL_MIC2 … #define M98088_REG_37_LVL_INA … #define M98088_REG_38_LVL_INB … #define M98088_REG_39_LVL_HP_L … #define M98088_REG_3A_LVL_HP_R … #define M98088_REG_3B_LVL_REC_L … #define M98088_REG_3C_LVL_REC_R … #define M98088_REG_3D_LVL_SPK_L … #define M98088_REG_3E_LVL_SPK_R … #define M98088_REG_3F_MICAGC_CFG … #define M98088_REG_40_MICAGC_THRESH … #define M98088_REG_41_SPKDHP … #define M98088_REG_42_SPKDHP_THRESH … #define M98088_REG_43_SPKALC_COMP … #define M98088_REG_44_PWRLMT_CFG … #define M98088_REG_45_PWRLMT_TIME … #define M98088_REG_46_THDLMT_CFG … #define M98088_REG_47_CFG_AUDIO_IN … #define M98088_REG_48_CFG_MIC … #define M98088_REG_49_CFG_LEVEL … #define M98088_REG_4A_CFG_BYPASS … #define M98088_REG_4B_CFG_JACKDET … #define M98088_REG_4C_PWR_EN_IN … #define M98088_REG_4D_PWR_EN_OUT … #define M98088_REG_4E_BIAS_CNTL … #define M98088_REG_4F_DAC_BIAS1 … #define M98088_REG_50_DAC_BIAS2 … #define M98088_REG_51_PWR_SYS … #define M98088_REG_52_DAI1_EQ_BASE … #define M98088_REG_84_DAI2_EQ_BASE … #define M98088_REG_B6_DAI1_BIQUAD_BASE … #define M98088_REG_C0_DAI2_BIQUAD_BASE … #define M98088_REG_FF_REV_ID … #define M98088_REG_CNT … /* MAX98088 Registers Bit Fields */ /* M98088_REG_11_DAI1_CLKMODE, M98088_REG_19_DAI2_CLKMODE */ #define M98088_CLKMODE_MASK … /* M98088_REG_14_DAI1_FORMAT, M98088_REG_1C_DAI2_FORMAT */ #define M98088_DAI_MAS … #define M98088_DAI_WCI … #define M98088_DAI_BCI … #define M98088_DAI_DLY … #define M98088_DAI_TDM … #define M98088_DAI_FSW … #define M98088_DAI_WS … /* M98088_REG_15_DAI1_CLOCK, M98088_REG_1D_DAI2_CLOCK */ #define M98088_DAI_BSEL64 … #define M98088_DAI_OSR64 … /* M98088_REG_16_DAI1_IOCFG, M98088_REG_1E_DAI2_IOCFG */ #define M98088_S1NORMAL … #define M98088_S2NORMAL … #define M98088_SDATA … /* M98088_REG_18_DAI1_FILTERS, M98088_REG_20_DAI2_FILTERS */ #define M98088_DAI_DHF … /* M98088_REG_22_MIX_DAC */ #define M98088_DAI1L_TO_DACL … #define M98088_DAI1R_TO_DACL … #define M98088_DAI2L_TO_DACL … #define M98088_DAI2R_TO_DACL … #define M98088_DAI1L_TO_DACR … #define M98088_DAI1R_TO_DACR … #define M98088_DAI2L_TO_DACR … #define M98088_DAI2R_TO_DACR … /* M98088_REG_2A_MIC_REC_CNTL */ #define M98088_REC_LINEMODE … #define M98088_REC_LINEMODE_MASK … /* M98088_REG_2D_MIX_SPK_CNTL */ #define M98088_MIX_SPKR_GAIN_MASK … #define M98088_MIX_SPKR_GAIN_SHIFT … #define M98088_MIX_SPKL_GAIN_MASK … #define M98088_MIX_SPKL_GAIN_SHIFT … /* M98088_REG_2F_LVL_DAI1_PLAY, M98088_REG_31_LVL_DAI2_PLAY */ #define M98088_DAI_MUTE … #define M98088_DAI_MUTE_MASK … #define M98088_DAI_VOICE_GAIN_MASK … #define M98088_DAI_ATTENUATION_MASK … #define M98088_DAI_ATTENUATION_SHIFT … /* M98088_REG_35_LVL_MIC1, M98088_REG_36_LVL_MIC2 */ #define M98088_MICPRE_MASK … #define M98088_MICPRE_SHIFT … /* M98088_REG_3A_LVL_HP_R */ #define M98088_HP_MUTE … /* M98088_REG_3C_LVL_REC_R */ #define M98088_REC_MUTE … /* M98088_REG_3E_LVL_SPK_R */ #define M98088_SP_MUTE … /* M98088_REG_48_CFG_MIC */ #define M98088_EXTMIC_MASK … #define M98088_DIGMIC_L … #define M98088_DIGMIC_R … /* M98088_REG_49_CFG_LEVEL */ #define M98088_VSEN … #define M98088_ZDEN … #define M98088_EQ2EN … #define M98088_EQ1EN … /* M98088_REG_4C_PWR_EN_IN */ #define M98088_INAEN … #define M98088_INBEN … #define M98088_MBEN … #define M98088_ADLEN … #define M98088_ADREN … /* M98088_REG_4D_PWR_EN_OUT */ #define M98088_HPLEN … #define M98088_HPREN … #define M98088_HPEN … #define M98088_SPLEN … #define M98088_SPREN … #define M98088_RECEN … #define M98088_DALEN … #define M98088_DAREN … /* M98088_REG_51_PWR_SYS */ #define M98088_SHDNRUN … #define M98088_PERFMODE … #define M98088_HPPLYBACK … #define M98088_PWRSV8K … #define M98088_PWRSV … /* Line inputs */ #define LINE_INA … #define LINE_INB … #define M98088_COEFS_PER_BAND … #define M98088_BYTE1(w) … #define M98088_BYTE0(w) … #endif
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