#ifndef _MAX98373_H
#define _MAX98373_H
#define MAX98373_R2000_SW_RESET …
#define MAX98373_R2001_INT_RAW1 …
#define MAX98373_R2002_INT_RAW2 …
#define MAX98373_R2003_INT_RAW3 …
#define MAX98373_R2004_INT_STATE1 …
#define MAX98373_R2005_INT_STATE2 …
#define MAX98373_R2006_INT_STATE3 …
#define MAX98373_R2007_INT_FLAG1 …
#define MAX98373_R2008_INT_FLAG2 …
#define MAX98373_R2009_INT_FLAG3 …
#define MAX98373_R200A_INT_EN1 …
#define MAX98373_R200B_INT_EN2 …
#define MAX98373_R200C_INT_EN3 …
#define MAX98373_R200D_INT_FLAG_CLR1 …
#define MAX98373_R200E_INT_FLAG_CLR2 …
#define MAX98373_R200F_INT_FLAG_CLR3 …
#define MAX98373_R2010_IRQ_CTRL …
#define MAX98373_R2014_THERM_WARN_THRESH …
#define MAX98373_R2015_THERM_SHDN_THRESH …
#define MAX98373_R2016_THERM_HYSTERESIS …
#define MAX98373_R2017_THERM_FOLDBACK_SET …
#define MAX98373_R2018_THERM_FOLDBACK_EN …
#define MAX98373_R201E_PIN_DRIVE_STRENGTH …
#define MAX98373_R2020_PCM_TX_HIZ_EN_1 …
#define MAX98373_R2021_PCM_TX_HIZ_EN_2 …
#define MAX98373_R2022_PCM_TX_SRC_1 …
#define MAX98373_R2023_PCM_TX_SRC_2 …
#define MAX98373_R2024_PCM_DATA_FMT_CFG …
#define MAX98373_R2025_AUDIO_IF_MODE …
#define MAX98373_R2026_PCM_CLOCK_RATIO …
#define MAX98373_R2027_PCM_SR_SETUP_1 …
#define MAX98373_R2028_PCM_SR_SETUP_2 …
#define MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1 …
#define MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2 …
#define MAX98373_R202B_PCM_RX_EN …
#define MAX98373_R202C_PCM_TX_EN …
#define MAX98373_R202E_ICC_RX_CH_EN_1 …
#define MAX98373_R202F_ICC_RX_CH_EN_2 …
#define MAX98373_R2030_ICC_TX_HIZ_EN_1 …
#define MAX98373_R2031_ICC_TX_HIZ_EN_2 …
#define MAX98373_R2032_ICC_LINK_EN_CFG …
#define MAX98373_R2034_ICC_TX_CNTL …
#define MAX98373_R2035_ICC_TX_EN …
#define MAX98373_R2036_SOUNDWIRE_CTRL …
#define MAX98373_R203D_AMP_DIG_VOL_CTRL …
#define MAX98373_R203E_AMP_PATH_GAIN …
#define MAX98373_R203F_AMP_DSP_CFG …
#define MAX98373_R2040_TONE_GEN_CFG …
#define MAX98373_R2041_AMP_CFG …
#define MAX98373_R2042_AMP_EDGE_RATE_CFG …
#define MAX98373_R2043_AMP_EN …
#define MAX98373_R2046_IV_SENSE_ADC_DSP_CFG …
#define MAX98373_R2047_IV_SENSE_ADC_EN …
#define MAX98373_R2051_MEAS_ADC_SAMPLING_RATE …
#define MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG …
#define MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG …
#define MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK …
#define MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK …
#define MAX98373_R2056_MEAS_ADC_PVDD_CH_EN …
#define MAX98373_R2090_BDE_LVL_HOLD …
#define MAX98373_R2091_BDE_GAIN_ATK_REL_RATE …
#define MAX98373_R2092_BDE_CLIPPER_MODE …
#define MAX98373_R2097_BDE_L1_THRESH …
#define MAX98373_R2098_BDE_L2_THRESH …
#define MAX98373_R2099_BDE_L3_THRESH …
#define MAX98373_R209A_BDE_L4_THRESH …
#define MAX98373_R209B_BDE_THRESH_HYST …
#define MAX98373_R20A8_BDE_L1_CFG_1 …
#define MAX98373_R20A9_BDE_L1_CFG_2 …
#define MAX98373_R20AA_BDE_L1_CFG_3 …
#define MAX98373_R20AB_BDE_L2_CFG_1 …
#define MAX98373_R20AC_BDE_L2_CFG_2 …
#define MAX98373_R20AD_BDE_L2_CFG_3 …
#define MAX98373_R20AE_BDE_L3_CFG_1 …
#define MAX98373_R20AF_BDE_L3_CFG_2 …
#define MAX98373_R20B0_BDE_L3_CFG_3 …
#define MAX98373_R20B1_BDE_L4_CFG_1 …
#define MAX98373_R20B2_BDE_L4_CFG_2 …
#define MAX98373_R20B3_BDE_L4_CFG_3 …
#define MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE …
#define MAX98373_R20B5_BDE_EN …
#define MAX98373_R20B6_BDE_CUR_STATE_READBACK …
#define MAX98373_R20D1_DHT_CFG …
#define MAX98373_R20D2_DHT_ATTACK_CFG …
#define MAX98373_R20D3_DHT_RELEASE_CFG …
#define MAX98373_R20D4_DHT_EN …
#define MAX98373_R20E0_LIMITER_THRESH_CFG …
#define MAX98373_R20E1_LIMITER_ATK_REL_RATES …
#define MAX98373_R20E2_LIMITER_EN …
#define MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG …
#define MAX98373_R20FF_GLOBAL_SHDN …
#define MAX98373_R21FF_REV_ID …
#define MAX98373_PCM_TX_CH_SRC_A_V_SHIFT …
#define MAX98373_PCM_TX_CH_SRC_A_I_SHIFT …
#define MAX98373_PCM_MODE_CFG_FORMAT_MASK …
#define MAX98373_PCM_MODE_CFG_FORMAT_SHIFT …
#define MAX98373_PCM_TX_CH_INTERLEAVE_MASK …
#define MAX98373_PCM_FORMAT_I2S …
#define MAX98373_PCM_FORMAT_LJ …
#define MAX98373_PCM_FORMAT_TDM_MODE0 …
#define MAX98373_PCM_FORMAT_TDM_MODE1 …
#define MAX98373_PCM_FORMAT_TDM_MODE2 …
#define MAX98373_PCM_MODE_CFG_CHANSZ_MASK …
#define MAX98373_PCM_MODE_CFG_CHANSZ_16 …
#define MAX98373_PCM_MODE_CFG_CHANSZ_24 …
#define MAX98373_PCM_MODE_CFG_CHANSZ_32 …
#define MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE …
#define MAX98373_PCM_CLK_SETUP_BSEL_MASK …
#define MAX98373_PCM_SR_SET1_SR_MASK …
#define MAX98373_PCM_SR_SET1_SR_8000 …
#define MAX98373_PCM_SR_SET1_SR_11025 …
#define MAX98373_PCM_SR_SET1_SR_12000 …
#define MAX98373_PCM_SR_SET1_SR_16000 …
#define MAX98373_PCM_SR_SET1_SR_22050 …
#define MAX98373_PCM_SR_SET1_SR_24000 …
#define MAX98373_PCM_SR_SET1_SR_32000 …
#define MAX98373_PCM_SR_SET1_SR_44100 …
#define MAX98373_PCM_SR_SET1_SR_48000 …
#define MAX98373_PCM_SR_SET1_SR_88200 …
#define MAX98373_PCM_SR_SET1_SR_96000 …
#define MAX98373_PCM_SR_SET2_SR_MASK …
#define MAX98373_PCM_SR_SET2_SR_SHIFT …
#define MAX98373_PCM_SR_SET2_IVADC_SR_MASK …
#define MAX98373_PCM_TO_SPK_MONOMIX_CFG_MASK …
#define MAX98373_PCM_TO_SPK_MONOMIX_CFG_SHIFT …
#define MAX98373_PCM_TO_SPK_CH0_SRC_MASK …
#define MAX98373_SPK_DIGI_GAIN_MASK …
#define MAX98373_SPK_DIGI_GAIN_SHIFT …
#define MAX98373_FS_GAIN_MAX_MASK …
#define MAX98373_FS_GAIN_MAX_SHIFT …
#define MAX98373_AMP_DSP_CFG_DCBLK_SHIFT …
#define MAX98373_AMP_DSP_CFG_DITH_SHIFT …
#define MAX98373_AMP_DSP_CFG_RMP_UP_SHIFT …
#define MAX98373_AMP_DSP_CFG_RMP_DN_SHIFT …
#define MAX98373_AMP_DSP_CFG_DAC_INV_SHIFT …
#define MAX98373_AMP_VOL_SEL_SHIFT …
#define MAX98373_SPKFB_EN_MASK …
#define MAX98373_SPK_EN_MASK …
#define MAX98373_SPKFB_EN_SHIFT …
#define MAX98373_FLT_EN_SHIFT …
#define MAX98373_LVL4_MUTE_EN_SHIFT …
#define MAX98373_LVL4_HOLD_EN_SHIFT …
#define MAX98373_BDE_EN_SHIFT …
#define MAX98373_DHT_SPK_GAIN_MIN_SHIFT …
#define MAX98373_DHT_ROT_PNT_SHIFT …
#define MAX98373_DHT_ATTACK_STEP_SHIFT …
#define MAX98373_DHT_ATTACK_RATE_SHIFT …
#define MAX98373_DHT_RELEASE_STEP_SHIFT …
#define MAX98373_DHT_RELEASE_RATE_SHIFT …
#define MAX98373_DHT_EN_SHIFT …
#define MAX98373_LIMITER_THRESH_SHIFT …
#define MAX98373_LIMITER_THRESH_SRC_SHIFT …
#define MAX98373_LIMITER_EN_SHIFT …
#define MAX98373_OVC_AUTORESTART_SHIFT …
#define MAX98373_THERM_AUTORESTART_SHIFT …
#define MAX98373_CMON_AUTORESTART_SHIFT …
#define MAX98373_CLOCK_MON_SHIFT …
#define MAX98373_GLOBAL_EN_MASK …
#define MAX98373_SOFT_RESET …
struct max98373_cache { … };
struct max98373_priv { … };
extern const struct snd_soc_component_driver soc_codec_dev_max98373;
extern const struct snd_soc_component_driver soc_codec_dev_max98373_sdw;
void max98373_reset(struct max98373_priv *max98373, struct device *dev);
void max98373_slot_config(struct device *dev,
struct max98373_priv *max98373);
#endif