/* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright (c) 2020 Maxim Integrated */ #ifndef _MAX98373_SDW_H #define _MAX98373_SDW_H #include "max98373.h" /* SoundWire Slave Control Port (SCP) */ #define MAX98373_R0040_SCP_INIT_STAT_1 … #define MAX98373_R0041_SCP_INIT_MASK_1 … #define MAX98373_R0042_SCP_INIT_STAT_2 … #define MAX98373_R0044_SCP_CTRL … #define MAX98373_R0045_SCP_SYSTEM_CTRL … #define MAX98373_R0046_SCP_DEV_NUMBER … #define MAX98373_R0050_SCP_DEV_ID_0 … #define MAX98373_R0051_SCP_DEV_ID_1 … #define MAX98373_R0052_SCP_DEV_ID_2 … #define MAX98373_R0053_SCP_DEV_ID_3 … #define MAX98373_R0054_SCP_DEV_ID_4 … #define MAX98373_R0055_SCP_DEV_ID_5 … #define MAX98373_R0060_SCP_FRAME_CTLR … #define MAX98373_R0070_SCP_FRAME_CTLR … /* SoundWire Device Data Port (DP) */ /* Data Port 1 Registers */ #define MAX98373_R0100_DP1_INIT_STAT … #define MAX98373_R0101_DP1_INIT_MASK … #define MAX98373_R0102_DP1_PORT_CTRL … #define MAX98373_R0103_DP1_BLOCK_CTRL_1 … #define MAX98373_R0104_DP1_PREPARE_STATUS … #define MAX98373_R0105_DP1_PREPARE_CTRL … /* Data Port 1 Bank 0 Registers */ #define MAX98373_R0120_DP1_CHANNEL_EN … #define MAX98373_R0122_DP1_SAMPLE_CTRL1 … #define MAX98373_R0123_DP1_SAMPLE_CTRL2 … #define MAX98373_R0124_DP1_OFFSET_CTRL1 … #define MAX98373_R0125_DP1_OFFSET_CTRL2 … #define MAX98373_R0126_DP1_HCTRL … #define MAX98373_R0127_DP1_BLOCK_CTRL3 … /* Data Port 1 Bank 1 Registers */ #define MAX98373_R0130_DP1_CHANNEL_EN … #define MAX98373_R0132_DP1_SAMPLE_CTRL1 … #define MAX98373_R0133_DP1_SAMPLE_CTRL2 … #define MAX98373_R0134_DP1_OFFSET_CTRL1 … #define MAX98373_R0135_DP1_OFFSET_CTRL2 … #define MAX98373_R0136_DP1_HCTRL … #define MAX98373_R0137_DP1_BLOCK_CTRL3 … /* Data Port 3 Registers */ #define MAX98373_R0300_DP3_INIT_STAT … #define MAX98373_R0301_DP3_INIT_MASK … #define MAX98373_R0302_DP3_PORT_CTRL … #define MAX98373_R0303_DP3_BLOCK_CTRL_1 … #define MAX98373_R0304_DP3_PREPARE_STATUS … #define MAX98373_R0305_DP3_PREPARE_CTRL … /* Data Port 3 Bank 0 Registers */ #define MAX98373_R0320_DP3_CHANNEL_EN … #define MAX98373_R0322_DP3_SAMPLE_CTRL1 … #define MAX98373_R0323_DP3_SAMPLE_CTRL2 … #define MAX98373_R0324_DP3_OFFSET_CTRL1 … #define MAX98373_R0325_DP3_OFFSET_CTRL2 … #define MAX98373_R0326_DP3_HCTRL … #define MAX98373_R0327_DP3_BLOCK_CTRL3 … /* Data Port 3 Bank 1 Registers */ #define MAX98373_R0330_DP3_CHANNEL_EN … #define MAX98373_R0332_DP3_SAMPLE_CTRL1 … #define MAX98373_R0333_DP3_SAMPLE_CTRL2 … #define MAX98373_R0334_DP3_OFFSET_CTRL1 … #define MAX98373_R0335_DP3_OFFSET_CTRL2 … #define MAX98373_R0336_DP3_HCTRL … #define MAX98373_R0337_DP3_BLOCK_CTRL3 … #endif
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